From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C402C26D4E7; Tue, 5 Aug 2025 15:03:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406196; cv=none; b=iuSXVC82rIlDgNcUwB7in7rL18wiqZI2ZTci1IcTRWDfkNBMYHHX3ODR19wXjrnAZY3dIWplQegpgHnH0JntQeV3Oz2LGqiWJh1Q8tW/y6MsG9UdoXN4IXfTVco0NTXdjfwuA2kxtgfkkFVIWGCCh4erU5UAufhMam3hMFyxC0E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406196; c=relaxed/simple; bh=jVzBHlFKVGvMLz6WNe8g4/6jarkLbASjdSO7FeJiugU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qlXhBwwAmPbZUCFLm+2WRmzQV3sM53JDzOYmnmDikX5JmU2Ah01l1lDem2k/z8h68JaX/QfcMct346nMSaRR3F9EYJh/D6DY6aBlzaAOCb18IGt1RNqpua65rusmEaybQrhR2pvOi/TOUqtbkRKa4ydva0TcbtmkwXSH3ISXstw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=DOJ5Rb7F; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="DOJ5Rb7F" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 0CA6225F17; Tue, 5 Aug 2025 17:03:12 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id XSytV74AFPED; Tue, 5 Aug 2025 17:03:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754406191; bh=jVzBHlFKVGvMLz6WNe8g4/6jarkLbASjdSO7FeJiugU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=DOJ5Rb7FZ6ohSjzXK8mEQdTvdHh/vMD2RnZa+aJ+YHPcYgyHYwOccbeY7olj1fu5a ruHUYK52HvEwY/RmXIXxTVa1QpsMXYXbbBh/IT99uuCzoj33XG94zMGZUt2ux21d8K IT1AaIXHt31Z5V8oq9hob04vr/vtI5b+1EGSqqsPw/NOnuEABgb9iRZrVJG6phgAlf 1RqFqKFDhyyH1OW6Op+3TEu/Ni9MRHDQKtytDuHKm4S88MGA9kauQw6wK5/wHELbKB 8l/owOdCZUAqjeMAPoXifE+Aaz91w6McHTBfY0wPaALmEjW4YRhxtVH4sxfVajj9Q5 DDpmOgXiL3QsA== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible Date: Tue, 5 Aug 2025 15:01:40 +0000 Message-ID: <20250805150147.25909-2-ziyao@disroot.org> In-Reply-To: <20250805150147.25909-1-ziyao@disroot.org> References: <20250805150147.25909-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the clock controller shipped in Loongson 2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, 2K0300 requires a 120MHz external clock input, and a separate dt-binding header is used for cleanness. Signed-off-by: Yao Zi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Yanteng Si --- .../bindings/clock/loongson,ls2k-clk.yaml | 21 ++++++-- MAINTAINERS | 1 + .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++ 3 files changed, 72 insertions(+), 4 deletions(-) create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml= b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml index 4f79cdb417ab..47eb6c0f85bc 100644 --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - loongson,ls2k0300-clk - loongson,ls2k0500-clk - loongson,ls2k-clk # This is for Loongson-2K1000 - loongson,ls2k2000-clk @@ -24,8 +25,7 @@ properties: maxItems: 1 =20 clocks: - items: - - description: 100m ref + maxItems: 1 =20 clock-names: items: @@ -36,13 +36,26 @@ properties: description: The clock consumer should specify the desired clock by having the cl= ock ID in its "clocks" phandle cell. See include/dt-bindings/clock/loong= son,ls2k-clk.h - for the full list of Loongson-2 SoC clock IDs. + and include/dt-bindings/clock/loongson,ls2k0300-clk.h for the full l= ist of + Loongson-2 SoC clock IDs. + +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-clk + then: + properties: + clock-names: false + else: + required: + - clock-names =20 required: - compatible - reg - clocks - - clock-names - '#clock-cells' =20 additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 4912b8a83bbb..7960e65d7dfc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14365,6 +14365,7 @@ S: Maintained F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml F: drivers/clk/clk-loongson2.c F: include/dt-bindings/clock/loongson,ls2k-clk.h +F: include/dt-bindings/clock/loongson,ls2k0300-clk.h =20 LOONGSON SPI DRIVER M: Yinbo Zhu diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt= -bindings/clock/loongson,ls2k0300-clk.h new file mode 100644 index 000000000000..5e8f7b2f33f2 --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Yao Zi + */ +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ + +/* Derivied from REFCLK */ +#define LS2K0300_CLK_STABLE 0 +#define LS2K0300_PLL_NODE 1 +#define LS2K0300_PLL_DDR 2 +#define LS2K0300_PLL_PIX 3 +#define LS2K0300_CLK_THSENS 4 + +/* Derived from PLL_NODE */ +#define LS2K0300_CLK_NODE_DIV 5 +#define LS2K0300_CLK_NODE_PLL_GATE 6 +#define LS2K0300_CLK_NODE_SCALE 7 +#define LS2K0300_CLK_NODE_GATE 8 +#define LS2K0300_CLK_GMAC_DIV 9 +#define LS2K0300_CLK_GMAC_GATE 10 +#define LS2K0300_CLK_I2S_DIV 11 +#define LS2K0300_CLK_I2S_SCALE 12 +#define LS2K0300_CLK_I2S_GATE 13 + +/* Derived from PLL_DDR */ +#define LS2K0300_CLK_DDR_DIV 14 +#define LS2K0300_CLK_DDR_GATE 15 +#define LS2K0300_CLK_NET_DIV 16 +#define LS2K0300_CLK_NET_GATE 17 +#define LS2K0300_CLK_DEV_DIV 18 +#define LS2K0300_CLK_DEV_GATE 19 + +/* Derived from PLL_PIX */ +#define LS2K0300_CLK_PIX_DIV 20 +#define LS2K0300_CLK_PIX_PLL_GATE 21 +#define LS2K0300_CLK_PIX_SCALE 22 +#define LS2K0300_CLK_PIX_GATE 23 +#define LS2K0300_CLK_GMACBP_DIV 24 +#define LS2K0300_CLK_GMACBP_GATE 25 + +/* Derived from CLK_DEV */ +#define LS2K0300_CLK_USB_SCALE 26 +#define LS2K0300_CLK_USB_GATE 27 +#define LS2K0300_CLK_APB_SCALE 28 +#define LS2K0300_CLK_APB_GATE 29 +#define LS2K0300_CLK_BOOT_SCALE 30 +#define LS2K0300_CLK_BOOT_GATE 31 +#define LS2K0300_CLK_SDIO_SCALE 32 +#define LS2K0300_CLK_SDIO_GATE 33 + +#define LS2K0300_CLK_GMAC_IN 34 + +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ --=20 2.50.1 From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 746C7279DB6; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="fFk72Kh4" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 48DAC25DF5; Tue, 5 Aug 2025 17:03:17 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id HNlgRMBm5Bq9; Tue, 5 Aug 2025 17:03:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754406196; bh=W3t9oodd0h8mbXHDxSoPHsP9rVuywlZj0hRu4ydwEWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=fFk72Kh4+CrR07yXwFydJ9/1+KBGvQjx97zXYmWpSAb7O7lGVRO0gMtafnHjUQgUX MmurAJeM29M4vXAFrgUnh3AJoBHVH1qwGLC7cW0xMAL/gse2wyFWLXp6tpWE1k3rh0 X0MPj4PgUn6cl6GiTtxjHZVjzyuQTmbglRd8pPicoyZxjLFxkfpmCrWHaPc2C1pPqP Yq3LKT8k3XroHUz0CqVPb15D1djRzVnF5MXwaPAiQ1CFxgz2cf+KKpXO9+TV5YNnKu sfvjPgTgqVzKJhBJHk3gjCQXsbcAIU7PtVrGEt0HppQWd6HC3+hXmNV2/HWpCd0Snj hdnVr1URUY1fw== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v3 2/8] clk: loongson2: Allow specifying clock flags for gate clock Date: Tue, 5 Aug 2025 15:01:41 +0000 Message-ID: <20250805150147.25909-3-ziyao@disroot.org> In-Reply-To: <20250805150147.25909-1-ziyao@disroot.org> References: <20250805150147.25909-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some gate clocks need to be supplied with flags, e.g., it may be required to specify CLK_IS_CRTICAL for CPU clocks. Add a field to loongson2_clk_board_info for representing clock flags, and specify it when registering gate clocks. A new helper macro, CLK_GATE_FLAGS, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 27e632edd484..cc3fb13e770f 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -50,6 +50,7 @@ struct loongson2_clk_board_info { const char *name; const char *parent_name; unsigned long fixed_rate; + unsigned long flags; u8 reg_offset; u8 div_shift; u8 div_width; @@ -105,6 +106,18 @@ struct loongson2_clk_board_info { .bit_idx =3D _bidx, \ } =20 +#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \ + _flags) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_GATE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .bit_idx =3D _bidx, \ + .flags =3D _flags \ + } + #define CLK_FIXED(_id, _name, _pname, _rate) \ { \ .id =3D _id, \ @@ -332,7 +345,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0, + hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); --=20 2.50.1 From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20B80273805; Tue, 5 Aug 2025 15:04:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406273; cv=none; b=k0q2BjXf6UraXOJawRR8HHD4XgBEPDAKYpQl1jINCjWElkZC3hea62pdrjcbL2sWYJw7xagmT+58TmSurUuVbvEKmo0+bStYDxV8mf7NPaUGIlF8tv5XrCWNvMkbrZYSMEoMSLtwIb9KQcqRAorF5zXntUEd2JwwhavvOvFs0Co= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406273; c=relaxed/simple; bh=vWymD5YE3JfeQfyR3NVLfRHmsx4EBqNPAgdwvWcHF00=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ov/a17DN21yvLDjhSxjhRvrzWVOXeSdlhWKFqHUryUdHv7HwdwaNkCeBKdhOHFvysCTXthoDarjzja8WdPzQK7eSShgvB+0WE2jrWaLTRvVyEN7Qj/ifq4I7TrkgIHT3ApwHnPAjpLwLwLFy0Mf5WRtKViSC7z8pROZhGeNCiss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=axLbpURP; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="axLbpURP" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id B3B5920012; Tue, 5 Aug 2025 17:04:30 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id jagGzta6IOGh; Tue, 5 Aug 2025 17:04:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754406270; bh=vWymD5YE3JfeQfyR3NVLfRHmsx4EBqNPAgdwvWcHF00=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=axLbpURPFc6nGaIgHXQweXVHSSmL8sq23L0dr+yTbSIXy2PA/n5uDXKtpyckx2m7i Oh0HVjXSrsG2Ib4FCKkudDdLhwO/5wJKPLfvpPwAABbeYP/xO7561YNZBQZaQH7zFW xX2Sz+SIl8Eah6pahywaYum4SJkgqBZ4wMXyMYlUbIPSW0MUc6A7LmN5wxnsqSlLnw O/a1mvB9MJw1umDlQsSYMRN8X5mKqeM8KahcednGPsTLHM1D4IXStiMo0j4Z6p/ODg HHs83dqAAIrs9/D87RLxoFuFcn5RHW13VKW4syZMCFExsKL/EOjCIu5Fy7vUbPa5jl WpNSO/VLK7XwA== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v3 3/8] clk: loongson2: Support scale clocks with an alternative mode Date: Tue, 5 Aug 2025 15:01:42 +0000 Message-ID: <20250805150147.25909-4-ziyao@disroot.org> In-Reply-To: <20250805150147.25909-1-ziyao@disroot.org> References: <20250805150147.25909-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 and 2K1500 ship scale clocks with an alternative mode. There's one mode bit in clock configuration register indicating the operation mode. When mode bit is unset, the scale clock acts the same as previous generation of scale clocks. When it's set, a different equation for calculating result frequency, Fout =3D Fin / (scale + 1), is used. This patch adds frequency calculation support for the scale clock variant. A helper macro, CLK_SCALE_MODE, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index cc3fb13e770f..bba97270376c 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -42,6 +42,7 @@ struct loongson2_clk_data { u8 div_width; u8 mult_shift; u8 mult_width; + u8 bit_idx; }; =20 struct loongson2_clk_board_info { @@ -96,6 +97,19 @@ struct loongson2_clk_board_info { .div_width =3D _dwidth, \ } =20 +#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \ + _dshift, _dwidth, _midx) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_SCALE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .div_shift =3D _dshift, \ + .div_width =3D _dwidth, \ + .bit_idx =3D _midx + 1, \ + } + #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ { \ .id =3D _id, \ @@ -243,13 +257,18 @@ static const struct clk_ops loongson2_pll_recalc_ops = =3D { static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - u64 val, mult; + u64 val, scale; + u32 mode =3D 0; struct loongson2_clk_data *clk =3D to_loongson2_clk(hw); =20 val =3D readq(clk->reg); - mult =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + scale =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + + if (clk->bit_idx) + mode =3D val & BIT(clk->bit_idx - 1); =20 - return div_u64((u64)parent_rate * mult, 8); + return mode =3D=3D 0 ? div_u64((u64)parent_rate * scale, 8) : + div_u64((u64)parent_rate, scale); } =20 static const struct clk_ops loongson2_freqscale_recalc_ops =3D { @@ -284,6 +303,7 @@ static struct clk_hw *loongson2_clk_register(struct loo= ngson2_clk_provider *clp, clk->div_width =3D cld->div_width; clk->mult_shift =3D cld->mult_shift; clk->mult_width =3D cld->mult_width; + clk->bit_idx =3D cld->bit_idx; clk->hw.init =3D &init; =20 hw =3D &clk->hw; --=20 2.50.1 From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33C2C277C9C; Tue, 5 Aug 2025 15:04:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406279; cv=none; b=bAT4Q++uCTQyCiMrhqCSFwwXCYEnPVn8JOiEi+faS1TSkGdFw6pVsTFR5ZiVJbpKB8VFokr7EYQueLFpJVLIFQLsfnxRD4rFOnm1iXONMWxf2/CpSABMo+BTZ5QBaTyaV6At+JzFWklD6RpU02X8XTF2QGSDjh561RmsYWYfSGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406279; c=relaxed/simple; bh=SphuyDnE/+01mJhTz5T8pC+wNRaE5hxsq4Cc5z+u9o0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iUCZd0Q2HJBLehLgy+5eddlFYsJF/wkTeU4iI4x8bDe1DYbahd8cWu+P9YRtt2fG2UO152EAcpxE5OWf81QCOOWhlLgblwAM5t7kcnEAGNEqaTYjHU3ZuocinVPESTgyPMsxBjy0NLm0q55AfdCAtJCkLAlEPoDSK4IFsXnM1FM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=HKx0Bbu5; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="HKx0Bbu5" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id CD1FE2005C; Tue, 5 Aug 2025 17:04:36 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id i43S4mpMmekB; Tue, 5 Aug 2025 17:04:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754406275; bh=SphuyDnE/+01mJhTz5T8pC+wNRaE5hxsq4Cc5z+u9o0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HKx0Bbu54z4vR89xil1TDVVqesJ2Z5gYbMaxsbFWG4rFsWm/E4GhtExhIK7mHa2kd tfLowNJ+m3P+5IUVTmdYBDEtpUzLqcoTIh5tHw+qSDkh1j7W2g1r6gQwGtRasxsKCY oAMU/oYFyN7udbOCN0fWdti7IIjDrICvORK1phteYKrUYlGhjf0cV6JeEH3KXnPhNw GfeYlzvy81wMQSHdCx8rHSv/jpwuxZwwZ3PbXjS6sHFSu/Ip8M4iJ/c6SQEfNnQa3q G/4uTirf5FEUde7sK4q2twFrcFQMGorG1EVywAY9M7bGlr8YJBVFwET57q+dQUO0Nj 2YCO4nsq4BBTw== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v3 4/8] clk: loongson2: Allow zero divisors for dividers Date: Tue, 5 Aug 2025 15:01:43 +0000 Message-ID: <20250805150147.25909-5-ziyao@disroot.org> In-Reply-To: <20250805150147.25909-1-ziyao@disroot.org> References: <20250805150147.25909-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 and 2K0500 ship divider clocks which allows zero divisors, in which case the divider acts the same as one is specified. Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to prepare for future introduction of these clocks. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index bba97270376c..7a916c7d2718 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -361,7 +361,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) p->parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, - CLK_DIVIDER_ONE_BASED, + CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &clp->clk_lock); break; case CLK_TYPE_GATE: --=20 2.50.1 From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8999B13B58A; Tue, 5 Aug 2025 15:04:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406286; cv=none; b=J3ZEcMDbmxb02I8fDVtCYKzXThxeBHFMiOkEkdI1+P1DeB4Lfy+vzMQeG3IR0Gy+vqgsDJw+Kxu/p8a0WnWxCQwsac7XigdUEsCfuFT0VzaDj1l5ox6PG0UZGXeUiorYjgrTIl1QL2Ix6GCoHxo4PUSCb2+yhShrkfubqpvk2O8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406286; c=relaxed/simple; bh=9uXW9RaBSeIrf8ozKfFOJ+DzM9/7r0rVkR5meCgzgp4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vuhdj4YhPmBKYx7bLjJ+Q7WuUrjfdrsU6ZZjYve4OuLSDeF5co8bQVj4xihrtrQSmL5gYyoY2owpIJPf4bRPkdMmRxICESKxEeTNFTT38WCIFYOdhLXfVtiy1Uh5L5mCC1+Sn5sO3gU/Cu4LH9yh0TiRtYtbbkS/YMBo5m1RPMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=PWdYWMaU; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="PWdYWMaU" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 5AB1C22C1F; Tue, 5 Aug 2025 17:04:43 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id iU1ZiM43gRSi; Tue, 5 Aug 2025 17:04:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754406282; bh=9uXW9RaBSeIrf8ozKfFOJ+DzM9/7r0rVkR5meCgzgp4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=PWdYWMaUUt+Up+//W3siXfruVoiUgyuN3U8azP0BYV3JG+AZSB/Y/m68KjGFTZNVo udBhYrs57WW4x60yUrs3kTPRDfKKkLRniI7suSPEG84vJncZ9bUMseXonY/ay90EGY 8rinh+CCdBJt/lnOaeOPvRCT7zSdbOe85b1+IbCU6ZvXESMVfA7NygTwSeTpSJKY49 34R093C9au54OGJrAJEqh7ucNB47g2G2fQuLkIFmDct3OEECG5rsQ6NBXI8WlWFcWS h360p8iz5246BSEpmBxMAXGc27N4bNadNroP/aipyN8NNqqmxcuQKQ8hgoZyzyUVUT sv9g+wwbnYWiw== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v3 5/8] clk: loongson2: Avoid hardcoding firmware name of the reference clock Date: Tue, 5 Aug 2025 15:01:44 +0000 Message-ID: <20250805150147.25909-6-ziyao@disroot.org> In-Reply-To: <20250805150147.25909-1-ziyao@disroot.org> References: <20250805150147.25909-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 requires a reference clock with a frequency different from previous SoCs (120MHz v.s. 100MHz), thus hardcoding the firmware name of the reference clock as ref_100m isn't a good idea. This patch retrives the clock name of the reference clock dynamically during probe, avoiding the hardcoded pdata structure and preparing for support of future SoCs. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 7a916c7d2718..52a9f1c2794a 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -13,10 +13,6 @@ #include #include =20 -static const struct clk_parent_data pdata[] =3D { - { .fw_name =3D "ref_100m", }, -}; - enum loongson2_clk_type { CLK_TYPE_PLL, CLK_TYPE_SCALE, @@ -275,7 +271,8 @@ static const struct clk_ops loongson2_freqscale_recalc_= ops =3D { .recalc_rate =3D loongson2_freqscale_recalc_rate, }; =20 -static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider= *clp, +static struct clk_hw *loongson2_clk_register(const char *parent, + struct loongson2_clk_provider *clp, const struct loongson2_clk_board_info *cld, const struct clk_ops *ops) { @@ -292,11 +289,7 @@ static struct clk_hw *loongson2_clk_register(struct lo= ongson2_clk_provider *clp, init.ops =3D ops; init.flags =3D 0; init.num_parents =3D 1; - - if (!cld->parent_name) - init.parent_data =3D pdata; - else - init.parent_names =3D &cld->parent_name; + init.parent_names =3D &parent; =20 clk->reg =3D clp->base + cld->reg_offset; clk->div_shift =3D cld->div_shift; @@ -321,11 +314,17 @@ static int loongson2_clk_probe(struct platform_device= *pdev) struct device *dev =3D &pdev->dev; struct loongson2_clk_provider *clp; const struct loongson2_clk_board_info *p, *data; + const char *refclk_name, *parent_name; =20 data =3D device_get_match_data(dev); if (!data) return -EINVAL; =20 + refclk_name =3D of_clk_get_parent_name(dev->of_node, 0); + if (IS_ERR(refclk_name)) + return dev_err_probe(dev, PTR_ERR(refclk_name), + "failed to get refclk name\n"); + for (p =3D data; p->name; p++) clks_num =3D max(clks_num, p->id + 1); =20 @@ -347,18 +346,20 @@ static int loongson2_clk_probe(struct platform_device= *pdev) =20 for (i =3D 0; i < clks_num; i++) { p =3D &data[i]; + parent_name =3D p->parent_name ? p->parent_name : refclk_name; + switch (p->type) { case CLK_TYPE_PLL: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_pll_recalc_ops); break; case CLK_TYPE_SCALE: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_freqscale_recalc_ops); break; case CLK_TYPE_DIVIDER: hw =3D devm_clk_hw_register_divider(dev, p->name, - p->parent_name, 0, + parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, CLK_DIVIDER_ONE_BASED | @@ -366,15 +367,15 @@ static int loongson2_clk_probe(struct platform_device= *pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + hw =3D devm_clk_hw_register_gate(dev, p->name, parent_name, p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); break; case CLK_TYPE_FIXED: - hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata, - 0, p->fixed_rate); + hw =3D devm_clk_hw_register_fixed_rate(dev, p->name, parent_name, + 0, p->fixed_rate); break; default: return dev_err_probe(dev, -EINVAL, "Invalid clk type\n"); --=20 2.50.1 From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E4B12749D7; Tue, 5 Aug 2025 15:05:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406334; cv=none; b=jTRvoy4sNtFsHYZch5UuoBES6kDfNsFTZsrvUOvCZoAj3bKW/7swu77OpJqlUQB2E70qkY9dy7f7ArfMCFlHPe+v1dcTjxXewHknJKtzkkRjFdYC5lSDdtsA3lSTZEzGhdHd0vbtEYWGRmcoBSjqz3LIqAeLRZKPNjXiU6P/0VA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754406334; c=relaxed/simple; bh=Jz51mo42bXiZbAkjpGnHDpNV+0hBPVOg3xjUryOnfsY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fJaH5iGqyT0jWnBgV5Fy2OdS0Ru79lyIo+3Rxw0p/pDUY6v51VCpJV7FXGSXKOF9arkpzh1J/xEFDVVYyLPL12xoWwJN3GwBvQWIoNvTdAEB+ppzZ7gdpG2dELW31rdrCu6ucpeLGzjzkus71zGHqWu5lDcWZlhiqera/FSgTBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=I2n0QTzN; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="I2n0QTzN" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id EF20322E35; Tue, 5 Aug 2025 17:05:30 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id D0ht1NTCS2r4; Tue, 5 Aug 2025 17:05:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754406330; bh=Jz51mo42bXiZbAkjpGnHDpNV+0hBPVOg3xjUryOnfsY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=I2n0QTzNXTUNiMZbHkS9HhbgdVHwfo8vJTmAHqWS2C8XbKYQ9aXzhi44coM9f4IH4 0/0EF8YD8tcvY1Ssi+W3z1xNrOku0ztvqIdMAqGtsBjlzhmVJUtloOH0wp/s0lpPy2 ZNTKZ5F+t8igYKAHF5MBDUgidpqIvd3Ig0nWBVvsjziSwPZ0nBpJj95tqGxeFrmoIr 4dIBgXlimtDgh5Wm1s/KY7O3Yq7gDCP5eygQ7RTqniS4W25m0zArvbUSoOawGgQVJK S9EhjKmW/MQb3eQ3BNw65oLUp+Ax+wu5NNZx41ge611tSmy19vd1fMmeLdMTSqFm/5 9QHoRpWUIc7Yw== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v3 6/8] clk: loongson2: Add clock definitions for Loongson 2K0300 SoC Date: Tue, 5 Aug 2025 15:01:45 +0000 Message-ID: <20250805150147.25909-7-ziyao@disroot.org> In-Reply-To: <20250805150147.25909-1-ziyao@disroot.org> References: <20250805150147.25909-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock controller of Loongson 2K0300 consists of three PLLs, requires an 120MHz external reference clock to function, and generates clocks in various frequencies for SoC peripherals. Clock definitions for previous SoC generations could be reused for most clock hardwares. There're two gates marked as critical, clk_node_gate and clk_boot_gate, which supply the CPU cores and the system configuration bus. Disabling them leads to a SoC hang. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 52a9f1c2794a..1d210a7683ea 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 enum loongson2_clk_type { CLK_TYPE_PLL, @@ -137,6 +138,52 @@ struct loongson2_clk_board_info { .fixed_rate =3D _rate, \ } =20 +static const struct loongson2_clk_board_info ls2k0300_clks[] =3D { + /* Reference Clock */ + CLK_PLL(LS2K0300_PLL_NODE, "pll_node", 0x00, 15, 9, 8, 7), + CLK_PLL(LS2K0300_PLL_DDR, "pll_ddr", 0x08, 15, 9, 8, 7), + CLK_PLL(LS2K0300_PLL_PIX, "pll_pix", 0x10, 15, 9, 8, 7), + CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000), + CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000), + /* Node PLL */ + CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7), + CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7), + CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7), + CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div= ", 0x00, 0), + CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div= ", 0x00, 1), + CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div",= 0x00, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_sca= le", + 0x24, 0, CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE, "clk_node_scale", "clk_node= _pll_gate", + 0x20, 0, 3, 3), + /* DDR PLL */ + CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7), + CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7), + CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7), + CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1), + CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE, "clk_ddr_gate", "clk_ddr_div", + 0x08, 0, CLK_IS_CRITICAL), + /* PIX PLL */ + CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7), + CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7), + CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x= 10, 0), + CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24= , 6), + CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", = 0x10, 1), + CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE, "clk_pix_scale", "clk_pix_pll_gate= ", + 0x20, 4, 3, 7), + /* clk_dev_gate */ + CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, = 24, 4), + CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2= ), + CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate", "clk_sdio_scale", 0x24,= 4), + CLK_GATE(LS2K0300_CLK_APB_GATE, "clk_apb_gate", "clk_apb_scale", 0x24, 3= ), + CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale", + 0x24, 1, CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE, "clk_usb_scale", "clk_dev_gate",= 0x20, 12, 3, 15), + CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE, "clk_apb_scale", "clk_dev_gate",= 0x20, 16, 3, 19), + CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate",= 0x20, 8, 3, 11), +}; + static const struct loongson2_clk_board_info ls2k0500_clks[] =3D { CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6), CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6), @@ -393,6 +440,7 @@ static int loongson2_clk_probe(struct platform_device *= pdev) } =20 static const struct of_device_id loongson2_clk_match_table[] =3D { + { .compatible =3D "loongson,ls2k0300-clk", .data =3D &ls2k0300_clks }, { .compatible =3D "loongson,ls2k0500-clk", .data =3D &ls2k0500_clks }, { .compatible =3D "loongson,ls2k-clk", .data =3D &ls2k1000_clks }, { .compatible =3D "loongson,ls2k2000-clk", .data =3D &ls2k2000_clks }, --=20 2.50.1 From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFC5E2797AE; Tue, 5 Aug 2025 15:05:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; 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charset="utf-8" Describe the clock controller integrated in Loongson 2K0300 SoC and clocks for UARTs. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/= boot/dts/loongson-2k0300.dtsi index ce3574691aa9..d909a4eca312 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300.dtsi +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include =20 / { @@ -21,7 +22,7 @@ cpu0: cpu@0 { compatible =3D "loongson,la264"; reg =3D <0>; device_type =3D "cpu"; - clocks =3D <&cpu_clk>; + clocks =3D <&clk LS2K0300_CLK_NODE_GATE>; }; =20 }; @@ -32,9 +33,10 @@ cpuintc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 - cpu_clk: clock-1000m { + refclk: clock-120m { compatible =3D "fixed-clock"; - clock-frequency =3D <1000000000>; + clock-frequency =3D <120000000>; + clock-output-names =3D "refclk_120m"; #clock-cells =3D <0>; }; =20 @@ -46,6 +48,13 @@ soc@10000000 { <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>, <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>; =20 + clk: clock-controller@16000400 { + compatible =3D "loongson,ls2k0300-clk"; + reg =3D <0x0 0x16000400 0x0 0x30>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; + liointc0: interrupt-controller@16001400 { compatible =3D "loongson,liointc-2.0"; reg =3D <0x0 0x16001400 0x0 0x40>, @@ -87,6 +96,7 @@ liointc1: interrupt-controller@16001440 { uart0: serial@16100000 { compatible =3D "ns16550a"; reg =3D <0 0x16100000 0 0x10>; + clocks =3D <&clk LS2K0300_CLK_APB_GATE>; interrupt-parent =3D <&liointc0>; interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; no-loopback-test; --=20 2.50.1 From nobody Sun Oct 5 10:44:45 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B12818FC92; Tue, 5 Aug 2025 15:05:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="gx5mqEmL" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 4D785204DA; Tue, 5 Aug 2025 17:05:43 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id Wv6F2cCIqU_R; Tue, 5 Aug 2025 17:05:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754406342; bh=81PMYlqM/y1cobIvGWv6NmLT8uHoL246gy0zJP1C1Hk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=gx5mqEmLGTRTCB8WYMPylE4e1nEcEm6yYwA5XL6b1xbrYLzSwrf9TYrccQENl/2iR 0mRQ9MinmqsNus88RQ/b3s0kxKUo6u+1mAdCyDB+VtBWk2YQWacpZa4OoGRYyvbnwO vyIwL2K25PzWkP5RFLhM//JvG/VEZeJ8hlvrTE6Do6eu+coE3Lcq1JTonAisfYodRN Hu78ICP2j0adzyFj87Yq0Lwehw7dU4GQxmOUCsH02jGdIvaOyxTRF0rN2jqlLTj4qu a6I6R2QB5NV5wo7QxrmVZUTjicHeIf/mJbyWEkbEhx/CAGnJu6PopZyZgQgsXFN9Id oLRyc1zhbrhUA== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v3 8/8] LoongArch: dts: Remove clock-frquency from UART0 of CTCISZ Forever Pi Date: Tue, 5 Aug 2025 15:01:47 +0000 Message-ID: <20250805150147.25909-9-ziyao@disroot.org> In-Reply-To: <20250805150147.25909-1-ziyao@disroot.org> References: <20250805150147.25909-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The property isn't required anymore as the supply clock of UART0 has been described. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts = b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts index a033c086461f..1bdfff7fae92 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts +++ b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts @@ -40,6 +40,5 @@ linux,cma { }; =20 &uart0 { - clock-frequency =3D <100000000>; status =3D "okay"; }; --=20 2.50.1