From nobody Sun Oct 5 10:45:17 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AD95156237; Tue, 5 Aug 2025 10:26:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754389604; cv=none; b=UgdjPmRI+PbD6MZCBP6TqruFB6roGr/lqceaEW2meqCfv7+zPY5qUCtAzR+ECdIOTFORFvkEJsktIO+CSTjtvo8P8mJ0D5rgTuoUFfRO75WXsyunN/5F7DKbRPyy6UoolJTmKLeSGAcBvEH/eakCLXtcqiZh2T5VP9x447u2wD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754389604; c=relaxed/simple; bh=UGKP9T8n9F1kTUfGEGO7Etj36JCUlKzaZSO38heUsps=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g0bkh3f8nQK7U1uAyKP+aw/LVmUQ/iWh8tIk3xYZlltdCz7DpqVj8W6uz3vjy8PzjfnKMrb/JNMTuxFfxEJ1rszCuIS5bHxaJSZTzspUD7wqkadioPSpv0vNVdjVHpyabdD4KcuTm84nylBXqDQ/rWv6XMn/OByh37F7Gklks80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=zd7ekgRm; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="zd7ekgRm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754389602; x=1785925602; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UGKP9T8n9F1kTUfGEGO7Etj36JCUlKzaZSO38heUsps=; b=zd7ekgRmqeaCVE2wDsmtPpGaVG6QIXlE9cBG8eaSZIOP6Vc6L/nFb3+5 cq3NWkpemK8DGfsA8Txlcxwp3+AHT5y1UoeTDL1lyQuSlKTLrOkexxsYE IBpZV7x8zvh7D34aFiqNpw5OQv9H0EAj9M4fuB3BvzmhWfRpFTEZGLflb C+UtjtlVrwxhMZ7AtitJs1dINcn7QuZ3kdBblvhJ6YiWFewLiCx5DlkIs yBsEWJ9Q8qEGMdJ9EqeTbkX8jle8/Nijtde68c4W3qBBmBgNolbVrI4ya YD56qRYd3Y1KlNk/1so/7P6w4MVsXlktBQYanIC6T+Y8iNyM5Kk2OUump Q==; X-CSE-ConnectionGUID: 5giYSL7rQRGsqPqo2rqYFw== X-CSE-MsgGUID: BGUNfPdXQXCQ7IAYcw0lJw== X-IronPort-AV: E=Sophos;i="6.17,265,1747724400"; d="scan'208";a="212248017" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 05 Aug 2025 03:26:40 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 5 Aug 2025 03:26:13 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 5 Aug 2025 03:26:07 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , CC: Subject: [PATCH v3 1/3] spi: atmel: simplify MR register update in cs_activate() Date: Tue, 5 Aug 2025 15:55:08 +0530 Message-ID: <20250805102510.36507-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250805102510.36507-1-manikandan.m@microchip.com> References: <20250805102510.36507-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" simplified the MR register configuration by updating only the PCS field using SPI_BFINS() instead of rewriting the entire register. Avoids code duplication. Signed-off-by: Manikandan Muralidharan --- drivers/spi/spi-atmel.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 89a6b46cd319..409f544d8983 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -397,20 +397,10 @@ static void cs_activate(struct atmel_spi *as, struct = spi_device *spi) * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS */ spi_writel(as, CSR0, asd->csr); - if (as->caps.has_wdrbt) { - spi_writel(as, MR, - SPI_BF(PCS, ~(0x01 << chip_select)) - | SPI_BIT(WDRBT) - | SPI_BIT(MODFDIS) - | SPI_BIT(MSTR)); - } else { - spi_writel(as, MR, - SPI_BF(PCS, ~(0x01 << chip_select)) - | SPI_BIT(MODFDIS) - | SPI_BIT(MSTR)); - } =20 mr =3D spi_readl(as, MR); + mr =3D SPI_BFINS(PCS, ~(0x01 << chip_select), mr); + spi_writel(as, MR, mr); =20 /* * Ensures the clock polarity is valid before we actually --=20 2.25.1 From nobody Sun Oct 5 10:45:17 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38E5926C3A0; Tue, 5 Aug 2025 10:26:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754389605; cv=none; b=q3vBrvA65x9AgqaW2jpPC0kRG9HG2nu3cjFuK05ND/Dc8PCLJPjoNCIelMtVNQ3LF0vxuxuiZLEC7NkkC838fjHIRzTOEmQxlBJa8l1hMBz+nfgm+D8vywK2v0YKlumeXJXPbDbONIJXHV826STgAbT2NjeWbAcrr45IWnnqb7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754389605; c=relaxed/simple; bh=jcHluiS23Qnyxsx+eLhpXfKCtwkHXmfK8TuIezg/KNo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q80bE/dNZipVoyPsdJShMejaABDgHFj+Ddsocqz3ur73z03AiGQL8YSI2SlkzaHvCrQx6amL8fr4DFlf4o8oxN02h6eguBrEvtxrj6+ZyahOjhjhfsP/FKkhf7sBn6GTZsdmL8Ye88BaQSHKUYvLy778+3YLJnBn2AStGz6n5HQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=QaQOyQka; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QaQOyQka" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754389604; x=1785925604; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jcHluiS23Qnyxsx+eLhpXfKCtwkHXmfK8TuIezg/KNo=; b=QaQOyQkad7wnVi9WDs4LKNfByUkQ3aEIQyxUYzCHitRq40ZjjnAODpWi oIS5y/WnqirB0T8VcUk8l7jlBGVN/IvvBV9HJ2UEkfg0Vzrnekh3V6Wws jX1j1rkcQyyZ3jf57/ptn02dZG3HhTqDfkP/6FGDpOvZDCL7GuEbvqdPj DIrFtjdtg+cLzle6p2UcE4C1fVMs0eagEdmOQ8OBPX7SClVDJA6Lgx6Y6 2zdykS8CQbVp+pCIdDgnhyXaHpx5JZ6CeICvNn/P5QdTXxXCQ6gRg18ih uKzMLS4AN1rN0+fNnLEyaKsn70jPqQy0O/QIEqPNMasl0nsj2Hea8hSub Q==; X-CSE-ConnectionGUID: 5giYSL7rQRGsqPqo2rqYFw== X-CSE-MsgGUID: K2sezLbaS86OHGPP6tSfdg== X-IronPort-AV: E=Sophos;i="6.17,265,1747724400"; d="scan'208";a="212248019" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 05 Aug 2025 03:26:41 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 5 Aug 2025 03:26:20 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 5 Aug 2025 03:26:15 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , CC: Subject: [PATCH v3 2/3] spi: dt-bindings: atmel,at91rm9200-spi: Add support for optional 'spi_gclk' clock Date: Tue, 5 Aug 2025 15:55:09 +0530 Message-ID: <20250805102510.36507-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250805102510.36507-1-manikandan.m@microchip.com> References: <20250805102510.36507-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The Atmel SPI controller supports both the peripheral clock and the Generic Clock (GCLK) as sources for SPCK generation. On platforms like the SAM9X7 SoC, the peripheral clock can reach frequencies up to 266=E2=80=AFMHz, which may exceed the maximum value supported by the Serial Clock Baud Rate (SCBR) divider, leading to SPI transfer failures. In such cases, the GCLK can be used as an alternative source for SPCK generation" This patch updates the Atmel SPI DT binding to support an optional programmable SPI generic clock, specified as 'spi_gclk', in addition to the required 'spi_clk'. Signed-off-by: Manikandan Muralidharan --- .../devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yam= l b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index d29772994cf5..11885d0cc209 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -31,11 +31,16 @@ properties: maxItems: 1 =20 clock-names: - contains: - const: spi_clk + items: + - const: spi_clk + - const: spi_gclk + minItems: 1 =20 clocks: - maxItems: 1 + items: + - description: Peripheral Bus clock + - description: Programmable Generic clock + minItems: 1 =20 dmas: items: --=20 2.25.1 From nobody Sun Oct 5 10:45:17 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4783226C3AA; Tue, 5 Aug 2025 10:26:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754389613; cv=none; b=Rw5Gz420e/0vqdeX/Q5jw9+SPqU76OF8jw/M6M2eS/MTthtnQIGXaSlSoflEo4+EQpR3TF6uJ3exnD89LQQIH8LI1tPVdE5RQaCDPqftJ6XJa+oBZg2MzYuL4wprrOEAWqgAc2bIg/ZUpPnQ4gdQCNfBSno3eQRuG2j55ruaUYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754389613; c=relaxed/simple; bh=aaF4RzhnHIcEcpz1/fOfbiJA8IKYcLEpZOP28Wzp2/8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bmxwgZjD0g2rH95s2DCKxeyhsaxxpvH3+6+ZO0BonzZmp6rFQPTUqCQhOjn6LpJGmx88eruykapQbMGG8wqFvum6xkrmpmhYo4IBKynvIo95cTtw8byw5ZZ007B7g3tFldn0EM/OS2N8EHtNLPcDB65hVDUtvJJapc5CiLOpSmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=uMYImeZi; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="uMYImeZi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754389612; x=1785925612; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aaF4RzhnHIcEcpz1/fOfbiJA8IKYcLEpZOP28Wzp2/8=; b=uMYImeZidz5XtAGWseum+3j6sNnz5LI9XoOhIxrW3PiVVjVTc9lDrstK BYyK9S8JWc8IfJFkviKo4mWl1HHIJIrH/DB1rnUAMN9T32FUaQiCda2lX NaUfeSJ9OfHmYStCabzvU8cdrCeFyIHEK9sMPTUdQjOHiCeK9h4Bj3Vxk 8SDSaDsmf4FCU4dJdZUcFAkNSFkDC6wApLN9xX4XTZ7E4ylB7krDpr61g fX50njgmTVdYLRapSl4/wL5fuEN9wFsDM//TDo+3edyvBbohSc9vBvLS4 js5VUgVpHDKTOdxcImOll9yax1YQutb8x/7Qq9bttJ7dyTTpuoDnrGa5G A==; X-CSE-ConnectionGUID: gINclLzITjaNL5SdvHAC7w== X-CSE-MsgGUID: 9bKWfwCNQjm7xBUPeXt5TQ== X-IronPort-AV: E=Sophos;i="6.17,265,1747724400"; d="scan'208";a="44291449" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 05 Aug 2025 03:26:51 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 5 Aug 2025 03:26:27 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 5 Aug 2025 03:26:22 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , CC: Subject: [PATCH v3 3/3] spi: atmel: Add support for handling GCLK as a clock source Date: Tue, 5 Aug 2025 15:55:10 +0530 Message-ID: <20250805102510.36507-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250805102510.36507-1-manikandan.m@microchip.com> References: <20250805102510.36507-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The SPI peripheral clock is typically used to derive the serial clock (SPCK) via the FLEX_SPI_CSRx.SCBR field. However, on platforms like the SAM9X7 SoC, where the peripheral clock can reach up to 266=E2=80= =AFMHz, this may exceed the SCBR limit, causing SPI transfers to fail. This patch adds support for using the SPI Generic Clock (GCLK) as an alternative and more flexible clock source for SPCK generation. The FLEX_SPI_MR.BRSRCCLK bit is updated accordingly to select between the peripheral clock and GCLK. Signed-off-by: Manikandan Muralidharan --- drivers/spi/spi-atmel.c | 64 +++++++++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 409f544d8983..89977bff76d2 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -256,6 +256,7 @@ struct atmel_spi { void __iomem *regs; int irq; struct clk *clk; + struct clk *gclk; struct platform_device *pdev; unsigned long spi_clk; =20 @@ -1480,6 +1481,8 @@ static void atmel_get_caps(struct atmel_spi *as) =20 static void atmel_spi_init(struct atmel_spi *as) { + u32 mr =3D 0; + spi_writel(as, CR, SPI_BIT(SWRST)); spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ =20 @@ -1487,12 +1490,17 @@ static void atmel_spi_init(struct atmel_spi *as) if (as->fifo_size) spi_writel(as, CR, SPI_BIT(FIFOEN)); =20 - if (as->caps.has_wdrbt) { - spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) - | SPI_BIT(MSTR)); - } else { - spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); - } + /* + * If GCLK is selected as the source clock for the bit rate generation + * Enable the BRSRCCLK/FDIV/DIV32 bit + */ + if (as->gclk) + mr |=3D SPI_BIT(FDIV); + + if (as->caps.has_wdrbt) + mr |=3D SPI_BIT(WDRBT); + + spi_writel(as, MR, mr | SPI_BIT(MODFDIS) | SPI_BIT(MSTR)); =20 if (as->use_pdc) spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); @@ -1555,6 +1563,11 @@ static int atmel_spi_probe(struct platform_device *p= dev) as->phybase =3D regs->start; as->irq =3D irq; as->clk =3D clk; + as->gclk =3D devm_clk_get_optional(&pdev->dev, "spi_gclk"); + if (IS_ERR(as->gclk)) { + ret =3D PTR_ERR(as->gclk); + goto out_unmap_regs; + } =20 init_completion(&as->xfer_completion); =20 @@ -1615,7 +1628,19 @@ static int atmel_spi_probe(struct platform_device *p= dev) if (ret) goto out_free_irq; =20 - as->spi_clk =3D clk_get_rate(clk); + /* + * In cases where the peripheral clock is higher,the FLEX_SPI_CSRx.SCBR + * exceeds the threshold (SCBR =E2=89=A4 255), the GCLK is used as the so= urce clock + * for the SPCK (SPI Serial Clock) bit rate generation + */ + if (as->gclk) { + ret =3D clk_prepare_enable(as->gclk); + if (ret) + goto out_disable_clk; + as->spi_clk =3D clk_get_rate(as->gclk); + } else { + as->spi_clk =3D clk_get_rate(clk); + } =20 as->fifo_size =3D 0; if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", @@ -1650,6 +1675,8 @@ static int atmel_spi_probe(struct platform_device *pd= ev) =20 spi_writel(as, CR, SPI_BIT(SWRST)); spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ + clk_disable_unprepare(as->gclk); +out_disable_clk: clk_disable_unprepare(clk); out_free_irq: out_unmap_regs: @@ -1685,6 +1712,8 @@ static void atmel_spi_remove(struct platform_device *= pdev) spin_unlock_irq(&as->lock); =20 clk_disable_unprepare(as->clk); + if (as->gclk) + clk_disable_unprepare(as->gclk); =20 pm_runtime_put_noidle(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -1696,6 +1725,8 @@ static int atmel_spi_runtime_suspend(struct device *d= ev) struct atmel_spi *as =3D spi_controller_get_devdata(host); =20 clk_disable_unprepare(as->clk); + if (as->gclk) + clk_disable_unprepare(as->gclk); pinctrl_pm_select_sleep_state(dev); =20 return 0; @@ -1705,10 +1736,20 @@ static int atmel_spi_runtime_resume(struct device *= dev) { struct spi_controller *host =3D dev_get_drvdata(dev); struct atmel_spi *as =3D spi_controller_get_devdata(host); + int ret; =20 pinctrl_pm_select_default_state(dev); =20 - return clk_prepare_enable(as->clk); + ret =3D clk_prepare_enable(as->clk); + if (ret) + return ret; + if (as->gclk) { + ret =3D clk_prepare_enable(as->gclk); + if (ret) + return ret; + } + + return 0; } =20 static int atmel_spi_suspend(struct device *dev) @@ -1736,10 +1777,17 @@ static int atmel_spi_resume(struct device *dev) ret =3D clk_prepare_enable(as->clk); if (ret) return ret; + if (as->gclk) { + ret =3D clk_prepare_enable(as->gclk); + if (ret) + return ret; + } =20 atmel_spi_init(as); =20 clk_disable_unprepare(as->clk); + if (as->gclk) + clk_disable_unprepare(as->gclk); =20 if (!pm_runtime_suspended(dev)) { ret =3D atmel_spi_runtime_resume(dev); --=20 2.25.1