From nobody Sun Oct 5 10:45:19 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3009F244679 for ; Tue, 5 Aug 2025 08:14:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381645; cv=none; b=OBeawV6fJNa7VIDn48PEs0dYXJICMOKL4xVPpLijA1kJwA2uZHqjxZKMsP+poVPtputMWTT4d+7s3kpOUeK1pabJvMC9mCveQK9rXFMiByblGZiVRWv/V/fbwM+OOGB3lN7uspdiC7FxyaBMe+aKCP1MreEGprMkTj9AfZIC2sM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381645; c=relaxed/simple; bh=FHLnF5YjCggfyN0+pjyMz7+fbaTAQaST2ZyNNIs5QAk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JD1UxQkH/0M2vC4sOFvr3s7pFbGWOo6Nf14C8q5w13tvyNxlbsdWEUdDWfRngmYUA2mryudjje/+HEo9qXlzx0vHjXbOWc6JSSlUeOePqQr0sMqLpN7/lsCBHbgJaVEYHi+L3cTkqXuzxZlu1fNRRNpvNIXT77WccB++oV8UjDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A194150C; Tue, 5 Aug 2025 01:13:54 -0700 (PDT) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D7F963F673; Tue, 5 Aug 2025 01:14:00 -0700 (PDT) From: Ryan Roberts To: Yang Shi , will@kernel.org, catalin.marinas@arm.com, akpm@linux-foundation.org, Miko.Lenczewski@arm.com, dev.jain@arm.com, scott@os.amperecomputing.com, cl@gentwo.org Cc: Ryan Roberts , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v6 1/4] arm64: Enable permission change on arm64 kernel block mappings Date: Tue, 5 Aug 2025 09:13:46 +0100 Message-ID: <20250805081350.3854670-2-ryan.roberts@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250805081350.3854670-1-ryan.roberts@arm.com> References: <20250805081350.3854670-1-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dev Jain This patch paves the path to enable huge mappings in vmalloc space and linear map space by default on arm64. For this we must ensure that we can handle any permission games on the kernel (init_mm) pagetable. Currently, __change_memory_common() uses apply_to_page_range() which does not support changing permissions for block mappings. We attempt to move away from this by using the pagewalk API, similar to what riscv does right now; however, it is the responsibility of the caller to ensure that we do not pass a range overlapping a partial block mapping or cont mapping; in such a case, the system must be able to support range splitting. This patch is tied with Yang Shi's attempt [1] at using huge mappings in the linear mapping in case the system supports BBML2, in which case we will be able to split the linear mapping if needed without break-before-make. Thus, Yang's series, IIUC, will be one such user of my patch; suppose we are changing permissions on a range of the linear map backed by PMD-hugepages, then the sequence of operations should look like the following: split_range(start) split_range(end); __change_memory_common(start, end); However, this patch can be used independently of Yang's; since currently permission games are being played only on pte mappings (due to apply_to_page_range not supporting otherwise), this patch provides the mechanism for enabling huge mappings for various kernel mappings like linear map and vmalloc. Reviewed-by: Catalin Marinas Reviewed-by: Ryan Roberts --------------------- Implementation --------------------- arm64 currently changes permissions on vmalloc objects locklessly, via apply_to_page_range, whose limitation is to deny changing permissions for block mappings. Therefore, we move away to use the generic pagewalk API, thus paving the path for enabling huge mappings by default on kernel space mappings, thus leading to more efficient TLB usage. However, the API currently enforces the init_mm.mmap_lock to be held. To avoid the unnecessary bottleneck of the mmap_lock for our usecase, this patch extends this generic API to be used locklessly, so as to retain the existing behaviour for changing permissions. Apart from this reason, it is noted at [2] that KFENCE can manipulate kernel pgtable entries during softirqs. It does this by calling set_memory_valid() -> __change_memory_common(). This being a non-sleepable context, we cannot take the init_mm mmap lock. Add comments to highlight the conditions under which we can use the lockless variant - no underlying VMA, and the user having exclusive control over the range, thus guaranteeing no concurrent access. We require that the start and end of a given range do not partially overlap block mappings, or cont mappings. Return -EINVAL in case a partial block mapping is detected in any of the PGD/P4D/PUD/PMD levels; add a corresponding comment in update_range_prot() to warn that eliminating such a condition is the responsibility of the caller. Note that, the pte level callback may change permissions for a whole contpte block, and that will be done one pte at a time, as opposed to an atomic operation for the block mappings. This is fine as any access will decode either the old or the new permission until the TLBI. apply_to_page_range() currently performs all pte level callbacks while in lazy mmu mode. Since arm64 can optimize performance by batching barriers when modifying kernel pgtables in lazy mmu mode, we would like to continue to benefit from this optimisation. Unfortunately walk_kernel_page_table_range() does not use lazy mmu mode. However, since the pagewalk framework is not allocating any memory, we can safely bracket the whole operation inside lazy mmu mode ourselves. Therefore, wrap the call to walk_kernel_page_table_range() with the lazy MMU helpers. [1] https://lore.kernel.org/all/20250304222018.615808-1-yang@os.amperecompu= ting.com/ [2] https://lore.kernel.org/linux-arm-kernel/89d0ad18-4772-4d8f-ae8a-7c48d2= 6a927e@arm.com/ Signed-off-by: Dev Jain Reviewed-by: Ryan Roberts --- arch/arm64/mm/pageattr.c | 155 +++++++++++++++++++++++++++++++-------- include/linux/pagewalk.h | 3 + mm/pagewalk.c | 24 ++++++ 3 files changed, 150 insertions(+), 32 deletions(-) diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 04d4a8f676db..c6a85000fa0e 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include #include @@ -20,6 +21,99 @@ struct page_change_data { pgprot_t clear_mask; }; =20 +static ptdesc_t set_pageattr_masks(ptdesc_t val, struct mm_walk *walk) +{ + struct page_change_data *masks =3D walk->private; + + val &=3D ~(pgprot_val(masks->clear_mask)); + val |=3D (pgprot_val(masks->set_mask)); + + return val; +} + +static int pageattr_pgd_entry(pgd_t *pgd, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pgd_t val =3D pgdp_get(pgd); + + if (pgd_leaf(val)) { + if (WARN_ON_ONCE((next - addr) !=3D PGDIR_SIZE)) + return -EINVAL; + val =3D __pgd(set_pageattr_masks(pgd_val(val), walk)); + set_pgd(pgd, val); + walk->action =3D ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_p4d_entry(p4d_t *p4d, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + p4d_t val =3D p4dp_get(p4d); + + if (p4d_leaf(val)) { + if (WARN_ON_ONCE((next - addr) !=3D P4D_SIZE)) + return -EINVAL; + val =3D __p4d(set_pageattr_masks(p4d_val(val), walk)); + set_p4d(p4d, val); + walk->action =3D ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_pud_entry(pud_t *pud, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pud_t val =3D pudp_get(pud); + + if (pud_leaf(val)) { + if (WARN_ON_ONCE((next - addr) !=3D PUD_SIZE)) + return -EINVAL; + val =3D __pud(set_pageattr_masks(pud_val(val), walk)); + set_pud(pud, val); + walk->action =3D ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_pmd_entry(pmd_t *pmd, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pmd_t val =3D pmdp_get(pmd); + + if (pmd_leaf(val)) { + if (WARN_ON_ONCE((next - addr) !=3D PMD_SIZE)) + return -EINVAL; + val =3D __pmd(set_pageattr_masks(pmd_val(val), walk)); + set_pmd(pmd, val); + walk->action =3D ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_pte_entry(pte_t *pte, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pte_t val =3D __ptep_get(pte); + + val =3D __pte(set_pageattr_masks(pte_val(val), walk)); + __set_pte(pte, val); + + return 0; +} + +static const struct mm_walk_ops pageattr_ops =3D { + .pgd_entry =3D pageattr_pgd_entry, + .p4d_entry =3D pageattr_p4d_entry, + .pud_entry =3D pageattr_pud_entry, + .pmd_entry =3D pageattr_pmd_entry, + .pte_entry =3D pageattr_pte_entry, +}; + bool rodata_full __ro_after_init =3D IS_ENABLED(CONFIG_RODATA_FULL_DEFAULT= _ENABLED); =20 bool can_set_direct_map(void) @@ -37,33 +131,35 @@ bool can_set_direct_map(void) arm64_kfence_can_set_direct_map() || is_realm_world(); } =20 -static int change_page_range(pte_t *ptep, unsigned long addr, void *data) +static int update_range_prot(unsigned long start, unsigned long size, + pgprot_t set_mask, pgprot_t clear_mask) { - struct page_change_data *cdata =3D data; - pte_t pte =3D __ptep_get(ptep); + struct page_change_data data; + int ret; =20 - pte =3D clear_pte_bit(pte, cdata->clear_mask); - pte =3D set_pte_bit(pte, cdata->set_mask); + data.set_mask =3D set_mask; + data.clear_mask =3D clear_mask; =20 - __set_pte(ptep, pte); - return 0; + arch_enter_lazy_mmu_mode(); + + /* + * The caller must ensure that the range we are operating on does not + * partially overlap a block mapping, or a cont mapping. Any such case + * must be eliminated by splitting the mapping. + */ + ret =3D walk_kernel_page_table_range_lockless(start, start + size, + &pageattr_ops, &data); + arch_leave_lazy_mmu_mode(); + + return ret; } =20 -/* - * This function assumes that the range is mapped with PAGE_SIZE pages. - */ static int __change_memory_common(unsigned long start, unsigned long size, - pgprot_t set_mask, pgprot_t clear_mask) + pgprot_t set_mask, pgprot_t clear_mask) { - struct page_change_data data; int ret; =20 - data.set_mask =3D set_mask; - data.clear_mask =3D clear_mask; - - ret =3D apply_to_page_range(&init_mm, start, size, change_page_range, - &data); - + ret =3D update_range_prot(start, size, set_mask, clear_mask); /* * If the memory is being made valid without changing any other bits * then a TLBI isn't required as a non-valid entry cannot be cached in @@ -71,6 +167,7 @@ static int __change_memory_common(unsigned long start, u= nsigned long size, */ if (pgprot_val(set_mask) !=3D PTE_VALID || pgprot_val(clear_mask)) flush_tlb_kernel_range(start, start + size); + return ret; } =20 @@ -174,32 +271,26 @@ int set_memory_valid(unsigned long addr, int numpages= , int enable) =20 int set_direct_map_invalid_noflush(struct page *page) { - struct page_change_data data =3D { - .set_mask =3D __pgprot(0), - .clear_mask =3D __pgprot(PTE_VALID), - }; + pgprot_t clear_mask =3D __pgprot(PTE_VALID); + pgprot_t set_mask =3D __pgprot(0); =20 if (!can_set_direct_map()) return 0; =20 - return apply_to_page_range(&init_mm, - (unsigned long)page_address(page), - PAGE_SIZE, change_page_range, &data); + return update_range_prot((unsigned long)page_address(page), + PAGE_SIZE, set_mask, clear_mask); } =20 int set_direct_map_default_noflush(struct page *page) { - struct page_change_data data =3D { - .set_mask =3D __pgprot(PTE_VALID | PTE_WRITE), - .clear_mask =3D __pgprot(PTE_RDONLY), - }; + pgprot_t set_mask =3D __pgprot(PTE_VALID | PTE_WRITE); + pgprot_t clear_mask =3D __pgprot(PTE_RDONLY); =20 if (!can_set_direct_map()) return 0; =20 - return apply_to_page_range(&init_mm, - (unsigned long)page_address(page), - PAGE_SIZE, change_page_range, &data); + return update_range_prot((unsigned long)page_address(page), + PAGE_SIZE, set_mask, clear_mask); } =20 static int __set_memory_enc_dec(unsigned long addr, diff --git a/include/linux/pagewalk.h b/include/linux/pagewalk.h index 682472c15495..8212e8f2d2d5 100644 --- a/include/linux/pagewalk.h +++ b/include/linux/pagewalk.h @@ -134,6 +134,9 @@ int walk_page_range(struct mm_struct *mm, unsigned long= start, int walk_kernel_page_table_range(unsigned long start, unsigned long end, const struct mm_walk_ops *ops, pgd_t *pgd, void *private); +int walk_kernel_page_table_range_lockless(unsigned long start, + unsigned long end, const struct mm_walk_ops *ops, + void *private); int walk_page_range_vma(struct vm_area_struct *vma, unsigned long start, unsigned long end, const struct mm_walk_ops *ops, void *private); diff --git a/mm/pagewalk.c b/mm/pagewalk.c index 648038247a8d..18a675ab87cf 100644 --- a/mm/pagewalk.c +++ b/mm/pagewalk.c @@ -633,6 +633,30 @@ int walk_kernel_page_table_range(unsigned long start, = unsigned long end, return walk_pgd_range(start, end, &walk); } =20 +/* + * Use this function to walk the kernel page tables locklessly. It should = be + * guaranteed that the caller has exclusive access over the range they are + * operating on - that there should be no concurrent access, for example, + * changing permissions for vmalloc objects. + */ +int walk_kernel_page_table_range_lockless(unsigned long start, unsigned lo= ng end, + const struct mm_walk_ops *ops, void *private) +{ + struct mm_walk walk =3D { + .ops =3D ops, + .mm =3D &init_mm, + .private =3D private, + .no_vma =3D true + }; + + if (start >=3D end) + return -EINVAL; + if (!check_ops_valid(ops)) + return -EINVAL; + + return walk_pgd_range(start, end, &walk); +} + /** * walk_page_range_debug - walk a range of pagetables not backed by a vma * @mm: mm_struct representing the target process of page table walk --=20 2.43.0 From nobody Sun Oct 5 10:45:19 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4DFA0248191 for ; Tue, 5 Aug 2025 08:14:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381645; cv=none; b=JK7pi82Jtkdgu3Xcct9ZPepzTpPvnHKtmPvR1mk/DgV9k25/JBTgJYe7/xOLafb82Ki0mHtCrdt9lBbLPjS2/kR9UCzCdvFMUi9H7jfzg/sq1h3f7DsfAbG+7Zc5aEnm93CEOIwH9hhjsuNqqRMkKKGtrLXClTxpkCYTDuVerFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381645; c=relaxed/simple; bh=Ap7m0TmJAeIC8BUf0uKvOn3bF3fuejzBm0DFp7CzvrY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DBsEsTJF64B+jUzK1I+ptUaupZPCMhaY72WJFxQzzOxKwt94M6DqmOqxk/GsX+qg4XOsGtUUquk5T/Kv3d/1CpeG/b/tzH3aT5ocxuSNGjMLsf/i8VFsas2Ayj90LRRQAGlEgl+ZCv+PSRJK2OKq/Bgsby9tiX3nQTT2TuiCxHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E12B51424; Tue, 5 Aug 2025 01:13:55 -0700 (PDT) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 94A2F3F673; Tue, 5 Aug 2025 01:14:02 -0700 (PDT) From: Ryan Roberts To: Yang Shi , will@kernel.org, catalin.marinas@arm.com, akpm@linux-foundation.org, Miko.Lenczewski@arm.com, dev.jain@arm.com, scott@os.amperecomputing.com, cl@gentwo.org Cc: Ryan Roberts , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v6 2/4] arm64: cpufeature: add AmpereOne to BBML2 allow list Date: Tue, 5 Aug 2025 09:13:47 +0100 Message-ID: <20250805081350.3854670-3-ryan.roberts@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250805081350.3854670-1-ryan.roberts@arm.com> References: <20250805081350.3854670-1-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yang Shi AmpereOne supports BBML2 without conflict abort, add to the allow list. Signed-off-by: Yang Shi Reviewed-by: Christoph Lameter (Ampere) Reviewed-by: Ryan Roberts --- arch/arm64/kernel/cpufeature.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9ad065f15f1d..b93f4ee57176 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2234,6 +2234,8 @@ static bool has_bbml2_noabort(const struct arm64_cpu_= capabilities *caps, int sco static const struct midr_range supports_bbml2_noabort_list[] =3D { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), + MIDR_ALL_VERSIONS(MIDR_AMPERE1), + MIDR_ALL_VERSIONS(MIDR_AMPERE1A), {} }; =20 --=20 2.43.0 From nobody Sun Oct 5 10:45:19 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2ABF9252292 for ; Tue, 5 Aug 2025 08:14:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381648; cv=none; b=INTpmJMQ4vKAdQgX3A9h0cE2Jt7RDWfR8vtS99r2f2tNAhNDrXUWvaB7BCaZpnqJYtLEpuKY65JbFrBkq8/K6O8eyqgGrjAeJvATd4MxkUKuBmQD/e08OAzILRUkNXcjsNMopBZJGFsqrXm7/W+oFEqnmawi6oAtw8xKbO+kdZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381648; c=relaxed/simple; bh=J2kpgocoGoUs2IqDWUUgbneE278Ytc4AvQR/LrxR1Sc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C4kYSMjcWlh+NhC6gfEDJL7Kh4mXlWBb89s8vIeldzuPm4mh/TZZ99/siHiPFGysWpdub+T+FyOO1wzoNgI6b1qoaAy/sAQk5LmVndK7QaBvw0K0TiK5I7U6Y/SWO9RLYixwg9v/TyPr26pNcXQYl2oPXiQfZlA51IZItsjBgDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 876CF150C; Tue, 5 Aug 2025 01:13:57 -0700 (PDT) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 37E473F673; Tue, 5 Aug 2025 01:14:04 -0700 (PDT) From: Ryan Roberts To: Yang Shi , will@kernel.org, catalin.marinas@arm.com, akpm@linux-foundation.org, Miko.Lenczewski@arm.com, dev.jain@arm.com, scott@os.amperecomputing.com, cl@gentwo.org Cc: Ryan Roberts , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v6 3/4] arm64: mm: support large block mapping when rodata=full Date: Tue, 5 Aug 2025 09:13:48 +0100 Message-ID: <20250805081350.3854670-4-ryan.roberts@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250805081350.3854670-1-ryan.roberts@arm.com> References: <20250805081350.3854670-1-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yang Shi When rodata=3Dfull is specified, kernel linear mapping has to be mapped at PTE level since large page table can't be split due to break-before-make rule on ARM64. This resulted in a couple of problems: - performance degradation - more TLB pressure - memory waste for kernel page table With FEAT_BBM level 2 support, splitting large block page table to smaller ones doesn't need to make the page table entry invalid anymore. This allows kernel split large block mapping on the fly. Add kernel page table split support and use large block mapping by default when FEAT_BBM level 2 is supported for rodata=3Dfull. When changing permissions for kernel linear mapping, the page table will be split to smaller size. The machine without FEAT_BBM level 2 will fallback to have kernel linear mapping PTE-mapped when rodata=3Dfull. With this we saw significant performance boost with some benchmarks and much less memory consumption on my AmpereOne machine (192 cores, 1P) with 256GB memory. * Memory use after boot Before: MemTotal: 258988984 kB MemFree: 254821700 kB After: MemTotal: 259505132 kB MemFree: 255410264 kB Around 500MB more memory are free to use. The larger the machine, the more memory saved. * Memcached We saw performance degradation when running Memcached benchmark with rodata=3Dfull vs rodata=3Don. Our profiling pointed to kernel TLB pressure. With this patchset we saw ops/sec is increased by around 3.5%, P99 latency is reduced by around 9.6%. The gain mainly came from reduced kernel TLB misses. The kernel TLB MPKI is reduced by 28.5%. The benchmark data is now on par with rodata=3Don too. * Disk encryption (dm-crypt) benchmark Ran fio benchmark with the below command on a 128G ramdisk (ext4) with disk encryption (by dm-crypt). fio --directory=3D/data --random_generator=3Dlfsr --norandommap \ --randrepeat 1 --status-interval=3D999 --rw=3Dwrite --bs=3D4k --loops= =3D1 \ --ioengine=3Dsync --iodepth=3D1 --numjobs=3D1 --fsync_on_close=3D1 = \ --group_reporting --thread --name=3Diops-test-job --eta-newline=3D1 \ --size 100G The IOPS is increased by 90% - 150% (the variance is high, but the worst number of good case is around 90% more than the best number of bad case). The bandwidth is increased and the avg clat is reduced proportionally. * Sequential file read Read 100G file sequentially on XFS (xfs_io read with page cache populated). The bandwidth is increased by 150%. Co-developed-by: Ryan Roberts Signed-off-by: Ryan Roberts Signed-off-by: Yang Shi --- arch/arm64/include/asm/cpufeature.h | 2 + arch/arm64/include/asm/mmu.h | 1 + arch/arm64/include/asm/pgtable.h | 5 + arch/arm64/kernel/cpufeature.c | 7 +- arch/arm64/mm/mmu.c | 237 +++++++++++++++++++++++++++- arch/arm64/mm/pageattr.c | 6 + 6 files changed, 252 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index bf13d676aae2..3f11e095a37d 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -871,6 +871,8 @@ static inline bool system_supports_pmuv3(void) return cpus_have_final_cap(ARM64_HAS_PMUV3); } =20 +bool bbml2_noabort_available(void); + static inline bool system_supports_bbml2_noabort(void) { return alternative_has_cap_unlikely(ARM64_HAS_BBML2_NOABORT); diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 6e8aa8e72601..98565b1b93e8 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -71,6 +71,7 @@ extern void create_pgd_mapping(struct mm_struct *mm, phys= _addr_t phys, pgprot_t prot, bool page_mappings_only); extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t pro= t); extern void mark_linear_text_alias_ro(void); +extern int split_kernel_leaf_mapping(unsigned long addr); =20 /* * This check is triggered during the early boot before the cpufeature diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index abd2dee416b3..aa89c2e67ebc 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -371,6 +371,11 @@ static inline pmd_t pmd_mkcont(pmd_t pmd) return __pmd(pmd_val(pmd) | PMD_SECT_CONT); } =20 +static inline pmd_t pmd_mknoncont(pmd_t pmd) +{ + return __pmd(pmd_val(pmd) & ~PMD_SECT_CONT); +} + #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP static inline int pte_uffd_wp(pte_t pte) { diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b93f4ee57176..f28f056087f3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2217,7 +2217,7 @@ static bool hvhe_possible(const struct arm64_cpu_capa= bilities *entry, return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); } =20 -static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, i= nt scope) +bool bbml2_noabort_available(void) { /* * We want to allow usage of BBML2 in as wide a range of kernel contexts @@ -2251,6 +2251,11 @@ static bool has_bbml2_noabort(const struct arm64_cpu= _capabilities *caps, int sco return true; } =20 +static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, i= nt scope) +{ + return bbml2_noabort_available(); +} + #ifdef CONFIG_ARM64_PAN static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) { diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index abd9725796e9..f6cd79287024 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -481,6 +481,8 @@ void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t = phys, unsigned long virt, int flags); #endif =20 +#define INVALID_PHYS_ADDR -1 + static phys_addr_t __pgd_pgtable_alloc(struct mm_struct *mm, enum pgtable_type pgtable_type) { @@ -488,7 +490,9 @@ static phys_addr_t __pgd_pgtable_alloc(struct mm_struct= *mm, struct ptdesc *ptdesc =3D pagetable_alloc(GFP_PGTABLE_KERNEL & ~__GFP_ZER= O, 0); phys_addr_t pa; =20 - BUG_ON(!ptdesc); + if (!ptdesc) + return INVALID_PHYS_ADDR; + pa =3D page_to_phys(ptdesc_page(ptdesc)); =20 switch (pgtable_type) { @@ -509,16 +513,229 @@ static phys_addr_t __pgd_pgtable_alloc(struct mm_str= uct *mm, return pa; } =20 +static phys_addr_t +try_pgd_pgtable_alloc_init_mm(enum pgtable_type pgtable_type) +{ + return __pgd_pgtable_alloc(&init_mm, pgtable_type); +} + static phys_addr_t __maybe_unused pgd_pgtable_alloc_init_mm(enum pgtable_type pgtable_type) { - return __pgd_pgtable_alloc(&init_mm, pgtable_type); + phys_addr_t pa; + + pa =3D __pgd_pgtable_alloc(&init_mm, pgtable_type); + BUG_ON(pa =3D=3D INVALID_PHYS_ADDR); + return pa; } =20 static phys_addr_t pgd_pgtable_alloc_special_mm(enum pgtable_type pgtable_type) { - return __pgd_pgtable_alloc(NULL, pgtable_type); + phys_addr_t pa; + + pa =3D __pgd_pgtable_alloc(NULL, pgtable_type); + BUG_ON(pa =3D=3D INVALID_PHYS_ADDR); + return pa; +} + +static void split_contpte(pte_t *ptep) +{ + int i; + + ptep =3D PTR_ALIGN_DOWN(ptep, sizeof(*ptep) * CONT_PTES); + for (i =3D 0; i < CONT_PTES; i++, ptep++) + __set_pte(ptep, pte_mknoncont(__ptep_get(ptep))); +} + +static int split_pmd(pmd_t *pmdp, pmd_t pmd) +{ + pmdval_t tableprot =3D PMD_TYPE_TABLE | PMD_TABLE_UXN | PMD_TABLE_AF; + unsigned long pfn =3D pmd_pfn(pmd); + pgprot_t prot =3D pmd_pgprot(pmd); + phys_addr_t pte_phys; + pte_t *ptep; + int i; + + pte_phys =3D try_pgd_pgtable_alloc_init_mm(TABLE_PTE); + if (pte_phys =3D=3D INVALID_PHYS_ADDR) + return -ENOMEM; + ptep =3D (pte_t *)phys_to_virt(pte_phys); + + if (pgprot_val(prot) & PMD_SECT_PXN) + tableprot |=3D PMD_TABLE_PXN; + + prot =3D __pgprot((pgprot_val(prot) & ~PTE_TYPE_MASK) | PTE_TYPE_PAGE); + prot =3D __pgprot(pgprot_val(prot) | PTE_CONT); + + for (i =3D 0; i < PTRS_PER_PTE; i++, ptep++, pfn++) + __set_pte(ptep, pfn_pte(pfn, prot)); + + /* + * Ensure the pte entries are visible to the table walker by the time + * the pmd entry that points to the ptes is visible. + */ + dsb(ishst); + __pmd_populate(pmdp, pte_phys, tableprot); + + return 0; +} + +static void split_contpmd(pmd_t *pmdp) +{ + int i; + + pmdp =3D PTR_ALIGN_DOWN(pmdp, sizeof(*pmdp) * CONT_PMDS); + for (i =3D 0; i < CONT_PMDS; i++, pmdp++) + set_pmd(pmdp, pmd_mknoncont(pmdp_get(pmdp))); +} + +static int split_pud(pud_t *pudp, pud_t pud) +{ + pudval_t tableprot =3D PUD_TYPE_TABLE | PUD_TABLE_UXN | PUD_TABLE_AF; + unsigned int step =3D PMD_SIZE >> PAGE_SHIFT; + unsigned long pfn =3D pud_pfn(pud); + pgprot_t prot =3D pud_pgprot(pud); + phys_addr_t pmd_phys; + pmd_t *pmdp; + int i; + + pmd_phys =3D try_pgd_pgtable_alloc_init_mm(TABLE_PMD); + if (pmd_phys =3D=3D INVALID_PHYS_ADDR) + return -ENOMEM; + pmdp =3D (pmd_t *)phys_to_virt(pmd_phys); + + if (pgprot_val(prot) & PMD_SECT_PXN) + tableprot |=3D PUD_TABLE_PXN; + + prot =3D __pgprot((pgprot_val(prot) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT); + prot =3D __pgprot(pgprot_val(prot) | PTE_CONT); + + for (i =3D 0; i < PTRS_PER_PMD; i++, pmdp++, pfn +=3D step) + set_pmd(pmdp, pfn_pmd(pfn, prot)); + + /* + * Ensure the pmd entries are visible to the table walker by the time + * the pud entry that points to the pmds is visible. + */ + dsb(ishst); + __pud_populate(pudp, pmd_phys, tableprot); + + return 0; +} + +static DEFINE_MUTEX(pgtable_split_lock); + +int split_kernel_leaf_mapping(unsigned long addr) +{ + pgd_t *pgdp, pgd; + p4d_t *p4dp, p4d; + pud_t *pudp, pud; + pmd_t *pmdp, pmd; + pte_t *ptep, pte; + int ret =3D 0; + + /* + * !BBML2_NOABORT systems should not be trying to change permissions on + * anything that is not pte-mapped in the first place. Just return early + * and let the permission change code raise a warning if not already + * pte-mapped. + */ + if (!system_supports_bbml2_noabort()) + return 0; + + /* + * Ensure addr is at least page-aligned since this is the finest + * granularity we can split to. + */ + if (addr !=3D PAGE_ALIGN(addr)) + return -EINVAL; + + mutex_lock(&pgtable_split_lock); + arch_enter_lazy_mmu_mode(); + + /* + * PGD: If addr is PGD aligned then addr already describes a leaf + * boundary. If not present then there is nothing to split. + */ + if (ALIGN_DOWN(addr, PGDIR_SIZE) =3D=3D addr) + goto out; + pgdp =3D pgd_offset_k(addr); + pgd =3D pgdp_get(pgdp); + if (!pgd_present(pgd)) + goto out; + + /* + * P4D: If addr is P4D aligned then addr already describes a leaf + * boundary. If not present then there is nothing to split. + */ + if (ALIGN_DOWN(addr, P4D_SIZE) =3D=3D addr) + goto out; + p4dp =3D p4d_offset(pgdp, addr); + p4d =3D p4dp_get(p4dp); + if (!p4d_present(p4d)) + goto out; + + /* + * PUD: If addr is PUD aligned then addr already describes a leaf + * boundary. If not present then there is nothing to split. Otherwise, + * if we have a pud leaf, split to contpmd. + */ + if (ALIGN_DOWN(addr, PUD_SIZE) =3D=3D addr) + goto out; + pudp =3D pud_offset(p4dp, addr); + pud =3D pudp_get(pudp); + if (!pud_present(pud)) + goto out; + if (pud_leaf(pud)) { + ret =3D split_pud(pudp, pud); + if (ret) + goto out; + } + + /* + * CONTPMD: If addr is CONTPMD aligned then addr already describes a + * leaf boundary. If not present then there is nothing to split. + * Otherwise, if we have a contpmd leaf, split to pmd. + */ + if (ALIGN_DOWN(addr, CONT_PMD_SIZE) =3D=3D addr) + goto out; + pmdp =3D pmd_offset(pudp, addr); + pmd =3D pmdp_get(pmdp); + if (!pmd_present(pmd)) + goto out; + if (pmd_leaf(pmd)) { + if (pmd_cont(pmd)) + split_contpmd(pmdp); + /* + * PMD: If addr is PMD aligned then addr already describes a + * leaf boundary. Otherwise, split to contpte. + */ + if (ALIGN_DOWN(addr, PMD_SIZE) =3D=3D addr) + goto out; + ret =3D split_pmd(pmdp, pmd); + if (ret) + goto out; + } + + /* + * CONTPTE: If addr is CONTPTE aligned then addr already describes a + * leaf boundary. If not present then there is nothing to split. + * Otherwise, if we have a contpte leaf, split to pte. + */ + if (ALIGN_DOWN(addr, CONT_PMD_SIZE) =3D=3D addr) + goto out; + ptep =3D pte_offset_kernel(pmdp, addr); + pte =3D __ptep_get(ptep); + if (!pte_present(pte)) + goto out; + if (pte_cont(pte)) + split_contpte(ptep); + +out: + arch_leave_lazy_mmu_mode(); + mutex_unlock(&pgtable_split_lock); + return ret; } =20 /* @@ -640,6 +857,16 @@ static inline void arm64_kfence_map_pool(phys_addr_t k= fence_pool, pgd_t *pgdp) { =20 #endif /* CONFIG_KFENCE */ =20 +static inline bool force_pte_mapping(void) +{ + bool bbml2 =3D system_capabilities_finalized() ? + system_supports_bbml2_noabort() : bbml2_noabort_available(); + + return (!bbml2 && (rodata_full || arm64_kfence_can_set_direct_map() || + is_realm_world())) || + debug_pagealloc_enabled(); +} + static void __init map_mem(pgd_t *pgdp) { static const u64 direct_map_end =3D _PAGE_END(VA_BITS_MIN); @@ -665,7 +892,7 @@ static void __init map_mem(pgd_t *pgdp) =20 early_kfence_pool =3D arm64_kfence_alloc_pool(); =20 - if (can_set_direct_map()) + if (force_pte_mapping()) flags |=3D NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; =20 /* @@ -1367,7 +1594,7 @@ int arch_add_memory(int nid, u64 start, u64 size, =20 VM_BUG_ON(!mhp_range_allowed(start, size, true)); =20 - if (can_set_direct_map()) + if (force_pte_mapping()) flags |=3D NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; =20 __create_pgd_mapping(swapper_pg_dir, start, __phys_to_virt(start), diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index c6a85000fa0e..6a8eefc16dbc 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -140,6 +140,12 @@ static int update_range_prot(unsigned long start, unsi= gned long size, data.set_mask =3D set_mask; data.clear_mask =3D clear_mask; =20 + ret =3D split_kernel_leaf_mapping(start); + if (!ret) + ret =3D split_kernel_leaf_mapping(start + size); + if (WARN_ON_ONCE(ret)) + return ret; + arch_enter_lazy_mmu_mode(); =20 /* --=20 2.43.0 From nobody Sun Oct 5 10:45:19 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D9B46256C9B for ; Tue, 5 Aug 2025 08:14:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381649; cv=none; b=MsFMZkvhwDpPmDtjLZnq/WOEwqjwf90ZIrOAJA8wKAvctRfYOJZV4VfAAFwGXNCUhrNFtcUVarW6Q1r+GdVzKqAG+4RHwmTvfW+bZ3Z2l4ak7HKUZAPYAPjAGNnsLAgJyRNmvj/wS1FMtx+NFdMfBOfzO/rfVEopBqAG69Mgt58= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754381649; c=relaxed/simple; bh=Jw5zRaXf/4VjiR/xkuwjdE2uUcPmQPItKQjRYEv7B3w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hp4KAcq08mf3MvUYB+VWC//E+0JlWswqRPK3g7VpvPU4k0yaboJh7r49GvjPzLmu72R7a+KHvRO5zbwu0OyQUXLenkm6fd1WsyWZZgOqfyleoDl1hxpJ5BUGZZQRrU0u4Agy37HPkf7UkwNKkXbr1jf0RifqFKrZ7mkUlTVOhkc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2B6F11424; Tue, 5 Aug 2025 01:13:59 -0700 (PDT) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF87E3F673; Tue, 5 Aug 2025 01:14:05 -0700 (PDT) From: Ryan Roberts To: Yang Shi , will@kernel.org, catalin.marinas@arm.com, akpm@linux-foundation.org, Miko.Lenczewski@arm.com, dev.jain@arm.com, scott@os.amperecomputing.com, cl@gentwo.org Cc: Ryan Roberts , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v6 4/4] arm64: mm: split linear mapping if BBML2 unsupported on secondary CPUs Date: Tue, 5 Aug 2025 09:13:49 +0100 Message-ID: <20250805081350.3854670-5-ryan.roberts@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250805081350.3854670-1-ryan.roberts@arm.com> References: <20250805081350.3854670-1-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yang Shi The kernel linear mapping is painted in very early stage of system boot. The cpufeature has not been finalized yet at this point. So the linear mapping is determined by the capability of boot CPU only. If the boot CPU supports BBML2, large block mappings will be used for linear mapping. But the secondary CPUs may not support BBML2, so repaint the linear mapping if large block mapping is used and the secondary CPUs don't support BBML2 once cpufeature is finalized on all CPUs. If the boot CPU doesn't support BBML2 or the secondary CPUs have the same BBML2 capability with the boot CPU, repainting the linear mapping is not needed. Repainting is implemented by the boot CPU, which we know supports BBML2, so it is safe for the live mapping size to change for this CPU. The linear map region is walked using the pagewalk API and any discovered large leaf mappings are split to pte mappings using the existing helper functions. Since the repainting is performed inside of a stop_machine(), we must use GFP_ATOMIC to allocate the extra intermediate pgtables. But since we are still early in boot, it is expected that there is plenty of memory available so we will never need to sleep for reclaim, and so GFP_ATOMIC is acceptable here. The secondary CPUs are all put into a waiting area with the idmap in TTBR0 and reserved map in TTBR1 while this is performed since they cannot be allowed to observe any size changes on the live mappings. Co-developed-by: Ryan Roberts Signed-off-by: Ryan Roberts Signed-off-by: Yang Shi --- arch/arm64/include/asm/mmu.h | 3 + arch/arm64/kernel/cpufeature.c | 8 ++ arch/arm64/mm/mmu.c | 151 ++++++++++++++++++++++++++++++--- arch/arm64/mm/proc.S | 25 +++++- 4 files changed, 172 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 98565b1b93e8..966c08fd8126 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -56,6 +56,8 @@ typedef struct { */ #define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff) =20 +extern bool linear_map_requires_bbml2; + static inline bool arm64_kernel_unmapped_at_el0(void) { return alternative_has_cap_unlikely(ARM64_UNMAP_KERNEL_AT_EL0); @@ -72,6 +74,7 @@ extern void create_pgd_mapping(struct mm_struct *mm, phys= _addr_t phys, extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t pro= t); extern void mark_linear_text_alias_ro(void); extern int split_kernel_leaf_mapping(unsigned long addr); +extern int linear_map_split_to_ptes(void *__unused); =20 /* * This check is triggered during the early boot before the cpufeature diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f28f056087f3..11392c741e48 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -85,6 +85,7 @@ #include #include #include +#include #include #include #include @@ -2013,6 +2014,12 @@ static int __init __kpti_install_ng_mappings(void *_= _unused) return 0; } =20 +static void __init linear_map_maybe_split_to_ptes(void) +{ + if (linear_map_requires_bbml2 && !system_supports_bbml2_noabort()) + stop_machine(linear_map_split_to_ptes, NULL, cpu_online_mask); +} + static void __init kpti_install_ng_mappings(void) { /* Check whether KPTI is going to be used */ @@ -3930,6 +3937,7 @@ void __init setup_system_features(void) { setup_system_capabilities(); =20 + linear_map_maybe_split_to_ptes(); kpti_install_ng_mappings(); =20 sve_setup(); diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index f6cd79287024..5b5a84b34024 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -27,6 +27,7 @@ #include #include #include +#include =20 #include #include @@ -483,11 +484,11 @@ void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_= t phys, unsigned long virt, =20 #define INVALID_PHYS_ADDR -1 =20 -static phys_addr_t __pgd_pgtable_alloc(struct mm_struct *mm, +static phys_addr_t __pgd_pgtable_alloc(struct mm_struct *mm, gfp_t gfp, enum pgtable_type pgtable_type) { /* Page is zeroed by init_clear_pgtable() so don't duplicate effort. */ - struct ptdesc *ptdesc =3D pagetable_alloc(GFP_PGTABLE_KERNEL & ~__GFP_ZER= O, 0); + struct ptdesc *ptdesc =3D pagetable_alloc(gfp & ~__GFP_ZERO, 0); phys_addr_t pa; =20 if (!ptdesc) @@ -514,9 +515,9 @@ static phys_addr_t __pgd_pgtable_alloc(struct mm_struct= *mm, } =20 static phys_addr_t -try_pgd_pgtable_alloc_init_mm(enum pgtable_type pgtable_type) +try_pgd_pgtable_alloc_init_mm(enum pgtable_type pgtable_type, gfp_t gfp) { - return __pgd_pgtable_alloc(&init_mm, pgtable_type); + return __pgd_pgtable_alloc(&init_mm, gfp, pgtable_type); } =20 static phys_addr_t __maybe_unused @@ -524,7 +525,7 @@ pgd_pgtable_alloc_init_mm(enum pgtable_type pgtable_typ= e) { phys_addr_t pa; =20 - pa =3D __pgd_pgtable_alloc(&init_mm, pgtable_type); + pa =3D __pgd_pgtable_alloc(&init_mm, GFP_PGTABLE_KERNEL, pgtable_type); BUG_ON(pa =3D=3D INVALID_PHYS_ADDR); return pa; } @@ -534,7 +535,7 @@ pgd_pgtable_alloc_special_mm(enum pgtable_type pgtable_= type) { phys_addr_t pa; =20 - pa =3D __pgd_pgtable_alloc(NULL, pgtable_type); + pa =3D __pgd_pgtable_alloc(NULL, GFP_PGTABLE_KERNEL, pgtable_type); BUG_ON(pa =3D=3D INVALID_PHYS_ADDR); return pa; } @@ -548,7 +549,7 @@ static void split_contpte(pte_t *ptep) __set_pte(ptep, pte_mknoncont(__ptep_get(ptep))); } =20 -static int split_pmd(pmd_t *pmdp, pmd_t pmd) +static int split_pmd(pmd_t *pmdp, pmd_t pmd, gfp_t gfp) { pmdval_t tableprot =3D PMD_TYPE_TABLE | PMD_TABLE_UXN | PMD_TABLE_AF; unsigned long pfn =3D pmd_pfn(pmd); @@ -557,7 +558,7 @@ static int split_pmd(pmd_t *pmdp, pmd_t pmd) pte_t *ptep; int i; =20 - pte_phys =3D try_pgd_pgtable_alloc_init_mm(TABLE_PTE); + pte_phys =3D try_pgd_pgtable_alloc_init_mm(TABLE_PTE, gfp); if (pte_phys =3D=3D INVALID_PHYS_ADDR) return -ENOMEM; ptep =3D (pte_t *)phys_to_virt(pte_phys); @@ -590,7 +591,7 @@ static void split_contpmd(pmd_t *pmdp) set_pmd(pmdp, pmd_mknoncont(pmdp_get(pmdp))); } =20 -static int split_pud(pud_t *pudp, pud_t pud) +static int split_pud(pud_t *pudp, pud_t pud, gfp_t gfp) { pudval_t tableprot =3D PUD_TYPE_TABLE | PUD_TABLE_UXN | PUD_TABLE_AF; unsigned int step =3D PMD_SIZE >> PAGE_SHIFT; @@ -600,7 +601,7 @@ static int split_pud(pud_t *pudp, pud_t pud) pmd_t *pmdp; int i; =20 - pmd_phys =3D try_pgd_pgtable_alloc_init_mm(TABLE_PMD); + pmd_phys =3D try_pgd_pgtable_alloc_init_mm(TABLE_PMD, gfp); if (pmd_phys =3D=3D INVALID_PHYS_ADDR) return -ENOMEM; pmdp =3D (pmd_t *)phys_to_virt(pmd_phys); @@ -688,7 +689,7 @@ int split_kernel_leaf_mapping(unsigned long addr) if (!pud_present(pud)) goto out; if (pud_leaf(pud)) { - ret =3D split_pud(pudp, pud); + ret =3D split_pud(pudp, pud, GFP_PGTABLE_KERNEL); if (ret) goto out; } @@ -713,7 +714,7 @@ int split_kernel_leaf_mapping(unsigned long addr) */ if (ALIGN_DOWN(addr, PMD_SIZE) =3D=3D addr) goto out; - ret =3D split_pmd(pmdp, pmd); + ret =3D split_pmd(pmdp, pmd, GFP_PGTABLE_KERNEL); if (ret) goto out; } @@ -738,6 +739,112 @@ int split_kernel_leaf_mapping(unsigned long addr) return ret; } =20 +static int split_to_ptes_pud_entry(pud_t *pudp, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pud_t pud =3D pudp_get(pudp); + int ret =3D 0; + + if (pud_leaf(pud)) + ret =3D split_pud(pudp, pud, GFP_ATOMIC); + + return ret; +} + +static int split_to_ptes_pmd_entry(pmd_t *pmdp, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pmd_t pmd =3D pmdp_get(pmdp); + int ret =3D 0; + + if (pmd_leaf(pmd)) { + if (pmd_cont(pmd)) + split_contpmd(pmdp); + ret =3D split_pmd(pmdp, pmd, GFP_ATOMIC); + } + + return ret; +} + +static int split_to_ptes_pte_entry(pte_t *ptep, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pte_t pte =3D __ptep_get(ptep); + + if (pte_cont(pte)) + split_contpte(ptep); + + return 0; +} + +static const struct mm_walk_ops split_to_ptes_ops =3D { + .pud_entry =3D split_to_ptes_pud_entry, + .pmd_entry =3D split_to_ptes_pmd_entry, + .pte_entry =3D split_to_ptes_pte_entry, +}; + +extern u32 repaint_done; + +int __init linear_map_split_to_ptes(void *__unused) +{ + /* + * Repainting the linear map must be done by CPU0 (the boot CPU) because + * that's the only CPU that we know supports BBML2. The other CPUs will + * be held in a waiting area with the idmap active. + */ + if (!smp_processor_id()) { + unsigned long lstart =3D _PAGE_OFFSET(vabits_actual); + unsigned long lend =3D PAGE_END; + unsigned long kstart =3D (unsigned long)lm_alias(_stext); + unsigned long kend =3D (unsigned long)lm_alias(__init_begin); + int ret; + + /* + * Wait for all secondary CPUs to be put into the waiting area. + */ + smp_cond_load_acquire(&repaint_done, VAL =3D=3D num_online_cpus()); + + /* + * Walk all of the linear map [lstart, lend), except the kernel + * linear map alias [kstart, kend), and split all mappings to + * PTE. The kernel alias remains static throughout runtime so + * can continue to be safely mapped with large mappings. + */ + ret =3D walk_kernel_page_table_range_lockless(lstart, kstart, + &split_to_ptes_ops, NULL); + if (!ret) + ret =3D walk_kernel_page_table_range_lockless(kend, lend, + &split_to_ptes_ops, NULL); + if (ret) + panic("Failed to split linear map\n"); + flush_tlb_kernel_range(lstart, lend); + + /* + * Relies on dsb in flush_tlb_kernel_range() to avoid reordering + * before any page table split operations. + */ + WRITE_ONCE(repaint_done, 0); + } else { + typedef void (repaint_wait_fn)(void); + extern repaint_wait_fn bbml2_wait_for_repainting; + repaint_wait_fn *wait_fn; + + wait_fn =3D (void *)__pa_symbol(bbml2_wait_for_repainting); + + /* + * At least one secondary CPU doesn't support BBML2 so cannot + * tolerate the size of the live mappings changing. So have the + * secondary CPUs wait for the boot CPU to make the changes + * with the idmap active and init_mm inactive. + */ + cpu_install_idmap(); + wait_fn(); + cpu_uninstall_idmap(); + } + + return 0; +} + /* * This function can only be used to modify existing table entries, * without allocating new levels of table. Note that this permits the @@ -857,6 +964,8 @@ static inline void arm64_kfence_map_pool(phys_addr_t kf= ence_pool, pgd_t *pgdp) { =20 #endif /* CONFIG_KFENCE */ =20 +bool linear_map_requires_bbml2; + static inline bool force_pte_mapping(void) { bool bbml2 =3D system_capabilities_finalized() ? @@ -892,6 +1001,8 @@ static void __init map_mem(pgd_t *pgdp) =20 early_kfence_pool =3D arm64_kfence_alloc_pool(); =20 + linear_map_requires_bbml2 =3D !force_pte_mapping() && can_set_direct_map(= ); + if (force_pte_mapping()) flags |=3D NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; =20 @@ -1025,7 +1136,8 @@ void __pi_map_range(u64 *pgd, u64 start, u64 end, u64= pa, pgprot_t prot, int level, pte_t *tbl, bool may_use_cont, u64 va_offset); =20 static u8 idmap_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __r= o_after_init, - kpti_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_= init; + kpti_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_= init, + bbml2_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after= _init; =20 static void __init create_idmap(void) { @@ -1050,6 +1162,19 @@ static void __init create_idmap(void) IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, __phys_to_virt(ptep) - ptep); } + + /* + * Setup idmap mapping for repaint_done flag. It will be used if + * repainting the linear mapping is needed later. + */ + if (linear_map_requires_bbml2) { + u64 pa =3D __pa_symbol(&repaint_done); + + ptep =3D __pa_symbol(bbml2_ptes); + __pi_map_range(&ptep, pa, pa + sizeof(u32), pa, PAGE_KERNEL, + IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, + __phys_to_virt(ptep) - ptep); + } } =20 void __init paging_init(void) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 8c75965afc9e..dbaac2e824d7 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -416,7 +416,29 @@ alternative_else_nop_endif __idmap_kpti_secondary: /* Uninstall swapper before surgery begins */ __idmap_cpu_set_reserved_ttbr1 x16, x17 + b scondary_cpu_wait =20 + .unreq swapper_ttb + .unreq flag_ptr +SYM_FUNC_END(idmap_kpti_install_ng_mappings) + .popsection +#endif + + .pushsection ".data", "aw", %progbits +SYM_DATA(repaint_done, .long 1) + .popsection + + .pushsection ".idmap.text", "a" +SYM_TYPED_FUNC_START(bbml2_wait_for_repainting) + /* Must be same registers as in idmap_kpti_install_ng_mappings */ + swapper_ttb .req x3 + flag_ptr .req x4 + + mrs swapper_ttb, ttbr1_el1 + adr_l flag_ptr, repaint_done + __idmap_cpu_set_reserved_ttbr1 x16, x17 + +scondary_cpu_wait: /* Increment the flag to let the boot CPU we're ready */ 1: ldxr w16, [flag_ptr] add w16, w16, #1 @@ -436,9 +458,8 @@ __idmap_kpti_secondary: =20 .unreq swapper_ttb .unreq flag_ptr -SYM_FUNC_END(idmap_kpti_install_ng_mappings) +SYM_FUNC_END(bbml2_wait_for_repainting) .popsection -#endif =20 /* * __cpu_setup --=20 2.43.0