From nobody Sun Oct 5 12:49:50 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B41602459FE; Tue, 5 Aug 2025 07:48:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380124; cv=none; b=g0EpEOgN7RoMVyHWA2qt0KvT0sQkzjnmJqf+r48bDKARIHeXy/R2FRGA4h/3oEg9u4IsrHerrJycaL65guAwRfmq28SXp/ENc1baGB/f1jGy53aZhNNt6GDC1KXZT0mV1j6tFemYCqOY18mdlGWnGKI5+PcABGVIDap8gAEVWLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380124; c=relaxed/simple; bh=tJ7o+S9MAcZ9O3MH3doLENuVw9J+TQdb5QZwH7DfNpQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lW9kvB9zhVgmwzFl/49/bDl3qOv2op53WthYqzLtK8wSD5jxkvgmV4C2YWeJPSK+X1ZbgJiW1alwCM3tpNFNgabgUICkGYY/tUi/0WJztP6Jb6koh/HcWu0rxsWf2dKsM8EI9qJ4YY/+AQrIgmzbI5zNKkJseXKb6jaAuTAMKD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Te7FJuIY; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Te7FJuIY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754380121; bh=tJ7o+S9MAcZ9O3MH3doLENuVw9J+TQdb5QZwH7DfNpQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Te7FJuIYX4k8bxrEzVJiBqwlSeToot3AKjttZZfEOcss2xzPB8DLGPpWLr9pVAz6J MGYAB8mwkGZCI1QCEpuGWFXKjbg3mjV3fctSRqLDflqwPCzg/F/F7nZTmWu85+CQVd IDWhFOybo3A7iW0AJXtRN54RcRkfonVxpp5XQ6pDthTQlxdSI3V4oDHhmpWC7MhM++ d7qlvKueRic9HFOI3r9Wn7AeV0OY3rQbJehTgsR0aoPzpADAPviJx2NTrkmX+XNTZz HtYlgew1Yc/fJ7v8CAR+h/pwQPYYFxP5z0F1bvAvLzNp/jTx03t3RY8x6SGJsx5yUr ut47shYnDfKjg== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4BA0417E09F0; Tue, 5 Aug 2025 09:48:40 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 05/10] pmdomain: mediatek: Handle SoCs with inverted SRAM power-down bits Date: Tue, 5 Aug 2025 09:47:41 +0200 Message-ID: <20250805074746.29457-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some SoCs, and even some subsystems in the same SoC, may have the logic for SRAM power-down inverted, as in, setting the bit means "power down" and unsetting means "power up": this is because some hardware subsystems use this as a power-lock indication and some use this as a power down one (for example, usually, the modem ss has it inverted!). In preparation for adding support for power domains with inverted SRAM_PDN bits, add a new MTK_SCPD_SRAM_PDN_INVERTED flag and check for it in scpsys_sram_enable() and scpsys_sram_disable(). Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 27 ++++++++++++++++------ drivers/pmdomain/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index 48dc5f188438..6118a389244a 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -79,16 +79,23 @@ static bool scpsys_domain_is_on(struct scpsys_domain *p= d) =20 static int scpsys_sram_enable(struct scpsys_domain *pd) { - u32 pdn_ack =3D pd->data->sram_pdn_ack_bits; + u32 expected_ack, pdn_ack =3D pd->data->sram_pdn_ack_bits; struct scpsys *scpsys =3D pd->scpsys; unsigned int tmp; int ret; =20 - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bi= ts); + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_PDN_INVERTED)) { + regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bit= s); + expected_ack =3D pdn_ack; + } else { + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_b= its); + expected_ack =3D 0; + } =20 /* Either wait until SRAM_PDN_ACK all 1 or 0 */ ret =3D regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) =3D=3D 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + (tmp & pdn_ack) =3D=3D expected_ack, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret < 0) return ret; =20 @@ -103,7 +110,7 @@ static int scpsys_sram_enable(struct scpsys_domain *pd) =20 static int scpsys_sram_disable(struct scpsys_domain *pd) { - u32 pdn_ack =3D pd->data->sram_pdn_ack_bits; + u32 expected_ack, pdn_ack =3D pd->data->sram_pdn_ack_bits; struct scpsys *scpsys =3D pd->scpsys; unsigned int tmp; =20 @@ -113,12 +120,18 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BI= T); } =20 - regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits= ); + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_PDN_INVERTED)) { + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_b= its); + expected_ack =3D 0; + } else { + regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bit= s); + expected_ack =3D pdn_ack; + } =20 /* Either wait until SRAM_PDN_ACK all 1 or 0 */ return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) =3D=3D pdn_ack, MTK_POLL_DELAY_US, - MTK_POLL_TIMEOUT); + (tmp & pdn_ack) =3D=3D expected_ack, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *= pd, diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/= mediatek/mtk-pm-domains.h index 4f2d331a866a..fbbfb23a8739 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -13,6 +13,7 @@ #define MTK_SCPD_EXT_BUCK_ISO BIT(6) #define MTK_SCPD_HAS_INFRA_NAO BIT(7) #define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) +#define MTK_SCPD_SRAM_PDN_INVERTED BIT(9) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 --=20 2.50.1