From nobody Sun Oct 5 12:49:53 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBEFB1448D5; Tue, 5 Aug 2025 07:48:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380121; cv=none; b=TaH1+vNxpaOCNffvZ5NOqNZbuxhAppOMvbILxsOK4mIfFd5L0vVvGFVXm8CMQ163C0yuulZNUp6HrNxgLbclZ9eoWNbtN76m2thQ9lQzYOZJhXr4ME4Hzn2OQZnZUxAymb9NkAs997c6XsPuInwR4ctbSSVk671Tu1IL2Q4LsH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380121; c=relaxed/simple; bh=/oEzo87CWaILm9HqGt46UkB1R49zirOV8M9U5d5DHgI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QCNjbxVZ559fDLf4Jg0pWxvQCzwH6qlgn2KMG0NxY4nOFKvc5niJ5nPNvUpS/eZY2g3pewDidEb0LFfFPFWZxtjmRN61I2wv/SC/gkNRWLY49HOoZ4vCMAdUUFYgbaN7iQlEIb9lzKezP/3aBY/2yANMENTtuIHXccTIHAmHWRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=qo/XefdI; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="qo/XefdI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754380118; bh=/oEzo87CWaILm9HqGt46UkB1R49zirOV8M9U5d5DHgI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qo/XefdIZj+0wfo2YP4SMJjNvwX/+WzpylDDXDA8tHLJdRxt1X45pX+jCCeMJmeds hojv6171/r5As9fc51/SoJDhdnZu7FJcEOiY6YaNN5V6QZE16A0VHcV5RHjtssXegv IaTCp595id5m10xALd8XLxGTLqxk+rbJFvaRSbdPwsPPyolobvxHpKKTmsHVos0oyX Vm8utEtYr6KTFYy5ls5uXRitAlrST3vnjavJ+LnPsNq5KG9FsG1ZIN4huDnMjQ494x xw3VhC4OsczT5Ki10QgC51lCYKJp/ik5s/sBU43YyG/2stvF7wkRubp6aUssQ8SfjA yfjOL/V8sWoaQ== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4AB6C17E046C; Tue, 5 Aug 2025 09:48:37 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 02/10] dt-bindings: clock: mediatek: Document #access-controller-cells Date: Tue, 5 Aug 2025 09:47:38 +0200 Message-ID: <20250805074746.29457-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Allow the #access-controller-cells property on all of the infracfg controllers on all MediaTek SoCs, as this always acts as an access control provider. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/clock/mediatek,infracfg.yaml | 3 +++ .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8192-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8195-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8365-sys-clock.yaml | 15 +++++++++++++++ 6 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml= b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml index d1d30700d9b0..27f1a31c3424 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml @@ -47,6 +47,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index 1c446fbc5108..2a1bf9073b7d 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -36,6 +36,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -48,6 +51,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8186-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-cloc= k.yaml index db13d51a4903..08472d363e8a 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml @@ -36,6 +36,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -49,6 +52,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8188-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | clock-controller@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cloc= k.yaml index bf8c9aacdf1e..f1ab8b0e0a98 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml @@ -26,6 +26,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -38,6 +41,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8192-infracfg +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cloc= k.yaml index 69f096eb168d..dcce8b188e4f 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml @@ -34,6 +34,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -46,6 +49,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8195-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-cloc= k.yaml index 643f84660c8e..b6f074f98db7 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml @@ -28,6 +28,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -38,6 +41,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8365-infracfg +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: clock-controller@10000000 { --=20 2.50.1