From nobody Sun Oct 5 10:48:54 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCE842E36E7; Tue, 5 Aug 2025 07:48:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380121; cv=none; b=f53NR7yRhxY6i8D9yezFoG2ovEHKSSCg8/ufgJ0Ic+b8kjZrnZyqSNiEB7Fp+X/TcQ587s8T6KgHKPiCrPYjM9Nxa2ExLpMHjqzbg7D7BAizQbb/zOfDQrbah9nmqCNMfzf2N9c9Vk5q0k+GsaffQn9qAHrOTjfQGM9PYED91SU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380121; c=relaxed/simple; bh=peebc5D4PFcvcgaCd/44d7/8DsPYW5IriESnKwJISdc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R8ZbMrpYGmh3vBoGhy4k5gRYej+POqaGdmvH6Z805XVP827LaZiBMO/bt8B7upKnFc0EQqqyvGt+UMzUPuLIbabsKf143yR54wyDhevTNoE9AVKjD0s1x5+PzIVccJPfx6YA5RK/9e25R4foLf3LNaQKIFbW5d/sqWQRYafJ0Vg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=UtO4vteF; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="UtO4vteF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754380117; bh=peebc5D4PFcvcgaCd/44d7/8DsPYW5IriESnKwJISdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UtO4vteFeGNcUgmceJe9WifkMc+NLe4PvZeNI7V9Rh/tt9s4MK3VuSCEezOBNtbOc x1+EabNFKu/4USudy6HBFBhQbdxIm5yEc7MUVMdo54HLUh8uOi8j9Wytcq95M9tA4I I17ajIGkaQsIqZ0wLZRw6Un2Qxq7aFwzKu1Z4RWiO7k6sDt1r3HqRR3vau9qBDfjP5 rVK60MjiKpaLwsTBfwBPgB31UmAXFqoSwMDWBLf3gJ37g9jIIULQ8u1thwk3U+EwN7 Rrptq/99ufFh7nainMmMODy/NYYUDbQ3TlfCQhG85VChebSJQIEZfukc77lnEOCG84 l5e3MiXehwRqQ== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4CB9D17E0286; Tue, 5 Aug 2025 09:48:36 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 01/10] dt-bindings: memory: mtk-smi: Document #access-controller-cells Date: Tue, 5 Aug 2025 09:47:37 +0200 Message-ID: <20250805074746.29457-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some of the SMI Common HW provides access control to at least the power controller: document the #access-controller-cells property and allow specifying it only for MT8183 and MT8365 as those are the only known SoCs with an SMI acting as access controller. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- .../memory-controllers/mediatek,smi-common.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/medi= atek,smi-common.yaml index 0762e0ff66ef..74b355a08493 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml @@ -74,6 +74,9 @@ properties: minItems: 2 maxItems: 4 =20 + '#access-controller-cells': + const: 0 + mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: a phandle to the smi-common node above. Only for sub-comm= on. @@ -168,6 +171,19 @@ allOf: - const: apb - const: smi =20 + - if: # for SMI providing access control + properties: + compatible: + enum: + - mediatek,mt8183-smi-common + - mediatek,mt8365-smi-common + then: + properties: + '#access-controller-cells': true + else: + properties: + '#access-controller-cells': false + additionalProperties: false =20 examples: --=20 2.50.1 From nobody Sun Oct 5 10:48:54 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBEFB1448D5; Tue, 5 Aug 2025 07:48:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380121; cv=none; b=TaH1+vNxpaOCNffvZ5NOqNZbuxhAppOMvbILxsOK4mIfFd5L0vVvGFVXm8CMQ163C0yuulZNUp6HrNxgLbclZ9eoWNbtN76m2thQ9lQzYOZJhXr4ME4Hzn2OQZnZUxAymb9NkAs997c6XsPuInwR4ctbSSVk671Tu1IL2Q4LsH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380121; c=relaxed/simple; bh=/oEzo87CWaILm9HqGt46UkB1R49zirOV8M9U5d5DHgI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QCNjbxVZ559fDLf4Jg0pWxvQCzwH6qlgn2KMG0NxY4nOFKvc5niJ5nPNvUpS/eZY2g3pewDidEb0LFfFPFWZxtjmRN61I2wv/SC/gkNRWLY49HOoZ4vCMAdUUFYgbaN7iQlEIb9lzKezP/3aBY/2yANMENTtuIHXccTIHAmHWRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=qo/XefdI; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="qo/XefdI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754380118; bh=/oEzo87CWaILm9HqGt46UkB1R49zirOV8M9U5d5DHgI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qo/XefdIZj+0wfo2YP4SMJjNvwX/+WzpylDDXDA8tHLJdRxt1X45pX+jCCeMJmeds hojv6171/r5As9fc51/SoJDhdnZu7FJcEOiY6YaNN5V6QZE16A0VHcV5RHjtssXegv IaTCp595id5m10xALd8XLxGTLqxk+rbJFvaRSbdPwsPPyolobvxHpKKTmsHVos0oyX Vm8utEtYr6KTFYy5ls5uXRitAlrST3vnjavJ+LnPsNq5KG9FsG1ZIN4huDnMjQ494x xw3VhC4OsczT5Ki10QgC51lCYKJp/ik5s/sBU43YyG/2stvF7wkRubp6aUssQ8SfjA yfjOL/V8sWoaQ== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4AB6C17E046C; Tue, 5 Aug 2025 09:48:37 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 02/10] dt-bindings: clock: mediatek: Document #access-controller-cells Date: Tue, 5 Aug 2025 09:47:38 +0200 Message-ID: <20250805074746.29457-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Allow the #access-controller-cells property on all of the infracfg controllers on all MediaTek SoCs, as this always acts as an access control provider. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/clock/mediatek,infracfg.yaml | 3 +++ .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8192-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8195-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8365-sys-clock.yaml | 15 +++++++++++++++ 6 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml= b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml index d1d30700d9b0..27f1a31c3424 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml @@ -47,6 +47,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index 1c446fbc5108..2a1bf9073b7d 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -36,6 +36,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -48,6 +51,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8186-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-cloc= k.yaml index db13d51a4903..08472d363e8a 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml @@ -36,6 +36,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -49,6 +52,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8188-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | clock-controller@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cloc= k.yaml index bf8c9aacdf1e..f1ab8b0e0a98 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml @@ -26,6 +26,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -38,6 +41,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8192-infracfg +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cloc= k.yaml index 69f096eb168d..dcce8b188e4f 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml @@ -34,6 +34,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -46,6 +49,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8195-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 { diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-cloc= k.yaml index 643f84660c8e..b6f074f98db7 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml @@ -28,6 +28,9 @@ properties: reg: maxItems: 1 =20 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1 =20 @@ -38,6 +41,18 @@ required: =20 additionalProperties: false =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8365-infracfg +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: clock-controller@10000000 { --=20 2.50.1 From nobody Sun Oct 5 10:48:54 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C0F8235BE8; Tue, 5 Aug 2025 07:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380123; cv=none; b=LdSMql9ccBhEzcBZmb4u182esDCZi8Y2GRlFuKChbAofpS8alGsxdjt2JunybNW7l9sI1rG4n+2bQLdjdbMn4mIgdna6f+f7FUp2BIngaZv06sVY3XJGW+WxunK/QMjxtYu+/S5A6dkUV+3DlV7G1Vwn9YZB24OTkCuk5CgKVfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380123; c=relaxed/simple; bh=t7Rehz1Jrb0D0nap14L/kwRSRhOnQ0fHBCl9LYwxpeg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k+n2spN9kaZNKqDI2JtLZPua+289qI/pwyPw4cgmf3SO3wnGP5b5yPiseGUBmJ3k4d4iP6t0dqSdd89CvVS0X9DoSNX7qiLxBPvA8xMMEiwEcS63CtcPHa4GDeP2/ewDQdYIlqaEdeqO1ZkI3BlX20G5NvYSQGzBhAFJlgJH+nc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=qqZTmbMe; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="qqZTmbMe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754380119; bh=t7Rehz1Jrb0D0nap14L/kwRSRhOnQ0fHBCl9LYwxpeg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qqZTmbMeyuJR1FWoWPIBn1q+u7lDZJx4B4wh8yjAynf3RZJxGZ/opTOFlFSkWsW1S iBtcbDLbFd/TLDVUf/tY69GZWW8AhBPmfkDtHiDyxwTisq5hqv5JRtiug6edzvMT8B woC6N3DzykUt9EJ4eDT+1kg671SfdT8VD2D5pIrsRGVo64VbOOENky9pRjHTv5TVNE o0687OyuN3EnnLhUjtELTcm9Cn00gabEy6gpe7F2omk2ME0PQsUIkq1gMLRuHP+Sm8 mwupupeSJbWle1e6j2jSyP5V+ZPbdSDNt7zI7Z4X4HaEI9Vr8Y/uJf/kcf4mEWDJCm fL4J9S+Dx3LVg== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4CBB117E07E6; Tue, 5 Aug 2025 09:48:38 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 03/10] dt-bindings: power: mediatek: Document access-controllers property Date: Tue, 5 Aug 2025 09:47:39 +0200 Message-ID: <20250805074746.29457-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Allow specifying access-controllers in the main power controller node and deprecate the old mediatek,infracfg, mediatek,infracfg-nao and mediatek,smi properties located in the children. This is done in order to both simplify the power controller nodes and in preparation for adding support for new generation SoCs like MT8196/MT6991 and other variants, which will need to set protection on new busses. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- .../power/mediatek,power-controller.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 9c7cc632abee..500d98921581 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -44,6 +44,15 @@ properties: '#size-cells': const: 0 =20 + access-controllers: + description: + A number of phandles to external blocks to set and clear the required + bits to enable or disable bus protection, necessary to avoid any bus + faults while enabling or disabling a power domain. + For example, this may hold phandles to INFRACFG and SMI. + minItems: 1 + maxItems: 3 + patternProperties: "^power-domain@[0-9a-f]+$": $ref: "#/$defs/power-domain-node" @@ -123,14 +132,17 @@ $defs: mediatek,infracfg: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG registe= r range. + deprecated: true =20 mediatek,infracfg-nao: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG-NAO reg= ister range. + deprecated: true =20 mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register ran= ge. + deprecated: true =20 required: - reg @@ -138,6 +150,31 @@ $defs: required: - compatible =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8183-power-controller + then: + properties: + access-controllers: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8365-power-controller + then: + properties: + access-controllers: + minItems: 3 + maxItems: 3 + additionalProperties: false =20 examples: --=20 2.50.1 From nobody Sun Oct 5 10:48:54 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54BB246326; 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Tue, 5 Aug 2025 09:48:39 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 04/10] pmdomain: mediatek: Refactor bus protection regmaps retrieval Date: Tue, 5 Aug 2025 09:47:40 +0200 Message-ID: <20250805074746.29457-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In preparation to add support for new generation SoCs like MT8196, MT6991 and other variants, which require to set bus protection on different busses than the ones found on legacy chips, and to also simplify and reduce memory footprint of this driver, refactor the mechanism to retrieve and use the bus protection regmaps. This is done by removing the three pointers to struct regmap from struct scpsys_domain (allocated for each power domain) and moving them to the main struct scpsys (allocated per driver instance) as an array of pointers to regmap named **bus_prot. That deprecates the old devicetree properties to grab phandles to the three predefined busses (infracfg, infracfg-nao and smi) and replaces it with the base property "access-controllers" that is meant to be an array of phandles holding the same busses where required (for now - for legacy SoCs). The new bus protection phandles are indexed by the bus_prot_index member of struct scpsys, used to map "bus type" (ex.: infra, smi, etc) to the specific *bus_prot[x] element. While the old per-power-domain regmap pointers were removed, the support for old devicetree was retained by still checking if the new property (in DT) and new-style declaration (in SoC specific platform data) are both present at probe time. If those are not present, a lookup for the old properties will be done in all of the children of the power controller, and pointers to regmaps will be retrieved with the old properties, but then will be internally remapped to follow the new style regmap anyway as to let this driver benefit of the memory footprint reduction. Finally, it was necessary to change macros in mtk-pm-domains.h and in mt8365-pm-domains.h to make use of the new style bus protection declaration, as the actual HW block is now recognized not by flags but by its own scpsys_bus_prot_block enumeration. The BUS_PROT_(STA)_COMPONENT_{INFRA,INFRA_NAO,SMI} flags were also removed since they are now unused, and because that enumeration was initially meant to vary the logic of bus protection and not the bus where work is performed, anyway! Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mt8365-pm-domains.h | 8 +- drivers/pmdomain/mediatek/mtk-pm-domains.c | 188 ++++++++++++++---- drivers/pmdomain/mediatek/mtk-pm-domains.h | 53 +++-- 3 files changed, 187 insertions(+), 62 deletions(-) diff --git a/drivers/pmdomain/mediatek/mt8365-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8365-pm-domains.h index 3d83d49eaa7c..6fbd5ef8d672 100644 --- a/drivers/pmdomain/mediatek/mt8365-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8365-pm-domains.h @@ -29,11 +29,9 @@ MT8365_SMI_COMMON_CLAMP_EN) =20 #define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \ - _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \ - BUS_PROT_COMPONENT_INFRA | \ - BUS_PROT_STA_COMPONENT_INFRA_NAO | \ - BUS_PROT_INVERTED | \ - BUS_PROT_REG_UPDATE) + _BUS_PROT_STA(INFRA, INFRA_NAO, _set_mask, _set, _set, \ + _sta_mask, _sta, \ + BUS_PROT_INVERTED | BUS_PROT_REG_UPDATE) =20 static const struct scpsys_domain_data scpsys_domain_data_mt8365[] =3D { [MT8365_POWER_DOMAIN_MM] =3D { diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index a58ed7e2d9a4..48dc5f188438 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -47,9 +47,6 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; - struct regmap *infracfg_nao; - struct regmap *infracfg; - struct regmap *smi; struct regulator *supply; }; =20 @@ -57,6 +54,8 @@ struct scpsys { struct device *dev; struct regmap *base; const struct scpsys_soc_data *soc_data; + u8 bus_prot_index[BUS_PROT_BLOCK_COUNT]; + struct regmap **bus_prot; struct genpd_onecell_data pd_data; struct generic_pm_domain *domains[]; }; @@ -125,19 +124,19 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *= pd, const struct scpsys_bus_prot_data *bpd) { - if (bpd->flags & BUS_PROT_COMPONENT_SMI) - return pd->smi; - else - return pd->infracfg; + struct scpsys *scpsys =3D pd->scpsys; + unsigned short block_idx =3D scpsys->bus_prot_index[bpd->bus_prot_block]; + + return scpsys->bus_prot[block_idx]; } =20 static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_doma= in *pd, const struct scpsys_bus_prot_data *bpd) { - if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO) - return pd->infracfg_nao; - else - return scpsys_bus_protect_get_regmap(pd, bpd); + struct scpsys *scpsys =3D pd->scpsys; + int block_idx =3D scpsys->bus_prot_index[bpd->bus_prot_sta_block]; + + return scpsys->bus_prot[block_idx]; } =20 static int scpsys_bus_protect_clear(struct scpsys_domain *pd, @@ -149,7 +148,7 @@ static int scpsys_bus_protect_clear(struct scpsys_domai= n *pd, u32 expected_ack; u32 val; =20 - expected_ack =3D (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mas= k : 0); + expected_ack =3D (bpd->bus_prot_sta_block =3D=3D BUS_PROT_BLOCK_INFRA_NAO= ? sta_mask : 0); =20 if (bpd->flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); @@ -355,7 +354,6 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys = *scpsys, struct device_no { const struct scpsys_domain_data *domain_data; struct scpsys_domain *pd; - struct device_node *smi_node; struct property *prop; const char *clk_name; int i, ret, num_clks; @@ -396,32 +394,6 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no node); } =20 - pd->infracfg =3D syscon_regmap_lookup_by_phandle_optional(node, "mediatek= ,infracfg"); - if (IS_ERR(pd->infracfg)) - return dev_err_cast_probe(scpsys->dev, pd->infracfg, - "%pOF: failed to get infracfg regmap\n", - node); - - smi_node =3D of_parse_phandle(node, "mediatek,smi", 0); - if (smi_node) { - pd->smi =3D device_node_to_regmap(smi_node); - of_node_put(smi_node); - if (IS_ERR(pd->smi)) - return dev_err_cast_probe(scpsys->dev, pd->smi, - "%pOF: failed to get SMI regmap\n", - node); - } - - if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) { - pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle(node, "mediatek,inf= racfg-nao"); - if (IS_ERR(pd->infracfg_nao)) - return dev_err_cast_probe(scpsys->dev, pd->infracfg_nao, - "%pOF: failed to get infracfg-nao regmap\n", - node); - } else { - pd->infracfg_nao =3D NULL; - } - num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ @@ -615,6 +587,136 @@ static void scpsys_domain_cleanup(struct scpsys *scps= ys) } } =20 +static int scpsys_get_bus_protection_legacy(struct device *dev, struct scp= sys *scpsys) +{ + const u8 bp_blocks[3] =3D { + BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI, BUS_PROT_BLOCK_INFRA_NAO + }; + struct device_node *np =3D dev->of_node; + struct device_node *node, *smi_np; + int num_regmaps =3D 0, i, j; + struct regmap *regmap[3]; + + /* + * Legacy code retrieves a maximum of three bus protection handles: + * some may be optional, or may not be, so the array of bp blocks + * that is normally passed in as platform data must be dynamically + * built in this case. + * + * Here, try to retrieve all of the regmaps that the legacy code + * supported and then count the number of the ones that are present, + * this makes it then possible to allocate the array of bus_prot + * regmaps and convert all to the new style handling. + */ + node =3D of_find_node_with_property(np, "mediatek,infracfg"); + if (node) { + regmap[0] =3D syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg"); + of_node_put(node); + num_regmaps++; + if (IS_ERR(regmap[0])) + return dev_err_probe(dev, PTR_ERR(regmap[0]), + "%pOF: failed to get infracfg regmap\n", + node); + } else { + regmap[0] =3D NULL; + } + + node =3D of_find_node_with_property(np, "mediatek,smi"); + if (node) { + smi_np =3D of_parse_phandle(node, "mediatek,smi", 0); + of_node_put(node); + if (!smi_np) + return -ENODEV; + + regmap[1] =3D device_node_to_regmap(smi_np); + num_regmaps++; + of_node_put(smi_np); + if (IS_ERR(regmap[1])) + return dev_err_probe(dev, PTR_ERR(regmap[1]), + "%pOF: failed to get SMI regmap\n", + node); + } else { + regmap[1] =3D NULL; + } + + node =3D of_find_node_with_property(np, "mediatek,infracfg-nao"); + if (node) { + regmap[2] =3D syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-n= ao"); + num_regmaps++; + of_node_put(node); + if (IS_ERR(regmap[2])) + return dev_err_probe(dev, PTR_ERR(regmap[2]), + "%pOF: failed to get infracfg regmap\n", + node); + } else { + regmap[2] =3D NULL; + } + + scpsys->bus_prot =3D devm_kmalloc_array(dev, num_regmaps, + sizeof(*scpsys->bus_prot), GFP_KERNEL); + if (!scpsys->bus_prot) + return -ENOMEM; + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(bp_blocks); i++) { + enum scpsys_bus_prot_block bp_type; + + if (!regmap[i]) + continue; + + bp_type =3D bp_blocks[i]; + scpsys->bus_prot_index[bp_type] =3D j; + scpsys->bus_prot[j] =3D regmap[i]; + + j++; + } + + return 0; +} + +static int scpsys_get_bus_protection(struct device *dev, struct scpsys *sc= psys) +{ + const struct scpsys_soc_data *soc =3D scpsys->soc_data; + struct device_node *np =3D dev->of_node; + int i, num_handles; + + num_handles =3D of_count_phandle_with_args(np, "access-controllers", NULL= ); + if (num_handles < 0 || num_handles !=3D soc->num_bus_prot_blocks) + return dev_err_probe(dev, -EINVAL, + "Cannot get access controllers: expected %u, got %d\n", + soc->num_bus_prot_blocks, num_handles); + + scpsys->bus_prot =3D devm_kmalloc_array(dev, soc->num_bus_prot_blocks, + sizeof(*scpsys->bus_prot), GFP_KERNEL); + if (!scpsys->bus_prot) + return -ENOMEM; + + for (i =3D 0; i < soc->num_bus_prot_blocks; i++) { + enum scpsys_bus_prot_block bp_type; + struct device_node *node; + + node =3D of_parse_phandle(np, "access-controllers", i); + if (!node) + return -EINVAL; + + /* + * Index the bus protection regmaps so that we don't have to + * find the right one by type with a loop at every execution + * of power sequence(s). + */ + bp_type =3D soc->bus_prot_blocks[i]; + scpsys->bus_prot_index[bp_type] =3D i; + + scpsys->bus_prot[i] =3D device_node_to_regmap(node); + of_node_put(node); + if (IS_ERR_OR_NULL(scpsys->bus_prot[i])) + return dev_err_probe(dev, scpsys->bus_prot[i] ? + PTR_ERR(scpsys->bus_prot[i]) : -ENXIO, + "Cannot get regmap for access controller %d\n", i); + } + + return 0; +} + static const struct of_device_id scpsys_of_match[] =3D { { .compatible =3D "mediatek,mt6735-power-controller", @@ -701,6 +803,14 @@ static int scpsys_probe(struct platform_device *pdev) return PTR_ERR(scpsys->base); } =20 + if (of_find_property(np, "access-controllers", NULL)) + ret =3D scpsys_get_bus_protection(dev, scpsys); + else + ret =3D scpsys_get_bus_protection_legacy(dev, scpsys); + + if (ret) + return ret; + ret =3D -ENODEV; for_each_available_child_of_node(np, node) { struct generic_pm_domain *domain; diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/= mediatek/mtk-pm-domains.h index 7085fa2976e9..4f2d331a866a 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -50,30 +50,43 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE =3D BIT(1), BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), BUS_PROT_INVERTED =3D BIT(3), - BUS_PROT_COMPONENT_INFRA =3D BIT(4), - BUS_PROT_COMPONENT_SMI =3D BIT(5), - BUS_PROT_STA_COMPONENT_INFRA_NAO =3D BIT(6), }; =20 -#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ - .bus_prot_set_clr_mask =3D (_set_clr_mask), \ - .bus_prot_set =3D _set, \ - .bus_prot_clr =3D _clr, \ - .bus_prot_sta_mask =3D (_sta_mask), \ - .bus_prot_sta =3D _sta, \ - .flags =3D _flags \ +enum scpsys_bus_prot_block { + BUS_PROT_BLOCK_INFRA, + BUS_PROT_BLOCK_INFRA_NAO, + BUS_PROT_BLOCK_SMI, + BUS_PROT_BLOCK_COUNT, +}; + +#define _BUS_PROT_STA(_hwip, _sta_hwip, _set_clr_mask, _set, _clr, \ + _sta_mask, _sta, _flags) \ + { \ + .bus_prot_block =3D BUS_PROT_BLOCK_##_hwip, \ + .bus_prot_sta_block =3D BUS_PROT_BLOCK_##_sta_hwip, \ + .bus_prot_set_clr_mask =3D (_set_clr_mask), \ + .bus_prot_set =3D _set, \ + .bus_prot_clr =3D _clr, \ + .bus_prot_sta_mask =3D (_sta_mask), \ + .bus_prot_sta =3D _sta, \ + .flags =3D _flags \ } =20 -#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip) +#define _BUS_PROT(_hwip, _set_clr_mask, _set, _clr, _sta_mask, \ + _sta, _flags) \ + _BUS_PROT_STA(_hwip, _hwip, _set_clr_mask, _set, _clr, \ + _sta_mask, _sta, _flags) + +#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, 0) =20 -#define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ - BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK) +#define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ + BUS_PROT_IGNORE_CLR_ACK) =20 -#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ - BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE) +#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ + BUS_PROT_REG_UPDATE) =20 #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(INFRA, _mask, \ @@ -82,6 +95,8 @@ enum scpsys_bus_prot_flags { INFRA_TOPAXI_PROTECTSTA1) =20 struct scpsys_bus_prot_data { + u8 bus_prot_block; + u8 bus_prot_sta_block; u32 bus_prot_set_clr_mask; u32 bus_prot_set; u32 bus_prot_clr; @@ -119,6 +134,8 @@ struct scpsys_domain_data { struct scpsys_soc_data { const struct scpsys_domain_data *domains_data; int num_domains; + enum scpsys_bus_prot_block *bus_prot_blocks; + int num_bus_prot_blocks; }; =20 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ --=20 2.50.1 From nobody Sun Oct 5 10:48:54 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B41602459FE; Tue, 5 Aug 2025 07:48:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380124; cv=none; b=g0EpEOgN7RoMVyHWA2qt0KvT0sQkzjnmJqf+r48bDKARIHeXy/R2FRGA4h/3oEg9u4IsrHerrJycaL65guAwRfmq28SXp/ENc1baGB/f1jGy53aZhNNt6GDC1KXZT0mV1j6tFemYCqOY18mdlGWnGKI5+PcABGVIDap8gAEVWLg= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Some SoCs, and even some subsystems in the same SoC, may have the logic for SRAM power-down inverted, as in, setting the bit means "power down" and unsetting means "power up": this is because some hardware subsystems use this as a power-lock indication and some use this as a power down one (for example, usually, the modem ss has it inverted!). In preparation for adding support for power domains with inverted SRAM_PDN bits, add a new MTK_SCPD_SRAM_PDN_INVERTED flag and check for it in scpsys_sram_enable() and scpsys_sram_disable(). Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 27 ++++++++++++++++------ drivers/pmdomain/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index 48dc5f188438..6118a389244a 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -79,16 +79,23 @@ static bool scpsys_domain_is_on(struct scpsys_domain *p= d) =20 static int scpsys_sram_enable(struct scpsys_domain *pd) { - u32 pdn_ack =3D pd->data->sram_pdn_ack_bits; + u32 expected_ack, pdn_ack =3D pd->data->sram_pdn_ack_bits; struct scpsys *scpsys =3D pd->scpsys; unsigned int tmp; int ret; =20 - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bi= ts); + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_PDN_INVERTED)) { + regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bit= s); + expected_ack =3D pdn_ack; + } else { + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_b= its); + expected_ack =3D 0; + } =20 /* Either wait until SRAM_PDN_ACK all 1 or 0 */ ret =3D regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) =3D=3D 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + (tmp & pdn_ack) =3D=3D expected_ack, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret < 0) return ret; =20 @@ -103,7 +110,7 @@ static int scpsys_sram_enable(struct scpsys_domain *pd) =20 static int scpsys_sram_disable(struct scpsys_domain *pd) { - u32 pdn_ack =3D pd->data->sram_pdn_ack_bits; + u32 expected_ack, pdn_ack =3D pd->data->sram_pdn_ack_bits; struct scpsys *scpsys =3D pd->scpsys; unsigned int tmp; =20 @@ -113,12 +120,18 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BI= T); } =20 - regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits= ); + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_PDN_INVERTED)) { + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_b= its); + expected_ack =3D 0; + } else { + regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bit= s); + expected_ack =3D pdn_ack; + } =20 /* Either wait until SRAM_PDN_ACK all 1 or 0 */ return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) =3D=3D pdn_ack, MTK_POLL_DELAY_US, - MTK_POLL_TIMEOUT); + (tmp & pdn_ack) =3D=3D expected_ack, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *= pd, diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/= mediatek/mtk-pm-domains.h index 4f2d331a866a..fbbfb23a8739 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -13,6 +13,7 @@ #define MTK_SCPD_EXT_BUCK_ISO BIT(6) #define MTK_SCPD_HAS_INFRA_NAO BIT(7) #define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) +#define MTK_SCPD_SRAM_PDN_INVERTED BIT(9) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 --=20 2.50.1 From nobody Sun Oct 5 10:48:54 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB07525229C; 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Tue, 5 Aug 2025 09:48:41 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 06/10] pmdomain: mediatek: Move ctl sequences out of power_on/off functions Date: Tue, 5 Aug 2025 09:47:42 +0200 Message-ID: <20250805074746.29457-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In preparation to support power domains of new SoCs and the modem power domains for both new and already supported chips, move the generic control power sequences out of the scpsys_power_on() and scpsys_power_off() and put them in new scpsys_ctl_pwrseq_on(), scpsys_ctl_pewseq_off() functions. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 57 ++++++++++++++-------- 1 file changed, 38 insertions(+), 19 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index 6118a389244a..d84f0e7cde12 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -244,11 +244,45 @@ static int scpsys_regulator_disable(struct regulator = *supply) return supply ? regulator_disable(supply) : 0; } =20 +static int scpsys_ctl_pwrseq_on(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + bool tmp; + int ret; + + /* subsys power on */ + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + + /* wait until PWR_ACK =3D 1 */ + ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DE= LAY_US, + MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + + return 0; +} + +static void scpsys_ctl_pwrseq_off(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + + /* subsys power off */ + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); +} + static int scpsys_power_on(struct generic_pm_domain *genpd) { struct scpsys_domain *pd =3D container_of(genpd, struct scpsys_domain, ge= npd); struct scpsys *scpsys =3D pd->scpsys; - bool tmp; int ret; =20 ret =3D scpsys_regulator_enable(pd->supply); @@ -263,20 +297,10 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs, pd->data->ext_buck_iso_mask); =20 - /* subsys power on */ - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); - - /* wait until PWR_ACK =3D 1 */ - ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DE= LAY_US, - MTK_POLL_TIMEOUT); - if (ret < 0) + ret =3D scpsys_ctl_pwrseq_on(pd); + if (ret) goto err_pwr_ack; =20 - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - /* * In few Mediatek platforms(e.g. MT6779), the bus protect policy is * stricter, which leads to bus protect release must be prior to bus @@ -342,12 +366,7 @@ static int scpsys_power_off(struct generic_pm_domain *= genpd) =20 clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); =20 - /* subsys power off */ - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for the modem power domains by adding its specific power sequence in functions scpsys_modem_pwrseq_{on,off}() and call them if the flag MTK_SCPD_MODEM_PWRSEQ is present. While at it, since some SoC models need to skip setting/clearing the PWR_RST_B_BIT, also add a MTK_SCPD_SKIP_RESET_B flag for that. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 41 ++++++++++++++++++++-- drivers/pmdomain/mediatek/mtk-pm-domains.h | 2 ++ 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index d84f0e7cde12..cf749ba5c3c7 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -279,6 +279,36 @@ static void scpsys_ctl_pwrseq_off(struct scpsys_domain= *pd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); } =20 +static int scpsys_modem_pwrseq_on(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + bool tmp; + int ret; + + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_SKIP_RESET_B)) + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + + /* wait until PWR_ACK =3D 1 */ + ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DE= LAY_US, + MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + return 0; +} + +static void scpsys_modem_pwrseq_off(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_SKIP_RESET_B)) + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); +} + static int scpsys_power_on(struct generic_pm_domain *genpd) { struct scpsys_domain *pd =3D container_of(genpd, struct scpsys_domain, ge= npd); @@ -297,7 +327,11 @@ static int scpsys_power_on(struct generic_pm_domain *g= enpd) regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs, pd->data->ext_buck_iso_mask); =20 - ret =3D scpsys_ctl_pwrseq_on(pd); + if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ)) + ret =3D scpsys_modem_pwrseq_on(pd); + else + ret =3D scpsys_ctl_pwrseq_on(pd); + if (ret) goto err_pwr_ack; =20 @@ -366,7 +400,10 @@ static int scpsys_power_off(struct generic_pm_domain *= genpd) =20 clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); 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Tue, 5 Aug 2025 09:48:43 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 08/10] pmdomain: mediatek: Add support for RTFF Hardware in MT8196/MT6991 Date: Tue, 5 Aug 2025 09:47:44 +0200 Message-ID: <20250805074746.29457-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable New generation SoCs use a new RTFF Hardware to save power during operation of various IPs, other than managing isolation of the internal buck converters during powerup/down of power domains. Since some of the power domains need different RTFF handling, add a new scpys_rtff_type enumeration and hold the value for each power domain in struct scpsys_domain_data. If RTFF HW is available, the RTFF additional power sequences are handled in scpsys_ctl_pwrseq_{on,off}(). Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 94 +++++++++++++++++++++- drivers/pmdomain/mediatek/mtk-pm-domains.h | 18 +++++ 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index cf749ba5c3c7..0ebe7379b94e 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -39,6 +39,12 @@ #define PWR_SRAM_CLKISO_BIT BIT(5) #define PWR_SRAM_ISOINT_B_BIT BIT(6) =20 +#define PWR_RTFF_SAVE BIT(24) +#define PWR_RTFF_NRESTORE BIT(25) +#define PWR_RTFF_CLK_DIS BIT(26) +#define PWR_RTFF_SAVE_FLAG BIT(27) +#define PWR_RTFF_UFS_CLK_DIS BIT(28) + struct scpsys_domain { struct generic_pm_domain genpd; const struct scpsys_domain_data *data; @@ -247,7 +253,7 @@ static int scpsys_regulator_disable(struct regulator *s= upply) static int scpsys_ctl_pwrseq_on(struct scpsys_domain *pd) { struct scpsys *scpsys =3D pd->scpsys; - bool tmp; + bool do_rtff_nrestore, tmp; int ret; =20 /* subsys power on */ @@ -260,10 +266,72 @@ static int scpsys_ctl_pwrseq_on(struct scpsys_domain = *pd) if (ret < 0) return ret; =20 + if (pd->data->rtff_type =3D=3D SCPSYS_RTFF_TYPE_PCIE_PHY) + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + + /* Wait for RTFF HW to sync buck isolation state if this is PCIe PHY RTFF= */ + if (pd->data->rtff_type =3D=3D SCPSYS_RTFF_TYPE_PCIE_PHY) + udelay(5); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); =20 + /* + * RTFF HW state may be modified by secure world or remote processors. + * + * With the only exception of STOR_UFS, which always needs save/restore, + * check if this power domain's RTFF is already on before trying to do + * the NRESTORE procedure, otherwise the system will lock up. + */ + switch (pd->data->rtff_type) { + case SCPSYS_RTFF_TYPE_GENERIC: + case SCPSYS_RTFF_TYPE_PCIE_PHY: + { + u32 ctl_status; + + regmap_read(scpsys->base, pd->data->ctl_offs, &ctl_status); + do_rtff_nrestore =3D ctl_status & PWR_RTFF_SAVE_FLAG; + break; + } + case SCPSYS_RTFF_TYPE_STOR_UFS: + /* STOR_UFS always needs NRESTORE */ + do_rtff_nrestore =3D true; + break; + default: + do_rtff_nrestore =3D false; + break; + } + + /* Return early if RTFF NRESTORE shall not be done */ + if (!do_rtff_nrestore) + return 0; + + switch (pd->data->rtff_type) { + case SCPSYS_RTFF_TYPE_GENERIC: + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE_FLAG); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS); + break; + case SCPSYS_RTFF_TYPE_PCIE_PHY: + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE_FLAG); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS); + break; + case SCPSYS_RTFF_TYPE_STOR_UFS: + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_UFS_CLK_DIS); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_NRESTORE); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_UFS_CLK_DIS= ); + break; + default: + break; + } + return 0; } =20 @@ -271,8 +339,32 @@ static void scpsys_ctl_pwrseq_off(struct scpsys_domain= *pd) { struct scpsys *scpsys =3D pd->scpsys; =20 + switch (pd->data->rtff_type) { + case SCPSYS_RTFF_TYPE_GENERIC: + case SCPSYS_RTFF_TYPE_PCIE_PHY: + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE_FLAG); + break; + case SCPSYS_RTFF_TYPE_STOR_UFS: + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_UFS_CLK_DIS); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_SAVE); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_UFS_CLK_DIS= ); + break; + default: + break; + } + /* subsys power off */ regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + + /* Wait for RTFF HW to sync buck isolation state if this is PCIe PHY RTFF= */ + if (pd->data->rtff_type =3D=3D SCPSYS_RTFF_TYPE_PCIE_PHY) + udelay(1); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/= mediatek/mtk-pm-domains.h index 931a54f1c5ca..b2e3dee03831 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -108,6 +108,22 @@ struct scpsys_bus_prot_data { u8 flags; }; =20 +/** + * enum scpsys_rtff_type - Type of RTFF Hardware for power domain + * @SCPSYS_RTFF_NONE: RTFF HW not present or domain not RTFF mana= ged + * @SCPSYS_RTFF_TYPE_GENERIC: Non-CPU, peripheral-generic RTFF HW + * @SCPSYS_RTFF_TYPE_PCIE_PHY: PCI-Express PHY specific RTFF HW + * @SCPSYS_RTFF_TYPE_STOR_UFS: Storage (UFS) specific RTFF HW + * @SCPSYS_RTFF_TYPE_MAX: Number of supported RTFF HW Types + */ +enum scpsys_rtff_type { + SCPSYS_RTFF_NONE =3D 0, + SCPSYS_RTFF_TYPE_GENERIC, + SCPSYS_RTFF_TYPE_PCIE_PHY, + SCPSYS_RTFF_TYPE_STOR_UFS, + SCPSYS_RTFF_TYPE_MAX +}; + /** * struct scpsys_domain_data - scp domain data for power on/off flow * @name: The name of the power domain. @@ -118,6 +134,7 @@ struct scpsys_bus_prot_data { * @ext_buck_iso_offs: The offset for external buck isolation * @ext_buck_iso_mask: The mask for external buck isolation * @caps: The flag for active wake-up action. + * @rtff_type: The power domain RTFF HW type * @bp_cfg: bus protection configuration for any subsystem */ struct scpsys_domain_data { @@ -129,6 +146,7 @@ struct scpsys_domain_data { int ext_buck_iso_offs; u32 ext_buck_iso_mask; u16 caps; + enum scpsys_rtff_type rtff_type; const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; int pwr_sta_offs; int pwr_sta2nd_offs; --=20 2.50.1 From nobody Sun Oct 5 10:48:54 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B08632594AA; Tue, 5 Aug 2025 07:48:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380128; cv=none; b=Erdsq5O0D0pdWg4Tf07Vbxx7tcLzOG4IiC/Uz+5R9d+bcXfLo5hFbaZmPVBzbRHCpe1856VqtHMrV6YSSKjQX7ycfLxFS949Kwz49MdOT4+WIghovTvz6AQ0cYmh0HFv+Z6O9nqLv6OMObc1fqooKgi2vaw02j4egkUbWpf0MEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754380128; c=relaxed/simple; bh=cvoBP4O9/ZJfi9ma34IbO7MMSJEg5uF0GVg1HKc7csA=; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dv36Bq5o1DyB+jJUcEbnZkGF1qVYLcUbqqwPX8Vpg1zs9keL4nXfsk1n/zOdOOh0d 06zZNKt3KASmeWXNth7rZDztKkvUJcD9vX85Grd9f6kHHWqcYVlpjCnOX7AjCdk2OH cX9HJvTMeDrpnX/8pqT1ZzbqO7fOWtyGRSM+K16R5gcOcnsIGI7SxJZNC7Bzv9VJb9 WIEdijTX/G0Ph0ztbC6uR5/C+4uQ8zTPbzNyP390wPHA2EwX1q3ig/k57x0PL5Zkg3 rFR9nIC4qtfjq4KVXsMwuiRVszkreD8PP1/Krm3n8ln+IIR/qkSa6Xj4npoXwEAm+T qLusp4qqWbMvw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 49B6E17E0DB9; Tue, 5 Aug 2025 09:48:44 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 09/10] pmdomain: mediatek: Convert all SoCs to new style regmap retrieval Date: Tue, 5 Aug 2025 09:47:45 +0200 Message-ID: <20250805074746.29457-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add the bus_prot_blocks handle and declare num_bus_prot_blocks to allow all of the currently supported AArch64 MediaTek SoCs to use the new style regmap retrieval in the driver when a new style devicetree declaring the mediatek,bus-protection phandle(s) in the main power controller node is found. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mt6795-pm-domains.h | 5 +++++ drivers/pmdomain/mediatek/mt8167-pm-domains.h | 5 +++++ drivers/pmdomain/mediatek/mt8173-pm-domains.h | 5 +++++ drivers/pmdomain/mediatek/mt8183-pm-domains.h | 5 +++++ drivers/pmdomain/mediatek/mt8186-pm-domains.h | 5 +++++ drivers/pmdomain/mediatek/mt8188-pm-domains.h | 6 ++++++ drivers/pmdomain/mediatek/mt8192-pm-domains.h | 5 +++++ drivers/pmdomain/mediatek/mt8195-pm-domains.h | 5 +++++ drivers/pmdomain/mediatek/mt8365-pm-domains.h | 6 ++++++ 9 files changed, 47 insertions(+) diff --git a/drivers/pmdomain/mediatek/mt6795-pm-domains.h b/drivers/pmdoma= in/mediatek/mt6795-pm-domains.h index a3f7785b04bd..dc8e9f8877ad 100644 --- a/drivers/pmdomain/mediatek/mt6795-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt6795-pm-domains.h @@ -9,6 +9,9 @@ /* * MT6795 power domain support */ +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt6795[] =3D { + BUS_PROT_BLOCK_INFRA +}; =20 static const struct scpsys_domain_data scpsys_domain_data_mt6795[] =3D { [MT6795_POWER_DOMAIN_VDEC] =3D { @@ -107,6 +110,8 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt6795[] =3D { static const struct scpsys_soc_data mt6795_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt6795, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt6795), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt6795, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt6795), }; =20 #endif /* __SOC_MEDIATEK_MT6795_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8167-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8167-pm-domains.h index 8a0e898b79ab..f6ee48a711a1 100644 --- a/drivers/pmdomain/mediatek/mt8167-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8167-pm-domains.h @@ -12,6 +12,9 @@ /* * MT8167 power domain support */ +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8167[] =3D { + BUS_PROT_BLOCK_INFRA +}; =20 static const struct scpsys_domain_data scpsys_domain_data_mt8167[] =3D { [MT8167_POWER_DOMAIN_MM] =3D { @@ -99,6 +102,8 @@ static const struct scpsys_domain_data scpsys_domain_dat= a_mt8167[] =3D { static const struct scpsys_soc_data mt8167_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt8167, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8167), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt8167, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt8167), }; =20 #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8173-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8173-pm-domains.h index 7be0f47f5214..561a644b5d1c 100644 --- a/drivers/pmdomain/mediatek/mt8173-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8173-pm-domains.h @@ -9,6 +9,9 @@ /* * MT8173 power domain support */ +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8173[] =3D { + BUS_PROT_BLOCK_INFRA +}; =20 static const struct scpsys_domain_data scpsys_domain_data_mt8173[] =3D { [MT8173_POWER_DOMAIN_VDEC] =3D { @@ -118,6 +121,8 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8173[] =3D { static const struct scpsys_soc_data mt8173_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt8173, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8173), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt8173, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt8173), }; =20 #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8183-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8183-pm-domains.h index c4c1b63d85b1..3742782a2702 100644 --- a/drivers/pmdomain/mediatek/mt8183-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8183-pm-domains.h @@ -9,6 +9,9 @@ /* * MT8183 power domain support */ +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8183[] =3D { + BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI +}; =20 static const struct scpsys_domain_data scpsys_domain_data_mt8183[] =3D { [MT8183_POWER_DOMAIN_AUDIO] =3D { @@ -290,6 +293,8 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8183[] =3D { static const struct scpsys_soc_data mt8183_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt8183, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8183), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt8183, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt8183), }; =20 #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8186-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8186-pm-domains.h index cbac715c38fa..00b9861af7c9 100644 --- a/drivers/pmdomain/mediatek/mt8186-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8186-pm-domains.h @@ -13,6 +13,9 @@ /* * MT8186 power domain support */ +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8186[] =3D { + BUS_PROT_BLOCK_INFRA +}; =20 static const struct scpsys_domain_data scpsys_domain_data_mt8186[] =3D { [MT8186_POWER_DOMAIN_MFG0] =3D { @@ -361,6 +364,8 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8186[] =3D { static const struct scpsys_soc_data mt8186_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt8186, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8186), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt8186, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt8186), }; =20 #endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8188-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8188-pm-domains.h index 007235be9efe..3a989e83e9b7 100644 --- a/drivers/pmdomain/mediatek/mt8188-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8188-pm-domains.h @@ -14,6 +14,10 @@ * MT8188 power domain support */ =20 +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8188[] =3D { + BUS_PROT_BLOCK_INFRA +}; + static const struct scpsys_domain_data scpsys_domain_data_mt8188[] =3D { [MT8188_POWER_DOMAIN_MFG0] =3D { .name =3D "mfg0", @@ -685,6 +689,8 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { static const struct scpsys_soc_data mt8188_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt8188, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8188), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt8188, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt8188), }; =20 #endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8192-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8192-pm-domains.h index 6f139eed3769..5d62fac5f682 100644 --- a/drivers/pmdomain/mediatek/mt8192-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8192-pm-domains.h @@ -9,6 +9,9 @@ /* * MT8192 power domain support */ +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8192[] =3D { + BUS_PROT_BLOCK_INFRA +}; =20 static const struct scpsys_domain_data scpsys_domain_data_mt8192[] =3D { [MT8192_POWER_DOMAIN_AUDIO] =3D { @@ -380,6 +383,8 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8192[] =3D { static const struct scpsys_soc_data mt8192_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt8192, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8192), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt8192, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt8192), }; =20 #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8195-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8195-pm-domains.h index 59aa031ae632..9405e8f62eaf 100644 --- a/drivers/pmdomain/mediatek/mt8195-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8195-pm-domains.h @@ -13,6 +13,9 @@ /* * MT8195 power domain support */ +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8195[] =3D { + BUS_PROT_BLOCK_INFRA +}; =20 static const struct scpsys_domain_data scpsys_domain_data_mt8195[] =3D { [MT8195_POWER_DOMAIN_PCIE_MAC_P0] =3D { @@ -661,6 +664,8 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { static const struct scpsys_soc_data mt8195_scpsys_data =3D { .domains_data =3D scpsys_domain_data_mt8195, .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8195), + .bus_prot_blocks =3D scpsys_bus_prot_blocks_mt8195, + .num_bus_prot_blocks =3D ARRAY_SIZE(scpsys_bus_prot_blocks_mt8195), }; =20 #endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mt8365-pm-domains.h b/drivers/pmdoma= in/mediatek/mt8365-pm-domains.h index 6fbd5ef8d672..33265ab8ce76 100644 --- a/drivers/pmdomain/mediatek/mt8365-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8365-pm-domains.h @@ -33,6 +33,10 @@ _sta_mask, _sta, \ BUS_PROT_INVERTED | BUS_PROT_REG_UPDATE) =20 +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8365[] =3D { + BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_INFRA_NAO, BUS_PROT_BLOCK_SMI +}; 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Tue, 5 Aug 2025 09:48:45 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v3 10/10] arm64: dts: mediatek: Convert all SoCs to use access-controllers Date: Tue, 5 Aug 2025 09:47:46 +0200 Message-ID: <20250805074746.29457-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> References: <20250805074746.29457-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The power controller now accepts a global access-controllers property instead of iterating through all of the power domains to check for each custom property. Where possible, cleanup all of the power controllers nodes in all of the currently supported SoCs to remove `mediatek,infracfg`, `mediatek,infracfg-nao` and `mediatek,smi` properties from the single power domains and add the phandles to some or all of those in the access-controllers property at the root of the power controller node. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 5 +++-- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 6 ++---- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 17 +++-------------- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 12 ++---------- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 23 ++--------------------- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 ++----------- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 20 ++------------------ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 16 ++++------------ 9 files changed, 22 insertions(+), 94 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts= /mediatek/mt6795.dtsi index e5e269a660b1..51f6209420be 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -275,6 +275,7 @@ topckgen: syscon@10000000 { infracfg: syscon@10001000 { compatible =3D "mediatek,mt6795-infracfg", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; @@ -295,8 +296,10 @@ scpsys: syscon@10006000 { spm: power-controller { compatible =3D "mediatek,mt6795-power-controller"; #address-cells =3D <1>; + #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg>; =20 /* power domains of the SoC */ power-domain@MT6795_POWER_DOMAIN_VDEC { @@ -324,7 +327,6 @@ power-domain@MT6795_POWER_DOMAIN_MM { clocks =3D <&topckgen CLK_TOP_MM_SEL>; clock-names =3D "mm"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; =20 power-domain@MT6795_POWER_DOMAIN_MJC { @@ -357,7 +359,6 @@ power-domain@MT6795_POWER_DOMAIN_MFG_2D { power-domain@MT6795_POWER_DOMAIN_MFG { reg =3D ; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts= /mediatek/mt8167.dtsi index 2374c0953057..3fb114c10e73 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -26,6 +26,7 @@ topckgen: topckgen@10000000 { infracfg: infracfg@10001000 { compatible =3D "mediatek,mt8167-infracfg", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; }; =20 @@ -44,6 +45,7 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg>; =20 /* power domains of the SoC */ power-domain@MT8167_POWER_DOMAIN_MM { @@ -51,7 +53,6 @@ power-domain@MT8167_POWER_DOMAIN_MM { clocks =3D <&topckgen CLK_TOP_SMI_MM>; clock-names =3D "mm"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; =20 power-domain@MT8167_POWER_DOMAIN_VDEC { @@ -77,7 +78,6 @@ power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; - mediatek,infracfg =3D <&infracfg>; =20 power-domain@MT8167_POWER_DOMAIN_MFG_2D { reg =3D ; @@ -88,7 +88,6 @@ power-domain@MT8167_POWER_DOMAIN_MFG_2D { power-domain@MT8167_POWER_DOMAIN_MFG { reg =3D ; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; }; }; @@ -96,7 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_MFG { power-domain@MT8167_POWER_DOMAIN_CONN { reg =3D ; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index 122a57c3780b..d44977a01981 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -363,6 +363,7 @@ topckgen: clock-controller@10000000 { infracfg: clock-controller@10001000 { compatible =3D "mediatek,mt8173-infracfg", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; @@ -460,6 +461,7 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg>; =20 /* power domains of the SoC */ power-domain@MT8173_POWER_DOMAIN_VDEC { @@ -486,7 +488,6 @@ power-domain@MT8173_POWER_DOMAIN_MM { clocks =3D <&topckgen CLK_TOP_MM_SEL>; clock-names =3D "mm"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; power-domain@MT8173_POWER_DOMAIN_VENC_LT { reg =3D ; @@ -520,7 +521,6 @@ power-domain@MT8173_POWER_DOMAIN_MFG_2D { power-domain@MT8173_POWER_DOMAIN_MFG { reg =3D ; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 3c1fe80e64b9..47b8425ba326 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -809,6 +809,7 @@ topckgen: syscon@10000000 { infracfg: syscon@10001000 { compatible =3D "mediatek,mt8183-infracfg", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; @@ -853,6 +854,7 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg>, <&smi_common>; =20 /* power domain of the SoC */ power-domain@MT8183_POWER_DOMAIN_AUDIO { @@ -866,7 +868,6 @@ power-domain@MT8183_POWER_DOMAIN_AUDIO { =20 power-domain@MT8183_POWER_DOMAIN_CONN { reg =3D ; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -894,7 +895,6 @@ power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { =20 power-domain@MT8183_POWER_DOMAIN_MFG_2D { reg =3D ; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; }; @@ -916,8 +916,6 @@ power-domain@MT8183_POWER_DOMAIN_DISP { clock-names =3D "mm", "mm-0", "mm-1", "mm-2", "mm-3", "mm-4", "mm-5", "mm-6", "mm-7", "mm-8", "mm-9"; - mediatek,infracfg =3D <&infracfg>; - mediatek,smi =3D <&smi_common>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -935,8 +933,6 @@ power-domain@MT8183_POWER_DOMAIN_CAM { clock-names =3D "cam", "cam-0", "cam-1", "cam-2", "cam-3", "cam-4", "cam-5", "cam-6"; - mediatek,infracfg =3D <&infracfg>; - mediatek,smi =3D <&smi_common>; #power-domain-cells =3D <0>; }; =20 @@ -946,20 +942,16 @@ power-domain@MT8183_POWER_DOMAIN_ISP { <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB2>; clock-names =3D "isp", "isp-0", "isp-1"; - mediatek,infracfg =3D <&infracfg>; - mediatek,smi =3D <&smi_common>; #power-domain-cells =3D <0>; }; =20 power-domain@MT8183_POWER_DOMAIN_VDEC { reg =3D ; - mediatek,smi =3D <&smi_common>; #power-domain-cells =3D <0>; }; =20 power-domain@MT8183_POWER_DOMAIN_VENC { reg =3D ; - mediatek,smi =3D <&smi_common>; #power-domain-cells =3D <0>; }; =20 @@ -975,8 +967,6 @@ power-domain@MT8183_POWER_DOMAIN_VPU_TOP { <&ipu_conn CLK_IPU_CONN_IMG_ADL>; clock-names =3D "vpu", "vpu1", "vpu-0", "vpu-1", "vpu-2", "vpu-3", "vpu-4", "vpu-5"; - mediatek,infracfg =3D <&infracfg>; - mediatek,smi =3D <&smi_common>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -985,7 +975,6 @@ power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { reg =3D ; clocks =3D <&topckgen CLK_TOP_MUX_DSP1>; clock-names =3D "vpu2"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -993,7 +982,6 @@ power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { reg =3D ; clocks =3D <&topckgen CLK_TOP_MUX_DSP2>; clock-names =3D "vpu3"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; }; @@ -1887,6 +1875,7 @@ smi_common: smi@14019000 { <&mmsys CLK_MM_GALS_COMM1>; clock-names =3D "apb", "smi", "gals0", "gals1"; power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + #access-controller-cells =3D <0>; }; =20 mdp3-ccorr@1401c000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index b91f88ffae0e..3fa85185e2c8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -861,6 +861,7 @@ topckgen: syscon@10000000 { infracfg_ao: syscon@10001000 { compatible =3D "mediatek,mt8186-infracfg_ao", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; @@ -900,6 +901,7 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg_ao>; =20 /* power domain of the SoC */ mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { @@ -912,7 +914,6 @@ mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { =20 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -972,7 +973,6 @@ power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { =20 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -980,7 +980,6 @@ power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { =20 power-domain@MT8186_POWER_DOMAIN_CONN_ON { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -997,7 +996,6 @@ power-domain@MT8186_POWER_DOMAIN_DIS { "subsys-smi-common", "subsys-smi-gals", "subsys-smi-iommu"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1007,7 +1005,6 @@ power-domain@MT8186_POWER_DOMAIN_VDEC { clocks =3D <&topckgen CLK_TOP_VDEC>, <&vdecsys CLK_VDEC_LARB1_CKEN>; clock-names =3D "vdec0", "larb"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -1024,7 +1021,6 @@ power-domain@MT8186_POWER_DOMAIN_CAM { "cam3", "gals", "subsys-cam-tm", "subsys-cam-top"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1045,7 +1041,6 @@ power-domain@MT8186_POWER_DOMAIN_IMG { clocks =3D <&imgsys1 CLK_IMG1_GALS_IMG1>, <&topckgen CLK_TOP_IMG1>; clock-names =3D "gals", "subsys-img-top"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1068,7 +1063,6 @@ power-domain@MT8186_POWER_DOMAIN_IPE { "subsys-ipe-larb1", "subsys-ipe-smi", "subsys-ipe-gals"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -1077,7 +1071,6 @@ power-domain@MT8186_POWER_DOMAIN_VENC { clocks =3D <&topckgen CLK_TOP_VENC>, <&vencsys CLK_VENC_CKE1_VENC>; clock-names =3D "venc0", "subsys-larb"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -1089,7 +1082,6 @@ power-domain@MT8186_POWER_DOMAIN_WPE { clock-names =3D "wpe0", "subsys-larb-ck", "subsys-larb-pclk"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 202478407727..13d6fda96e84 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -964,6 +964,7 @@ topckgen: syscon@10000000 { infracfg_ao: syscon@10001000 { compatible =3D "mediatek,mt8188-infracfg-ao", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; @@ -1002,6 +1003,7 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg_ao>; =20 /* power domain of the SoC */ mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { @@ -1015,7 +1017,6 @@ mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { clocks =3D <&apmixedsys CLK_APMIXED_MFGPLL>, <&topckgen CLK_TOP_MFG_CORE_TMP>; clock-names =3D "mfg", "alt"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1076,7 +1077,6 @@ power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { "ss-emi", "ss-subcmn-rdr", "ss-rsi", "ss-cmn-l4", "ss-vdec1", "ss-wpe", "ss-cvdo-ve1"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1095,7 +1095,6 @@ power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { clock-names =3D "cfgck", "cfgxo", "ss-gals", "ss-cmn", "ss-emi", "ss-iommu", "ss-larb", "ss-rsi", "ss-bus"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1111,7 +1110,6 @@ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { clock-names =3D "cfgck", "cfgxo", "ss-vpp1-g5", "ss-vpp1-g6", "ss-vpp1-l5", "ss-vpp1-l6"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -1119,7 +1117,6 @@ power-domain@MT8188_POWER_DOMAIN_VDEC0 { reg =3D ; clocks =3D <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; clock-names =3D "ss-vdec1-soc-l1"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1128,7 +1125,6 @@ power-domain@MT8188_POWER_DOMAIN_VDEC1 { reg =3D ; clocks =3D <&vdecsys CLK_VDEC2_LARB1>; clock-names =3D "ss-vdec2-l1"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -1140,7 +1136,6 @@ cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE= { <&topckgen CLK_TOP_CCU_AHB>, <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; clock-names =3D "cam", "ccu", "bus", "cfgck"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1155,7 +1150,6 @@ power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { clock-names=3D "ss-cam-l13", "ss-cam-l14", "ss-cam-mm0", "ss-cam-mm1", "ss-camsys"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1193,7 +1187,6 @@ power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { <&vdosys1 CLK_VDO1_GALS>; clock-names =3D "cfgck", "cfgxo", "ss-larb2", "ss-larb3", "ss-gals"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1203,19 +1196,16 @@ power-domain@MT8188_POWER_DOMAIN_HDMI_TX { clocks =3D <&topckgen CLK_TOP_HDMI_APB>, <&topckgen CLK_TOP_HDCP_24M>; clock-names =3D "bus", "hdcp"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 power-domain@MT8188_POWER_DOMAIN_DP_TX { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 power-domain@MT8188_POWER_DOMAIN_EDP_TX { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -1228,7 +1218,6 @@ power-domain@MT8188_POWER_DOMAIN_VENC { <&vencsys CLK_VENC1_GALS_SRAM>; clock-names =3D "ss-ve1-larb", "ss-ve1-core", "ss-ve1-gals", "ss-ve1-sram"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -1237,7 +1226,6 @@ power-domain@MT8188_POWER_DOMAIN_WPE { clocks =3D <&wpesys CLK_WPE_TOP_SMI_LARB7>, <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; clock-names =3D "ss-wpe-l7", "ss-wpe-l7pce"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -1245,7 +1233,6 @@ power-domain@MT8188_POWER_DOMAIN_WPE { =20 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; clocks =3D <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; clock-names =3D "ss-pextp-fmem"; #power-domain-cells =3D <0>; @@ -1269,14 +1256,12 @@ power-domain@MT8188_POWER_DOMAIN_ADSP_AO { clocks =3D <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, <&topckgen CLK_TOP_ADSP>; clock-names =3D "bus", "main"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; =20 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -1285,7 +1270,6 @@ power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { reg =3D ; clocks =3D <&topckgen CLK_TOP_ASM_H>; clock-names =3D "asm"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -1295,13 +1279,11 @@ power-domain@MT8188_POWER_DOMAIN_AUDIO { <&topckgen CLK_TOP_AUD_INTBUS>, <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; clock-names =3D "a1sys", "intbus", "adspck"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 power-domain@MT8188_POWER_DOMAIN_ADSP { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -1311,7 +1293,6 @@ power-domain@MT8188_POWER_DOMAIN_ETHER { reg =3D ; clocks =3D <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; clock-names =3D "ethermac"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 47dea10dd3b8..56e4dd00e004 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -459,6 +459,7 @@ topckgen: syscon@10000000 { infracfg: syscon@10001000 { compatible =3D "mediatek,mt8192-infracfg", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; @@ -504,6 +505,7 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg>; =20 /* power domain of the SoC */ power-domain@MT8192_POWER_DOMAIN_AUDIO { @@ -512,7 +514,6 @@ power-domain@MT8192_POWER_DOMAIN_AUDIO { <&infracfg CLK_INFRA_AUDIO_26M_B>, <&infracfg CLK_INFRA_AUDIO>; clock-names =3D "audio", "audio1", "audio2"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -520,7 +521,6 @@ power-domain@MT8192_POWER_DOMAIN_CONN { reg =3D ; clocks =3D <&infracfg CLK_INFRA_PMIC_CONN>; clock-names =3D "conn"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -535,7 +535,6 @@ mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { =20 mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { reg =3D ; - mediatek,infracfg =3D <&infracfg>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -576,7 +575,6 @@ power-domain@MT8192_POWER_DOMAIN_DISP { <&mmsys CLK_MM_SMI_IOMMU>; clock-names =3D "disp", "disp-0", "disp-1", "disp-2", "disp-3"; - mediatek,infracfg =3D <&infracfg>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -590,7 +588,6 @@ power-domain@MT8192_POWER_DOMAIN_IPE { <&ipesys CLK_IPE_GALS>; clock-names =3D "ipe", "ipe-0", "ipe-1", "ipe-2", "ipe-3"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -600,7 +597,6 @@ power-domain@MT8192_POWER_DOMAIN_ISP { <&imgsys CLK_IMG_LARB9>, <&imgsys CLK_IMG_GALS>; clock-names =3D "isp", "isp-0", "isp-1"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -610,7 +606,6 @@ power-domain@MT8192_POWER_DOMAIN_ISP2 { <&imgsys2 CLK_IMG2_LARB11>, <&imgsys2 CLK_IMG2_GALS>; clock-names =3D "isp2", "isp2-0", "isp2-1"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -619,7 +614,6 @@ power-domain@MT8192_POWER_DOMAIN_MDP { clocks =3D <&topckgen CLK_TOP_MDP_SEL>, <&mdpsys CLK_MDP_SMI0>; clock-names =3D "mdp", "mdp-0"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -628,7 +622,6 @@ power-domain@MT8192_POWER_DOMAIN_VENC { clocks =3D <&topckgen CLK_TOP_VENC_SEL>, <&vencsys CLK_VENC_SET1_VENC>; clock-names =3D "venc", "venc-0"; - mediatek,infracfg =3D <&infracfg>; #power-domain-cells =3D <0>; }; =20 @@ -639,7 +632,6 @@ power-domain@MT8192_POWER_DOMAIN_VDEC { <&vdecsys_soc CLK_VDEC_SOC_LAT>, <&vdecsys_soc CLK_VDEC_SOC_LARB1>; clock-names =3D "vdec", "vdec-0", "vdec-1", "vdec-2"; - mediatek,infracfg =3D <&infracfg>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -664,7 +656,6 @@ power-domain@MT8192_POWER_DOMAIN_CAM { <&camsys CLK_CAM_CAM2MM_GALS>; clock-names =3D "cam", "cam-0", "cam-1", "cam-2", "cam-3"; - mediatek,infracfg =3D <&infracfg>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 8877953ce292..6d1aeca07331 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -489,6 +489,7 @@ topckgen: syscon@10000000 { infracfg_ao: syscon@10001000 { compatible =3D "mediatek,mt8195-infracfg_ao", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; @@ -530,6 +531,7 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg_ao>; =20 /* power domain of the SoC */ mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { @@ -543,7 +545,6 @@ mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { clocks =3D <&apmixedsys CLK_APMIXED_MFGPLL>, <&topckgen CLK_TOP_MFG_CORE_TMP>; clock-names =3D "mfg", "alt"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -612,7 +613,6 @@ power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { "vppsys0-12", "vppsys0-13", "vppsys0-14", "vppsys0-15", "vppsys0-16", "vppsys0-17", "vppsys0-18"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -629,7 +629,6 @@ power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { clock-names =3D "vdosys0", "vdosys0-0", "vdosys0-1", "vdosys0-2", "vdosys0-3", "vdosys0-4", "vdosys0-5"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -641,7 +640,6 @@ power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; clock-names =3D "vppsys1", "vppsys1-0", "vppsys1-1"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -653,7 +651,6 @@ power-domain@MT8195_POWER_DOMAIN_WPESYS { <&wpesys CLK_WPE_SMI_LARB8_P>; clock-names =3D "wepsys-0", "wepsys-1", "wepsys-2", "wepsys-3"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -661,7 +658,6 @@ power-domain@MT8195_POWER_DOMAIN_VDEC0 { reg =3D ; clocks =3D <&vdecsys_soc CLK_VDEC_SOC_LARB1>; clock-names =3D "vdec0-0"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <0>; @@ -670,7 +666,6 @@ power-domain@MT8195_POWER_DOMAIN_VDEC1 { reg =3D ; clocks =3D <&vdecsys CLK_VDEC_LARB1>; clock-names =3D "vdec1-0"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -678,7 +673,6 @@ power-domain@MT8195_POWER_DOMAIN_VDEC2 { reg =3D ; clocks =3D <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; clock-names =3D "vdec2-0"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -687,7 +681,6 @@ power-domain@MT8195_POWER_DOMAIN_VENC { reg =3D ; clocks =3D <&vencsys CLK_VENC_LARB>; clock-names =3D "venc0-larb"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <0>; @@ -696,7 +689,6 @@ power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { reg =3D ; clocks =3D <&vencsys_core1 CLK_VENC_CORE1_LARB>; clock-names =3D "venc1-larb"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -709,20 +701,17 @@ power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { <&vdosys1 CLK_VDO1_GALS>; clock-names =3D "vdosys1", "vdosys1-0", "vdosys1-1", "vdosys1-2"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; =20 power-domain@MT8195_POWER_DOMAIN_DP_TX { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 power-domain@MT8195_POWER_DOMAIN_EPD_TX { reg =3D ; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; =20 @@ -739,7 +728,6 @@ power-domain@MT8195_POWER_DOMAIN_IMG { clocks =3D <&imgsys CLK_IMG_LARB9>, <&imgsys CLK_IMG_GALS>; clock-names =3D "img-0", "img-1"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -755,7 +743,6 @@ power-domain@MT8195_POWER_DOMAIN_IPE { <&imgsys CLK_IMG_IPE>, <&ipesys CLK_IPE_SMI_LARB12>; clock-names =3D "ipe", "ipe-0", "ipe-1"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; @@ -769,7 +756,6 @@ power-domain@MT8195_POWER_DOMAIN_CAM { <&camsys CLK_CAM_CAM2SYS_GALS>; clock-names =3D "cam-0", "cam-1", "cam-2", "cam-3", "cam-4"; - mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; @@ -836,7 +822,6 @@ power-domain@MT8195_POWER_DOMAIN_ADSP { clock-names =3D "adsp", "adsp1"; #address-cells =3D <1>; #size-cells =3D <0>; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <1>; =20 power-domain@MT8195_POWER_DOMAIN_AUDIO { @@ -847,7 +832,6 @@ power-domain@MT8195_POWER_DOMAIN_AUDIO { <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; clock-names =3D "audio", "audio1", "audio2", "audio3"; - mediatek,infracfg =3D <&infracfg_ao>; #power-domain-cells =3D <0>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index e6d2b3221a3b..3ed53e906482 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -301,6 +301,7 @@ topckgen: syscon@10000000 { infracfg: syscon@10001000 { compatible =3D "mediatek,mt8365-infracfg", "syscon"; reg =3D <0 0x10001000 0 0x1000>; + #access-controller-cells =3D <0>; #clock-cells =3D <1>; }; =20 @@ -325,6 +326,8 @@ spm: power-controller { #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; + access-controllers =3D <&infracfg>, <&infracfg_nao>, + <&smi_common>; =20 /* power domains of the SoC */ power-domain@MT8365_POWER_DOMAIN_MM { @@ -337,8 +340,6 @@ power-domain@MT8365_POWER_DOMAIN_MM { clock-names =3D "mm", "mm-0", "mm-1", "mm-2", "mm-3"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; - mediatek,infracfg-nao =3D <&infracfg_nao>; #address-cells =3D <1>; #size-cells =3D <0>; =20 @@ -354,20 +355,16 @@ power-domain@MT8365_POWER_DOMAIN_CAM { "cam-2", "cam-3", "cam-4", "cam-5"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; - mediatek,smi =3D <&smi_common>; }; =20 power-domain@MT8365_POWER_DOMAIN_VDEC { reg =3D ; #power-domain-cells =3D <0>; - mediatek,smi =3D <&smi_common>; }; =20 power-domain@MT8365_POWER_DOMAIN_VENC { reg =3D ; #power-domain-cells =3D <0>; - mediatek,smi =3D <&smi_common>; }; =20 power-domain@MT8365_POWER_DOMAIN_APU { @@ -384,8 +381,6 @@ power-domain@MT8365_POWER_DOMAIN_APU { "apu-3", "apu-4", "apu-5"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; - mediatek,smi =3D <&smi_common>; }; }; =20 @@ -395,7 +390,6 @@ power-domain@MT8365_POWER_DOMAIN_CONN { <&topckgen CLK_TOP_CONN_26M>; clock-names =3D "conn", "conn1"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; =20 power-domain@MT8365_POWER_DOMAIN_MFG { @@ -403,7 +397,6 @@ power-domain@MT8365_POWER_DOMAIN_MFG { clocks =3D <&topckgen CLK_TOP_MFG_SEL>; clock-names =3D "mfg"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; =20 power-domain@MT8365_POWER_DOMAIN_AUDIO { @@ -413,7 +406,6 @@ power-domain@MT8365_POWER_DOMAIN_AUDIO { <&infracfg CLK_IFR_AUD_26M_BK>; clock-names =3D "audio", "audio1", "audio2"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; =20 power-domain@MT8365_POWER_DOMAIN_DSP { @@ -422,7 +414,6 @@ power-domain@MT8365_POWER_DOMAIN_DSP { <&topckgen CLK_TOP_DSP_26M>; clock-names =3D "dsp", "dsp1"; #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; }; }; }; @@ -795,6 +786,7 @@ smi_common: smi@14002000 { <&mmsys CLK_MM_MM_SMI_COMM1>; clock-names =3D "apb", "smi", "gals0", "gals1"; power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + #access-controller-cells =3D <0>; }; =20 larb0: larb@14003000 { --=20 2.50.1