From nobody Sun Oct 5 10:47:23 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3180C21D00A; Tue, 5 Aug 2025 06:51:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754376711; cv=none; b=AmlLBeQSFG+uoHA+xOnGSiZPAwyx4rLEfPV4BwaC+U5FgqOybDFyRwpZSgA8lLYXop0c+1hUFHOiKFyg6x4g79Me6jjWvD4XkoYM7XTiRw4SPd4Udutzhxq+1ttyYB+THmA62fqt2mPnhavIqb+mOp+9bBhiiPYGUckZ9ZHjo54= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754376711; c=relaxed/simple; bh=D3I2JaWVEMVlLKJ+PjzHt80JLOTgVVkvCJfr9Iyis38=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rFst9FCv7ysDy11GtZEqk+f0dbMtwxR3zeGvdY13sizQ+swRXhu404RvOc2xcH2Eg35+3eSkJmn41pK9neZvTL3lw8uf3GalczMd4XHV5HMTs9pCQ5Vh+agMyCjafbU5l15so51uoT34XHbFsvLNRW/hjsQo8kgzKOh0cMqLrA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4bx3qm3VHkz14MBl; Tue, 5 Aug 2025 14:46:44 +0800 (CST) Received: from dggpemf500015.china.huawei.com (unknown [7.185.36.143]) by mail.maildlp.com (Postfix) with ESMTPS id 3E8BC1402E9; Tue, 5 Aug 2025 14:51:40 +0800 (CST) Received: from huawei.com (10.90.31.46) by dggpemf500015.china.huawei.com (7.185.36.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 5 Aug 2025 14:51:39 +0800 From: Longfang Liu To: , , , , CC: , , , , Subject: [PATCH v7 1/3] migration: update BAR space size Date: Tue, 5 Aug 2025 14:51:04 +0800 Message-ID: <20250805065106.898298-2-liulongfang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250805065106.898298-1-liulongfang@huawei.com> References: <20250805065106.898298-1-liulongfang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500015.china.huawei.com (7.185.36.143) Content-Type: text/plain; charset="utf-8" On new platforms greater than QM_HW_V3, the live migration configuration region is moved from VF to PF. The VF's own configuration space is restored to the complete 64KB, and there is no need to divide the size of the BAR configuration space equally. Signed-off-by: Longfang Liu Reviewed-by: Shameer Kolothum --- .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c | 36 ++++++++++++++----- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c b/drivers/vfio/= pci/hisilicon/hisi_acc_vfio_pci.c index 397f5e445136..ddb3fd4df5aa 100644 --- a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c +++ b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c @@ -1250,6 +1250,28 @@ static struct hisi_qm *hisi_acc_get_pf_qm(struct pci= _dev *pdev) return !IS_ERR(pf_qm) ? pf_qm : NULL; } =20 +static size_t hisi_acc_get_resource_len(struct vfio_pci_core_device *vdev, + unsigned int index) +{ + struct hisi_acc_vf_core_device *hisi_acc_vdev =3D + hisi_acc_drvdata(vdev->pdev); + + /* + * On the old HW_V3 device, the ACC VF device BAR2 + * region encompasses both functional register space + * and migration control register space. + * only the functional region should be report to Guest. + */ + if (hisi_acc_vdev->pf_qm->ver =3D=3D QM_HW_V3) + return (pci_resource_len(vdev->pdev, index) >> 1); + /* + * On the new HW device, the migration control register + * has been moved to the PF device BAR2 region. + * The VF device BAR2 is entirely functional register space. + */ + return pci_resource_len(vdev->pdev, index); +} + static int hisi_acc_pci_rw_access_check(struct vfio_device *core_vdev, size_t count, loff_t *ppos, size_t *new_count) @@ -1260,8 +1282,9 @@ static int hisi_acc_pci_rw_access_check(struct vfio_d= evice *core_vdev, =20 if (index =3D=3D VFIO_PCI_BAR2_REGION_INDEX) { loff_t pos =3D *ppos & VFIO_PCI_OFFSET_MASK; - resource_size_t end =3D pci_resource_len(vdev->pdev, index) / 2; + resource_size_t end; =20 + end =3D hisi_acc_get_resource_len(vdev, index); /* Check if access is for migration control region */ if (pos >=3D end) return -EINVAL; @@ -1282,8 +1305,9 @@ static int hisi_acc_vfio_pci_mmap(struct vfio_device = *core_vdev, index =3D vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); if (index =3D=3D VFIO_PCI_BAR2_REGION_INDEX) { u64 req_len, pgoff, req_start; - resource_size_t end =3D pci_resource_len(vdev->pdev, index) / 2; + resource_size_t end; =20 + end =3D hisi_acc_get_resource_len(vdev, index); req_len =3D vma->vm_end - vma->vm_start; pgoff =3D vma->vm_pgoff & ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); @@ -1330,7 +1354,6 @@ static long hisi_acc_vfio_pci_ioctl(struct vfio_devic= e *core_vdev, unsigned int if (cmd =3D=3D VFIO_DEVICE_GET_REGION_INFO) { struct vfio_pci_core_device *vdev =3D container_of(core_vdev, struct vfio_pci_core_device, vdev); - struct pci_dev *pdev =3D vdev->pdev; struct vfio_region_info info; unsigned long minsz; =20 @@ -1345,12 +1368,7 @@ static long hisi_acc_vfio_pci_ioctl(struct vfio_devi= ce *core_vdev, unsigned int if (info.index =3D=3D VFIO_PCI_BAR2_REGION_INDEX) { info.offset =3D VFIO_PCI_INDEX_TO_OFFSET(info.index); =20 - /* - * ACC VF dev BAR2 region consists of both functional - * register space and migration control register space. - * Report only the functional region to Guest. - */ - info.size =3D pci_resource_len(pdev, info.index) / 2; + info.size =3D hisi_acc_get_resource_len(vdev, info.index); =20 info.flags =3D VFIO_REGION_INFO_FLAG_READ | VFIO_REGION_INFO_FLAG_WRITE | --=20 2.24.0 From nobody Sun Oct 5 10:47:23 2025 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2F5221571; Tue, 5 Aug 2025 06:52:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754376744; cv=none; b=SWgvJ2n2ybLt5LeLgKr/dZ5rk5GoFohlQvi75TKa3RQVlacMhxmFQxkYrxe9HHYmnWHpX13/OKNQii9T8JvVrPJYZSyL9Ub0HWqA9KNKP2XXtM6iF470yIunZmD5Q/QZc7LCZ/KdwmT+4Jh+22YMROLSFAatu3EOjbl3hdSn1vc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754376744; c=relaxed/simple; bh=5D97KnmkJhmHWowy32+sKgydeWlWSW7EIvxRuhDs5Vk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Tue, 5 Aug 2025 14:52:11 +0800 From: Longfang Liu To: , , , , CC: , , , , Subject: [PATCH v7 2/3] migration: qm updates BAR configuration Date: Tue, 5 Aug 2025 14:51:05 +0800 Message-ID: <20250805065106.898298-3-liulongfang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250805065106.898298-1-liulongfang@huawei.com> References: <20250805065106.898298-1-liulongfang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500015.china.huawei.com (7.185.36.143) Content-Type: text/plain; charset="utf-8" On new platforms greater than QM_HW_V3, the configuration region for the live migration function of the accelerator device is no longer placed in the VF, but is instead placed in the PF. Therefore, the configuration region of the live migration function needs to be opened when the QM driver is loaded. When the QM driver is uninstalled, the driver needs to clear this configuration. Signed-off-by: Longfang Liu Reviewed-by: Shameer Kolothum Acked-by: Herbert Xu --- drivers/crypto/hisilicon/qm.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 7c41f9593d03..b5ce9b1e9c56 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -242,6 +242,9 @@ #define QM_QOS_MAX_CIR_U 6 #define QM_AUTOSUSPEND_DELAY 3000 =20 +#define QM_MIG_REGION_SEL 0x100198 +#define QM_MIG_REGION_EN 0x1 + /* abnormal status value for stopping queue */ #define QM_STOP_QUEUE_FAIL 1 #define QM_DUMP_SQC_FAIL 3 @@ -3004,11 +3007,36 @@ static void qm_put_pci_res(struct hisi_qm *qm) pci_release_mem_regions(pdev); } =20 +static void hisi_mig_region_clear(struct hisi_qm *qm) +{ + u32 val; + + /* Clear migration region set of PF */ + if (qm->fun_type =3D=3D QM_HW_PF && qm->ver > QM_HW_V3) { + val =3D readl(qm->io_base + QM_MIG_REGION_SEL); + val &=3D ~BIT(0); + writel(val, qm->io_base + QM_MIG_REGION_SEL); + } +} + +static void hisi_mig_region_enable(struct hisi_qm *qm) +{ + u32 val; + + /* Select migration region of PF */ + if (qm->fun_type =3D=3D QM_HW_PF && qm->ver > QM_HW_V3) { + val =3D readl(qm->io_base + QM_MIG_REGION_SEL); + val |=3D QM_MIG_REGION_EN; + writel(val, qm->io_base + QM_MIG_REGION_SEL); + } +} + static void hisi_qm_pci_uninit(struct hisi_qm *qm) { struct pci_dev *pdev =3D qm->pdev; =20 pci_free_irq_vectors(pdev); + hisi_mig_region_clear(qm); qm_put_pci_res(qm); pci_disable_device(pdev); } @@ -5630,6 +5658,7 @@ int hisi_qm_init(struct hisi_qm *qm) goto err_free_qm_memory; =20 qm_cmd_init(qm); + hisi_mig_region_enable(qm); =20 return 0; =20 --=20 2.24.0 From nobody Sun Oct 5 10:47:23 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ECB9A927; Tue, 5 Aug 2025 06:52:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754376768; cv=none; b=Q0EnZaahH6SJwS0kewALrJbeGtXwqdgSCpBFDxg2Fg1x43B0igkz29+236HG8m6MZidTFr8CsgtqX5a4MjUJf3TQUMPQy9UenLhsqlBlcGto13PiKPz7fo/kzCHzIDO6xzxU95NlmsKYq8pBmiUsiQlCLYrtt/wlOrzYtRi2LpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754376768; c=relaxed/simple; bh=dOMNrFkdF3d/bghtMW/jDThJaP82j14On+OkxCJkibU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ChF3lOnjHUr+hBObsKT7Jvh8+/UxNDtBI5VK0oT/FtpXChye3muTNeVpw+W/bQuw37w8wxKJYNMbzz+OaB9lF7/isXeadEu8Y/bTAndduHe616pPfsMVdmZZmeJcmM6+2d0n7yjL5qVtGDaCimvCPGcp86xwg+i/eepvQk+EZVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4bx3rz72m6z14M9N; Tue, 5 Aug 2025 14:47:47 +0800 (CST) Received: from dggpemf500015.china.huawei.com (unknown [7.185.36.143]) by mail.maildlp.com (Postfix) with ESMTPS id B93031402E9; Tue, 5 Aug 2025 14:52:43 +0800 (CST) Received: from huawei.com (10.90.31.46) by dggpemf500015.china.huawei.com (7.185.36.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 5 Aug 2025 14:52:43 +0800 From: Longfang Liu To: , , , , CC: , , , , Subject: [PATCH v7 3/3] migration: adapt to new migration configuration Date: Tue, 5 Aug 2025 14:51:06 +0800 Message-ID: <20250805065106.898298-4-liulongfang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250805065106.898298-1-liulongfang@huawei.com> References: <20250805065106.898298-1-liulongfang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500015.china.huawei.com (7.185.36.143) Content-Type: text/plain; charset="utf-8" On new platforms greater than QM_HW_V3, the migration region has been relocated from the VF to the PF. The driver must also be modified accordingly to adapt to the new hardware device. On the older hardware platform QM_HW_V3, the live migration configuration region is placed in the latter 32K portion of the VF's BAR2 configuration space. On the new hardware platform QM_HW_V4, the live migration configuration region also exists in the same 32K area immediately following the VF's BAR2, just like on QM_HW_V3. However, access to this region is now controlled by hardware. Additionally, a copy of the live migration configuration region is present in the PF's BA= R2 configuration space. On the new hardware platform QM_HW_V4, when an older version of the driver is loaded, it behaves like QM_HW_V3 and uses the configuration region in the VF, ensuring that the live migration function continues to work normally. When the new version of the driver is loaded, it directly uses the configuration region in the PF. Meanwhile, hardware configuration disables the live migration configuration region in the VF's BAR2: reads return all 0xF values, and writes are silently ignored. Signed-off-by: Longfang Liu Reviewed-by: Shameer Kolothum --- .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c | 164 ++++++++++++------ .../vfio/pci/hisilicon/hisi_acc_vfio_pci.h | 7 + 2 files changed, 118 insertions(+), 53 deletions(-) diff --git a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c b/drivers/vfio/= pci/hisilicon/hisi_acc_vfio_pci.c index ddb3fd4df5aa..a20785bcea62 100644 --- a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c +++ b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c @@ -125,6 +125,72 @@ static int qm_get_cqc(struct hisi_qm *qm, u64 *addr) return 0; } =20 +static int qm_get_xqc_regs(struct hisi_acc_vf_core_device *hisi_acc_vdev, + struct acc_vf_data *vf_data) +{ + struct hisi_qm *qm =3D &hisi_acc_vdev->vf_qm; + struct device *dev =3D &qm->pdev->dev; + u32 eqc_addr, aeqc_addr; + int ret; + + if (qm->ver =3D=3D QM_HW_V3) { + eqc_addr =3D QM_EQC_DW0; + aeqc_addr =3D QM_AEQC_DW0; + } else { + eqc_addr =3D QM_EQC_PF_DW0; + aeqc_addr =3D QM_AEQC_PF_DW0; + } + + /* QM_EQC_DW has 7 regs */ + ret =3D qm_read_regs(qm, eqc_addr, vf_data->qm_eqc_dw, 7); + if (ret) { + dev_err(dev, "failed to read QM_EQC_DW\n"); + return ret; + } + + /* QM_AEQC_DW has 7 regs */ + ret =3D qm_read_regs(qm, aeqc_addr, vf_data->qm_aeqc_dw, 7); + if (ret) { + dev_err(dev, "failed to read QM_AEQC_DW\n"); + return ret; + } + + return 0; +} + +static int qm_set_xqc_regs(struct hisi_acc_vf_core_device *hisi_acc_vdev, + struct acc_vf_data *vf_data) +{ + struct hisi_qm *qm =3D &hisi_acc_vdev->vf_qm; + struct device *dev =3D &qm->pdev->dev; + u32 eqc_addr, aeqc_addr; + int ret; + + if (qm->ver =3D=3D QM_HW_V3) { + eqc_addr =3D QM_EQC_DW0; + aeqc_addr =3D QM_AEQC_DW0; + } else { + eqc_addr =3D QM_EQC_PF_DW0; + aeqc_addr =3D QM_AEQC_PF_DW0; + } + + /* QM_EQC_DW has 7 regs */ + ret =3D qm_write_regs(qm, eqc_addr, vf_data->qm_eqc_dw, 7); + if (ret) { + dev_err(dev, "failed to write QM_EQC_DW\n"); + return ret; + } + + /* QM_AEQC_DW has 7 regs */ + ret =3D qm_write_regs(qm, aeqc_addr, vf_data->qm_aeqc_dw, 7); + if (ret) { + dev_err(dev, "failed to write QM_AEQC_DW\n"); + return ret; + } + + return 0; +} + static int qm_get_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data) { struct device *dev =3D &qm->pdev->dev; @@ -167,20 +233,6 @@ static int qm_get_regs(struct hisi_qm *qm, struct acc_= vf_data *vf_data) return ret; } =20 - /* QM_EQC_DW has 7 regs */ - ret =3D qm_read_regs(qm, QM_EQC_DW0, vf_data->qm_eqc_dw, 7); - if (ret) { - dev_err(dev, "failed to read QM_EQC_DW\n"); - return ret; - } - - /* QM_AEQC_DW has 7 regs */ - ret =3D qm_read_regs(qm, QM_AEQC_DW0, vf_data->qm_aeqc_dw, 7); - if (ret) { - dev_err(dev, "failed to read QM_AEQC_DW\n"); - return ret; - } - return 0; } =20 @@ -239,20 +291,6 @@ static int qm_set_regs(struct hisi_qm *qm, struct acc_= vf_data *vf_data) return ret; } =20 - /* QM_EQC_DW has 7 regs */ - ret =3D qm_write_regs(qm, QM_EQC_DW0, vf_data->qm_eqc_dw, 7); - if (ret) { - dev_err(dev, "failed to write QM_EQC_DW\n"); - return ret; - } - - /* QM_AEQC_DW has 7 regs */ - ret =3D qm_write_regs(qm, QM_AEQC_DW0, vf_data->qm_aeqc_dw, 7); - if (ret) { - dev_err(dev, "failed to write QM_AEQC_DW\n"); - return ret; - } - return 0; } =20 @@ -522,6 +560,10 @@ static int vf_qm_load_data(struct hisi_acc_vf_core_dev= ice *hisi_acc_vdev, return ret; } =20 + ret =3D qm_set_xqc_regs(hisi_acc_vdev, vf_data); + if (ret) + return ret; + ret =3D hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); if (ret) { dev_err(dev, "set sqc failed\n"); @@ -589,6 +631,10 @@ static int vf_qm_state_save(struct hisi_acc_vf_core_de= vice *hisi_acc_vdev, vf_data->vf_qm_state =3D QM_READY; hisi_acc_vdev->vf_qm_state =3D vf_data->vf_qm_state; =20 + ret =3D qm_get_xqc_regs(hisi_acc_vdev, vf_data); + if (ret) + return ret; + ret =3D vf_qm_read_data(vf_qm, vf_data); if (ret) return ret; @@ -1186,34 +1232,45 @@ static int hisi_acc_vf_qm_init(struct hisi_acc_vf_c= ore_device *hisi_acc_vdev) { struct vfio_pci_core_device *vdev =3D &hisi_acc_vdev->core_device; struct hisi_qm *vf_qm =3D &hisi_acc_vdev->vf_qm; + struct hisi_qm *pf_qm =3D hisi_acc_vdev->pf_qm; struct pci_dev *vf_dev =3D vdev->pdev; =20 - /* - * ACC VF dev BAR2 region consists of both functional register space - * and migration control register space. For migration to work, we - * need access to both. Hence, we map the entire BAR2 region here. - * But unnecessarily exposing the migration BAR region to the Guest - * has the potential to prevent/corrupt the Guest migration. Hence, - * we restrict access to the migration control space from - * Guest(Please see mmap/ioctl/read/write override functions). - * - * Please note that it is OK to expose the entire VF BAR if migration - * is not supported or required as this cannot affect the ACC PF - * configurations. - * - * Also the HiSilicon ACC VF devices supported by this driver on - * HiSilicon hardware platforms are integrated end point devices - * and the platform lacks the capability to perform any PCIe P2P - * between these devices. - */ - - vf_qm->io_base =3D - ioremap(pci_resource_start(vf_dev, VFIO_PCI_BAR2_REGION_INDEX), - pci_resource_len(vf_dev, VFIO_PCI_BAR2_REGION_INDEX)); - if (!vf_qm->io_base) - return -EIO; + if (pf_qm->ver =3D=3D QM_HW_V3) { + /* + * ACC VF dev BAR2 region consists of both functional register space + * and migration control register space. For migration to work, we + * need access to both. Hence, we map the entire BAR2 region here. + * But unnecessarily exposing the migration BAR region to the Guest + * has the potential to prevent/corrupt the Guest migration. Hence, + * we restrict access to the migration control space from + * Guest(Please see mmap/ioctl/read/write override functions). + * + * Please note that it is OK to expose the entire VF BAR if migration + * is not supported or required as this cannot affect the ACC PF + * configurations. + * + * Also the HiSilicon ACC VF devices supported by this driver on + * HiSilicon hardware platforms are integrated end point devices + * and the platform lacks the capability to perform any PCIe P2P + * between these devices. + */ =20 + vf_qm->io_base =3D + ioremap(pci_resource_start(vf_dev, VFIO_PCI_BAR2_REGION_INDEX), + pci_resource_len(vf_dev, VFIO_PCI_BAR2_REGION_INDEX)); + if (!vf_qm->io_base) + return -EIO; + } else { + /* + * On hardware platforms greater than QM_HW_V3, the migration function + * register is placed in the BAR2 configuration region of the PF, + * and each VF device occupies 8KB of configuration space. + */ + vf_qm->io_base =3D pf_qm->io_base + QM_MIG_REGION_OFFSET + + hisi_acc_vdev->vf_id * QM_MIG_REGION_SIZE; + } vf_qm->fun_type =3D QM_HW_VF; + vf_qm->ver =3D pf_qm->ver; vf_qm->pdev =3D vf_dev; mutex_init(&vf_qm->mailbox_lock); =20 @@ -1539,7 +1596,8 @@ static void hisi_acc_vfio_pci_close_device(struct vfi= o_device *core_vdev) hisi_acc_vf_disable_fds(hisi_acc_vdev); mutex_lock(&hisi_acc_vdev->open_mutex); hisi_acc_vdev->dev_opened =3D false; - iounmap(vf_qm->io_base); + if (vf_qm->ver =3D=3D QM_HW_V3) + iounmap(vf_qm->io_base); mutex_unlock(&hisi_acc_vdev->open_mutex); vfio_pci_core_close_device(core_vdev); } diff --git a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h b/drivers/vfio/= pci/hisilicon/hisi_acc_vfio_pci.h index 91002ceeebc1..348f8bb5b42c 100644 --- a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h +++ b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h @@ -59,6 +59,13 @@ #define ACC_DEV_MAGIC_V1 0XCDCDCDCDFEEDAACC #define ACC_DEV_MAGIC_V2 0xAACCFEEDDECADEDE =20 +#define QM_MIG_REGION_OFFSET 0x180000 +#define QM_MIG_REGION_SIZE 0x2000 + +#define QM_SUB_VERSION_ID 0x100210 +#define QM_EQC_PF_DW0 0x1c00 +#define QM_AEQC_PF_DW0 0x1c20 + struct acc_vf_data { #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state) /* QM match information */ --=20 2.24.0