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Tue, 5 Aug 2025 06:28:10 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D788620040; Tue, 5 Aug 2025 06:28:09 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BE2D420043; Tue, 5 Aug 2025 06:28:02 +0000 (GMT) Received: from li-621bac4c-27c7-11b2-a85c-c2bf7c4b3c07.ibm.com.com (unknown [9.43.39.141]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 5 Aug 2025 06:28:02 +0000 (GMT) From: Saket Kumar Bhaskar To: bpf@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Cc: hbathini@linux.ibm.com, sachinpb@linux.ibm.com, venkat88@linux.ibm.com, andrii@kernel.org, eddyz87@gmail.com, mykolal@fb.com, ast@kernel.org, daniel@iogearbox.net, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, john.fastabend@gmail.com, kpsingh@kernel.org, sdf@fomichev.me, haoluo@google.com, jolsa@kernel.org, christophe.leroy@csgroup.eu, naveen@kernel.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, memxor@gmail.com, iii@linux.ibm.com, shuah@kernel.org Subject: [bpf-next 1/6] bpf,powerpc: Introduce bpf_jit_emit_probe_mem_store() to emit store instructions Date: Tue, 5 Aug 2025 11:57:42 +0530 Message-ID: <20250805062747.3479221-2-skb99@linux.ibm.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250805062747.3479221-1-skb99@linux.ibm.com> References: <20250805062747.3479221-1-skb99@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: CUuaPoBERhcFskGYnC0ub0cAgoTHhzdP X-Authority-Analysis: v=2.4 cv=dNummPZb c=1 sm=1 tr=0 ts=6891a47f cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=2OwXVqhp2XgA:10 a=VnNF1IyMAAAA:8 a=ZRMFVuExfS53ZnwnCJ4A:9 X-Proofpoint-ORIG-GUID: JzARWKijZQTX1fZ4J85RUQnXouNe7SPW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA1MDA0NSBTYWx0ZWRfX0ENfDfgj0Yjq EgcNWuRtzGHzQZTZOC3aupYIkdrT8UjwrOop84pJa9XRQMmwiV2HEcyLDgeyK1t3bjpZo3sYtsF y1DLTObRHQ4BwNiZhZxPmVsTOzoWDDGp/Js3x2retZbU6acbuh+ZUJupG4z6X4GroucpAl6QeoO EwlHFoE2uXr2fsmmdUspLGvhAMRf5eamve9Yzlj6BOLtZVkKeIDX4ofYrE5rgIsLhUioqRP5grl PoZ4TvOBW1sXHIUHpDfcg7/jBa1GG73FSrrc1Bz+DMRQ1EMJW3HcsNC1hw8MSM2mZGN5Ef85HrX ZKuSgjyPPO4lqCJdlkpboE/j4llzxM9TT07a7cbylJMHER3bWCkOpURyci3XrslCu5CV1hWWO7H ZiSA1xgeYtfH1SZLpuYGXV8UkTc7npnu8IoqCZfdUPtb6ztT6+c1WSTM1HHIRyaJblN6JFul X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-05_01,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 mlxscore=0 clxscore=1015 mlxlogscore=813 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508050045 Content-Type: text/plain; charset="utf-8" bpf_jit_emit_probe_mem_store() is introduced to emit instructions for storing memory values depending on the size (byte, halfword, word, doubleword). Signed-off-by: Saket Kumar Bhaskar --- arch/powerpc/net/bpf_jit_comp64.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_c= omp64.c index 025524378443..489de21fe3d6 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -409,6 +409,36 @@ asm ( " blr ;" ); =20 +static int bpf_jit_emit_probe_mem_store(struct codegen_context *ctx, u32 s= rc_reg, s16 off, + u32 code, u32 *image) +{ + u32 tmp1_reg =3D bpf_to_ppc(TMP_REG_1); + u32 tmp2_reg =3D bpf_to_ppc(TMP_REG_2); + + switch (BPF_SIZE(code)) { + case BPF_B: + EMIT(PPC_RAW_STB(src_reg, tmp1_reg, off)); + break; + case BPF_H: + EMIT(PPC_RAW_STH(src_reg, tmp1_reg, off)); + break; + case BPF_W: + EMIT(PPC_RAW_STW(src_reg, tmp1_reg, off)); + break; + case BPF_DW: + if (off % 4) { + EMIT(PPC_RAW_LI(tmp2_reg, off)); + EMIT(PPC_RAW_STDX(src_reg, tmp1_reg, tmp2_reg)); + } else { + EMIT(PPC_RAW_STD(src_reg, tmp1_reg, off)); + } + break; + default: + return -EINVAL; + } + return 0; +} + static int emit_atomic_ld_st(const struct bpf_insn insn, struct codegen_co= ntext *ctx, u32 *image) { u32 code =3D insn.code; --=20 2.43.5 From nobody Sun Oct 5 10:47:12 2025 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFE5F21ABD4; Tue, 5 Aug 2025 06:28:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754375338; cv=none; b=WjBo+C0f4zmxSzu3U74WUqW9X1TUlPJ+Tm7OLfoEdhQCB7FLeLjxYgESU2T1dVDgy1TKn1owuKrQkXFOAHBSqqovNF0Vdbh0Qzbcux5xaZucIGeP/uD+uEV8BzHqC4WJVSsfOC41ZLbcoeK8+4FDhhYPMRc2X4DWBzz5oxvpTN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754375338; c=relaxed/simple; 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Tue, 5 Aug 2025 06:28:10 +0000 (GMT) From: Saket Kumar Bhaskar To: bpf@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Cc: hbathini@linux.ibm.com, sachinpb@linux.ibm.com, venkat88@linux.ibm.com, andrii@kernel.org, eddyz87@gmail.com, mykolal@fb.com, ast@kernel.org, daniel@iogearbox.net, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, john.fastabend@gmail.com, kpsingh@kernel.org, sdf@fomichev.me, haoluo@google.com, jolsa@kernel.org, christophe.leroy@csgroup.eu, naveen@kernel.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, memxor@gmail.com, iii@linux.ibm.com, shuah@kernel.org Subject: [bpf-next 2/6] bpf,powerpc: Implement PROBE_MEM32 pseudo instructions Date: Tue, 5 Aug 2025 11:57:43 +0530 Message-ID: <20250805062747.3479221-3-skb99@linux.ibm.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250805062747.3479221-1-skb99@linux.ibm.com> References: <20250805062747.3479221-1-skb99@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 5GZma-dZGgal9zCf26Gy1vfz1S5_bwv3 X-Proofpoint-ORIG-GUID: Te_J4uSLL7WmQIYhyQWLAeX1HJUOmFeh X-Authority-Analysis: v=2.4 cv=GNoIEvNK c=1 sm=1 tr=0 ts=6891a487 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=2OwXVqhp2XgA:10 a=VnNF1IyMAAAA:8 a=ZFvp2un6vmrCkh9nRUAA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA1MDA0NSBTYWx0ZWRfX9sfsT883v+S1 9/epqTWQdufx/qfvhczBMr+Uylx0mKHdzY5/xQMoBY9NaAjHciLSDn4gGOdKC/k28Ljxd5DRk5B i1jiBYxcFCPqXt5AmhJHnhab/7oLy2EljNQSLO+J5/uvJ9q1khnjmACZVb7xtG0S9MZgz4YhetO JAmB3bhhYpeY5U8b2Yrrph+46TlI8wzNU3/6CfINAKGSPe8Jb4COZrJcLWi1u29UIetr4lYeoGM fjdVZrmTtLpwGyjHEpMfsiQsZ2C/QBawVt7MpmrsEk7eqWC70xYMg/cboy/bGdKTG0pJ5q4CWQg HlX/HCKXKiZ+j8psAHsIrf4nt7tiyDaL8T+JE5Yo1FV4YKeApWOttYHqj94dBxxgCz6+kgVs89X WkmI9gQ8a+H+ABSiJ9PtniXm/kvorYlNCWYuCjYjBua5pHlx9z5hdskcJThWkBuHD6J/pbJA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-05_01,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 bulkscore=0 mlxscore=0 mlxlogscore=899 impostorscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508050045 Content-Type: text/plain; charset="utf-8" Add support for [LDX | STX | ST], PROBE_MEM32, [B | H | W | DW] instructions. They are similar to PROBE_MEM instructions with the following differences: - PROBE_MEM32 supports store. - PROBE_MEM32 relies on the verifier to clear upper 32-bit of the src/dst register - PROBE_MEM32 adds 64-bit kern_vm_start address (which is stored in _R26 in the prologue). Due to bpf_arena constructions such _R26 + reg + off16 access is guaranteed to be within arena virtual range, so no address check at run-time. - PROBE_MEM32 allows STX and ST. If they fault the store is a nop. When LDX faults the destination register is zeroed. To support these on powerpc, we do tmp1 =3D _R26 + src/dst reg and then use tmp1 as the new src/dst register. This allows us to reuse most of the code for normal [LDX | STX | ST]. Signed-off-by: Saket Kumar Bhaskar --- arch/powerpc/net/bpf_jit.h | 5 +- arch/powerpc/net/bpf_jit_comp.c | 10 ++- arch/powerpc/net/bpf_jit_comp32.c | 2 +- arch/powerpc/net/bpf_jit_comp64.c | 108 ++++++++++++++++++++++++++++-- 4 files changed, 114 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h index 4c26912c2e3c..2d095a873305 100644 --- a/arch/powerpc/net/bpf_jit.h +++ b/arch/powerpc/net/bpf_jit.h @@ -161,9 +161,10 @@ struct codegen_context { unsigned int seen; unsigned int idx; unsigned int stack_size; - int b2p[MAX_BPF_JIT_REG + 2]; + int b2p[MAX_BPF_JIT_REG + 3]; unsigned int exentry_idx; unsigned int alt_exit_addr; + u64 arena_vm_start; }; =20 #define bpf_to_ppc(r) (ctx->b2p[r]) @@ -201,7 +202,7 @@ int bpf_jit_emit_exit_insn(u32 *image, struct codegen_c= ontext *ctx, int tmp_reg, =20 int bpf_add_extable_entry(struct bpf_prog *fp, u32 *image, u32 *fimage, in= t pass, struct codegen_context *ctx, int insn_idx, - int jmp_off, int dst_reg); + int jmp_off, int dst_reg, u32 code); =20 #endif =20 diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_com= p.c index c0684733e9d6..35bfdf4d8785 100644 --- a/arch/powerpc/net/bpf_jit_comp.c +++ b/arch/powerpc/net/bpf_jit_comp.c @@ -204,6 +204,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *f= p) =20 /* Make sure that the stack is quadword aligned. */ cgctx.stack_size =3D round_up(fp->aux->stack_depth, 16); + cgctx.arena_vm_start =3D bpf_arena_get_kern_vm_start(fp->aux->arena); =20 /* Scouting faux-generate pass 0 */ if (bpf_jit_build_body(fp, NULL, NULL, &cgctx, addrs, 0, false)) { @@ -326,7 +327,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *f= p) */ int bpf_add_extable_entry(struct bpf_prog *fp, u32 *image, u32 *fimage, in= t pass, struct codegen_context *ctx, int insn_idx, int jmp_off, - int dst_reg) + int dst_reg, u32 code) { off_t offset; unsigned long pc; @@ -354,7 +355,12 @@ int bpf_add_extable_entry(struct bpf_prog *fp, u32 *im= age, u32 *fimage, int pass (fp->aux->num_exentries * BPF_FIXUP_LEN * 4) + (ctx->exentry_idx * BPF_FIXUP_LEN * 4); =20 - fixup[0] =3D PPC_RAW_LI(dst_reg, 0); + if ((BPF_CLASS(code) =3D=3D BPF_LDX && BPF_MODE(code) =3D=3D BPF_PROBE_ME= M32) || + (BPF_CLASS(code) =3D=3D BPF_LDX && BPF_MODE(code) =3D=3D BPF_PROBE_ME= M)) + fixup[0] =3D PPC_RAW_LI(dst_reg, 0); + else if (BPF_CLASS(code) =3D=3D BPF_ST || BPF_CLASS(code) =3D=3D BPF_STX) + fixup[0] =3D PPC_RAW_NOP(); + if (IS_ENABLED(CONFIG_PPC32)) fixup[1] =3D PPC_RAW_LI(dst_reg - 1, 0); /* clear higher 32-bit register= too */ =20 diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_c= omp32.c index 0aace304dfe1..3087e744fb25 100644 --- a/arch/powerpc/net/bpf_jit_comp32.c +++ b/arch/powerpc/net/bpf_jit_comp32.c @@ -1087,7 +1087,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *imag= e, u32 *fimage, struct code } =20 ret =3D bpf_add_extable_entry(fp, image, fimage, pass, ctx, insn_idx, - jmp_off, dst_reg); + jmp_off, dst_reg, code); if (ret) return ret; } diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_c= omp64.c index 489de21fe3d6..16e62766c757 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -44,6 +44,7 @@ /* BPF register usage */ #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) +#define ARENA_VM_START (MAX_BPF_JIT_REG + 2) =20 /* BPF to ppc register mappings */ void bpf_jit_init_reg_mapping(struct codegen_context *ctx) @@ -61,6 +62,8 @@ void bpf_jit_init_reg_mapping(struct codegen_context *ctx) ctx->b2p[BPF_REG_7] =3D _R28; ctx->b2p[BPF_REG_8] =3D _R29; ctx->b2p[BPF_REG_9] =3D _R30; + /* non volatile register for kern_vm_start address */ + ctx->b2p[ARENA_VM_START] =3D _R26; /* frame pointer aka BPF_REG_10 */ ctx->b2p[BPF_REG_FP] =3D _R31; /* eBPF jit internal registers */ @@ -69,8 +72,8 @@ void bpf_jit_init_reg_mapping(struct codegen_context *ctx) ctx->b2p[TMP_REG_2] =3D _R10; } =20 -/* PPC NVR range -- update this if we ever use NVRs below r27 */ -#define BPF_PPC_NVR_MIN _R27 +/* PPC NVR range -- update this if we ever use NVRs below r26 */ +#define BPF_PPC_NVR_MIN _R26 =20 static inline bool bpf_has_stack_frame(struct codegen_context *ctx) { @@ -170,10 +173,17 @@ void bpf_jit_build_prologue(u32 *image, struct codege= n_context *ctx) if (bpf_is_seen_register(ctx, bpf_to_ppc(i))) EMIT(PPC_RAW_STD(bpf_to_ppc(i), _R1, bpf_jit_stack_offsetof(ctx, bpf_to= _ppc(i)))); =20 + if (ctx->arena_vm_start) + EMIT(PPC_RAW_STD(bpf_to_ppc(ARENA_VM_START), _R1, + bpf_jit_stack_offsetof(ctx, bpf_to_ppc(ARENA_VM_START)))); + /* Setup frame pointer to point to the bpf stack area */ if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP))) EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), _R1, STACK_FRAME_MIN_SIZE + ctx->stack_size)); + + if (ctx->arena_vm_start) + PPC_LI64(bpf_to_ppc(ARENA_VM_START), ctx->arena_vm_start); } =20 static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_contex= t *ctx) @@ -185,6 +195,10 @@ static void bpf_jit_emit_common_epilogue(u32 *image, s= truct codegen_context *ctx if (bpf_is_seen_register(ctx, bpf_to_ppc(i))) EMIT(PPC_RAW_LD(bpf_to_ppc(i), _R1, bpf_jit_stack_offsetof(ctx, bpf_to_= ppc(i)))); =20 + if (ctx->arena_vm_start) + EMIT(PPC_RAW_LD(bpf_to_ppc(ARENA_VM_START), _R1, + bpf_jit_stack_offsetof(ctx, bpf_to_ppc(ARENA_VM_START)))); + /* Tear down our stack frame */ if (bpf_has_stack_frame(ctx)) { EMIT(PPC_RAW_ADDI(_R1, _R1, BPF_PPC_STACKFRAME + ctx->stack_size)); @@ -990,6 +1004,50 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *imag= e, u32 *fimage, struct code } break; =20 + case BPF_STX | BPF_PROBE_MEM32 | BPF_B: + case BPF_STX | BPF_PROBE_MEM32 | BPF_H: + case BPF_STX | BPF_PROBE_MEM32 | BPF_W: + case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: + + EMIT(PPC_RAW_ADD(tmp1_reg, dst_reg, bpf_to_ppc(ARENA_VM_START))); + + ret =3D bpf_jit_emit_probe_mem_store(ctx, src_reg, off, code, image); + if (ret) + return ret; + + ret =3D bpf_add_extable_entry(fp, image, fimage, pass, ctx, + ctx->idx - 1, 4, -1, code); + if (ret) + return ret; + + break; + + case BPF_ST | BPF_PROBE_MEM32 | BPF_B: + case BPF_ST | BPF_PROBE_MEM32 | BPF_H: + case BPF_ST | BPF_PROBE_MEM32 | BPF_W: + case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: + + EMIT(PPC_RAW_ADD(tmp1_reg, dst_reg, bpf_to_ppc(ARENA_VM_START))); + + if (BPF_SIZE(code) =3D=3D BPF_W || BPF_SIZE(code) =3D=3D BPF_DW) { + PPC_LI32(tmp2_reg, imm); + src_reg =3D tmp2_reg; + } else { + EMIT(PPC_RAW_LI(tmp2_reg, imm)); + src_reg =3D tmp2_reg; + } + + ret =3D bpf_jit_emit_probe_mem_store(ctx, src_reg, off, code, image); + if (ret) + return ret; + + ret =3D bpf_add_extable_entry(fp, image, fimage, pass, ctx, + ctx->idx - 1, 4, -1, code); + if (ret) + return ret; + + break; + /* * BPF_STX ATOMIC (atomic ops) */ @@ -1142,9 +1200,10 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *ima= ge, u32 *fimage, struct code * Check if 'off' is word aligned for BPF_DW, because * we might generate two instructions. */ - if ((BPF_SIZE(code) =3D=3D BPF_DW || - (BPF_SIZE(code) =3D=3D BPF_B && BPF_MODE(code) =3D=3D BPF_PROBE_ME= MSX)) && - (off & 3)) + if ((BPF_SIZE(code) =3D=3D BPF_DW && (off & 3)) || + (BPF_SIZE(code) =3D=3D BPF_B && + BPF_MODE(code) =3D=3D BPF_PROBE_MEMSX) || + (BPF_SIZE(code) =3D=3D BPF_B && BPF_MODE(code) =3D=3D BPF_MEMSX)) PPC_JMP((ctx->idx + 3) * 4); else PPC_JMP((ctx->idx + 2) * 4); @@ -1190,12 +1249,49 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *im= age, u32 *fimage, struct code =20 if (BPF_MODE(code) =3D=3D BPF_PROBE_MEM) { ret =3D bpf_add_extable_entry(fp, image, fimage, pass, ctx, - ctx->idx - 1, 4, dst_reg); + ctx->idx - 1, 4, dst_reg, code); if (ret) return ret; } break; =20 + /* dst =3D *(u64 *)(ul) (src + ARENA_VM_START + off) */ + case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: + case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: + case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: + case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: + + EMIT(PPC_RAW_ADD(tmp1_reg, src_reg, bpf_to_ppc(ARENA_VM_START))); + + switch (size) { + case BPF_B: + EMIT(PPC_RAW_LBZ(dst_reg, tmp1_reg, off)); + break; + case BPF_H: + EMIT(PPC_RAW_LHZ(dst_reg, tmp1_reg, off)); + break; + case BPF_W: + EMIT(PPC_RAW_LWZ(dst_reg, tmp1_reg, off)); + break; + case BPF_DW: + if (off % 4) { + EMIT(PPC_RAW_LI(tmp2_reg, off)); + EMIT(PPC_RAW_LDX(dst_reg, tmp1_reg, tmp2_reg)); + } else { + EMIT(PPC_RAW_LD(dst_reg, tmp1_reg, off)); + } + break; + } + + if (size !=3D BPF_DW && insn_is_zext(&insn[i + 1])) + addrs[++i] =3D ctx->idx * 4; + + ret =3D bpf_add_extable_entry(fp, image, fimage, pass, ctx, + ctx->idx - 1, 4, dst_reg, code); + if (ret) + return ret; + break; + /* * Doubleword load * 16 byte instruction that uses two 'struct bpf_insn' --=20 2.43.5 From nobody Sun Oct 5 10:47:12 2025 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C24F821ABCF; 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charset="utf-8" LLVM generates bpf_addr_space_cast instruction while translating pointers between native (zero) address space and __attribute__((address_space(N))). The addr_space=3D0 is reserved as bpf_arena address space. rY =3D addr_space_cast(rX, 0, 1) is processed by the verifier and converted to normal 32-bit move: wX =3D wY. rY =3D addr_space_cast(rX, 1, 0) : used to convert a bpf arena pointer to a pointer in the userspace vma. This has to be converted by the JIT. Signed-off-by: Saket Kumar Bhaskar --- arch/powerpc/net/bpf_jit.h | 1 + arch/powerpc/net/bpf_jit_comp.c | 6 ++++++ arch/powerpc/net/bpf_jit_comp64.c | 11 +++++++++++ 3 files changed, 18 insertions(+) diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h index 2d095a873305..748e30e8b5b4 100644 --- a/arch/powerpc/net/bpf_jit.h +++ b/arch/powerpc/net/bpf_jit.h @@ -165,6 +165,7 @@ struct codegen_context { unsigned int exentry_idx; unsigned int alt_exit_addr; u64 arena_vm_start; + u64 user_vm_start; }; =20 #define bpf_to_ppc(r) (ctx->b2p[r]) diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_com= p.c index 35bfdf4d8785..2b3f90930c27 100644 --- a/arch/powerpc/net/bpf_jit_comp.c +++ b/arch/powerpc/net/bpf_jit_comp.c @@ -205,6 +205,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *f= p) /* Make sure that the stack is quadword aligned. */ cgctx.stack_size =3D round_up(fp->aux->stack_depth, 16); cgctx.arena_vm_start =3D bpf_arena_get_kern_vm_start(fp->aux->arena); + cgctx.user_vm_start =3D bpf_arena_get_user_vm_start(fp->aux->arena); =20 /* Scouting faux-generate pass 0 */ if (bpf_jit_build_body(fp, NULL, NULL, &cgctx, addrs, 0, false)) { @@ -441,6 +442,11 @@ bool bpf_jit_supports_kfunc_call(void) return true; } =20 +bool bpf_jit_supports_arena(void) +{ + return IS_ENABLED(CONFIG_PPC64); +} + bool bpf_jit_supports_far_kfunc_call(void) { return IS_ENABLED(CONFIG_PPC64); diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_c= omp64.c index 16e62766c757..d4fe4dacf2d6 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -812,6 +812,17 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image= , u32 *fimage, struct code */ case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst =3D src */ case BPF_ALU64 | BPF_MOV | BPF_X: /* dst =3D src */ + + if (insn_is_cast_user(&insn[i])) { + EMIT(PPC_RAW_RLDICL(tmp1_reg, src_reg, 0, 32)); + PPC_LI64(dst_reg, (ctx->user_vm_start & 0xffffffff00000000UL)); + EMIT(PPC_RAW_CMPDI(tmp1_reg, 0)); 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Tue, 5 Aug 2025 06:28:24 +0000 (GMT) From: Saket Kumar Bhaskar To: bpf@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Cc: hbathini@linux.ibm.com, sachinpb@linux.ibm.com, venkat88@linux.ibm.com, andrii@kernel.org, eddyz87@gmail.com, mykolal@fb.com, ast@kernel.org, daniel@iogearbox.net, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, john.fastabend@gmail.com, kpsingh@kernel.org, sdf@fomichev.me, haoluo@google.com, jolsa@kernel.org, christophe.leroy@csgroup.eu, naveen@kernel.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, memxor@gmail.com, iii@linux.ibm.com, shuah@kernel.org Subject: [bpf-next 4/6] bpf,powerpc: Introduce bpf_jit_emit_atomic_ops() to emit atomic instructions Date: Tue, 5 Aug 2025 11:57:45 +0530 Message-ID: <20250805062747.3479221-5-skb99@linux.ibm.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250805062747.3479221-1-skb99@linux.ibm.com> References: <20250805062747.3479221-1-skb99@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA1MDA0NSBTYWx0ZWRfXwiJSf2dWPA2n 2Iv/EQoxRlLW23TjNZ0uDp6JwW6KZePtFViAxhd5mt4bcRvYZRMFSJPErJS6dszQ6nQHfWtXGQ3 lDMydrDdFweplrZSzAiFbIlOYz/uVS1MhTy4N2ybUo2QwZDzHe7Abd99vDvO8E3FalZvAXF3Ja7 hgibLd7fKp2XUMajCCe2lQLxiKXu3brJXpf/828GQoiKrMiznM/o1jJcmAACv55tkmCRhGeg/nB x7Sth7L1eb8HcdWG0ubziEmwnvjzhoNbZn1Jxj/624phGxAUZeZXDYlf1l0CTpoMoqKe+EebRXo fIbDXgGny0ypovrRrQn/MSJT25aUhWS6d617KVb0KH7O4QzjAJZMw97WgbaYHTF3CvtMqw+BFGB 0WCem9zn2GtKsi6lr6C4o970Js3dMVUxB0eANGlNi8jGi4RrrhacCoaE8dR4eOamGoYeI6ss X-Proofpoint-GUID: y1IvXRs28EEz1D4IoEQyuqPzy5m9abLt X-Proofpoint-ORIG-GUID: 5m-gE2FuSQ8KJqOr79Xa4f8uo9KsfHfl X-Authority-Analysis: v=2.4 cv=AZSxH2XG c=1 sm=1 tr=0 ts=6891a495 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=2OwXVqhp2XgA:10 a=VnNF1IyMAAAA:8 a=mLi99PhJ1kaOFlELNpEA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-05_01,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508050045 Content-Type: text/plain; charset="utf-8" The existing code for emitting bpf atomic instruction sequences for atomic operations such as XCHG, CMPXCHG, ADD, AND, OR, and XOR has been refactored into a reusable function, bpf_jit_emit_ppc_atomic_op(). It also computes the jump offset and tracks the instruction index for jited LDARX/LWARX to be used in case it causes a fault. Signed-off-by: Saket Kumar Bhaskar --- arch/powerpc/net/bpf_jit_comp64.c | 203 +++++++++++++++++------------- 1 file changed, 115 insertions(+), 88 deletions(-) diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_c= omp64.c index d4fe4dacf2d6..6a85cd847075 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -423,6 +423,111 @@ asm ( " blr ;" ); =20 +static int bpf_jit_emit_atomic_ops(u32 *image, struct codegen_context *ctx, + const struct bpf_insn *insn, u32 *jmp_off, + u32 *tmp_idx, u32 *addrp) +{ + u32 tmp1_reg =3D bpf_to_ppc(TMP_REG_1); + u32 tmp2_reg =3D bpf_to_ppc(TMP_REG_2); + u32 size =3D BPF_SIZE(insn->code); + u32 src_reg =3D bpf_to_ppc(insn->src_reg); + u32 dst_reg =3D bpf_to_ppc(insn->dst_reg); + s32 imm =3D insn->imm; + + u32 save_reg =3D tmp2_reg; + u32 ret_reg =3D src_reg; + u32 fixup_idx; + + /* Get offset into TMP_REG_1 */ + EMIT(PPC_RAW_LI(tmp1_reg, insn->off)); + /* + * Enforce full ordering for operations with BPF_FETCH by emitting a 'sync' + * before and after the operation. + * + * This is a requirement in the Linux Kernel Memory Model. + * See __cmpxchg_u64() in asm/cmpxchg.h as an example. + */ + if ((imm & BPF_FETCH) && IS_ENABLED(CONFIG_SMP)) + EMIT(PPC_RAW_SYNC()); + + *tmp_idx =3D ctx->idx; + + /* load value from memory into TMP_REG_2 */ + if (size =3D=3D BPF_DW) + EMIT(PPC_RAW_LDARX(tmp2_reg, tmp1_reg, dst_reg, 0)); + else + EMIT(PPC_RAW_LWARX(tmp2_reg, tmp1_reg, dst_reg, 0)); + /* Save old value in _R0 */ + if (imm & BPF_FETCH) + EMIT(PPC_RAW_MR(_R0, tmp2_reg)); + + switch (imm) { + case BPF_ADD: + case BPF_ADD | BPF_FETCH: + EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg)); + break; + case BPF_AND: + case BPF_AND | BPF_FETCH: + EMIT(PPC_RAW_AND(tmp2_reg, tmp2_reg, src_reg)); + break; + case BPF_OR: + case BPF_OR | BPF_FETCH: + EMIT(PPC_RAW_OR(tmp2_reg, tmp2_reg, src_reg)); + break; + case BPF_XOR: + case BPF_XOR | BPF_FETCH: + EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg)); + break; + case BPF_CMPXCHG: + /* + * Return old value in BPF_REG_0 for BPF_CMPXCHG & + * in src_reg for other cases. + */ + ret_reg =3D bpf_to_ppc(BPF_REG_0); + + /* Compare with old value in BPF_R0 */ + if (size =3D=3D BPF_DW) + EMIT(PPC_RAW_CMPD(bpf_to_ppc(BPF_REG_0), tmp2_reg)); + else + EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), tmp2_reg)); + /* Don't set if different from old value */ + PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4); + fallthrough; + case BPF_XCHG: + save_reg =3D src_reg; + break; + default: + return -EOPNOTSUPP; + } + + /* store new value */ + if (size =3D=3D BPF_DW) + EMIT(PPC_RAW_STDCX(save_reg, tmp1_reg, dst_reg)); + else + EMIT(PPC_RAW_STWCX(save_reg, tmp1_reg, dst_reg)); + /* we're done if this succeeded */ + PPC_BCC_SHORT(COND_NE, *tmp_idx * 4); + fixup_idx =3D ctx->idx; + + if (imm & BPF_FETCH) { + /* Emit 'sync' to enforce full ordering */ + if (IS_ENABLED(CONFIG_SMP)) + EMIT(PPC_RAW_SYNC()); + EMIT(PPC_RAW_MR(ret_reg, _R0)); + /* + * Skip unnecessary zero-extension for 32-bit cmpxchg. + * For context, see commit 39491867ace5. + */ + if (size !=3D BPF_DW && imm =3D=3D BPF_CMPXCHG && + insn_is_zext(insn + 1)) + *addrp =3D ctx->idx * 4; + } + + *jmp_off =3D (fixup_idx - *tmp_idx) * 4; + + return 0; +} + static int bpf_jit_emit_probe_mem_store(struct codegen_context *ctx, u32 s= rc_reg, s16 off, u32 code, u32 *image) { @@ -538,7 +643,6 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,= u32 *fimage, struct code u32 size =3D BPF_SIZE(code); u32 tmp1_reg =3D bpf_to_ppc(TMP_REG_1); u32 tmp2_reg =3D bpf_to_ppc(TMP_REG_2); - u32 save_reg, ret_reg; s16 off =3D insn[i].off; s32 imm =3D insn[i].imm; bool func_addr_fixed; @@ -546,6 +650,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,= u32 *fimage, struct code u64 imm64; u32 true_cond; u32 tmp_idx; + u32 jmp_off; =20 /* * addrs[] maps a BPF bytecode address into a real offset from @@ -1081,93 +1186,15 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *im= age, u32 *fimage, struct code return -EOPNOTSUPP; } =20 - save_reg =3D tmp2_reg; - ret_reg =3D src_reg; - - /* Get offset into TMP_REG_1 */ - EMIT(PPC_RAW_LI(tmp1_reg, off)); - /* - * Enforce full ordering for operations with BPF_FETCH by emitting a 's= ync' - * before and after the operation. - * - * This is a requirement in the Linux Kernel Memory Model. - * See __cmpxchg_u64() in asm/cmpxchg.h as an example. - */ - if ((imm & BPF_FETCH) && IS_ENABLED(CONFIG_SMP)) - EMIT(PPC_RAW_SYNC()); - tmp_idx =3D ctx->idx * 4; - /* load value from memory into TMP_REG_2 */ - if (size =3D=3D BPF_DW) - EMIT(PPC_RAW_LDARX(tmp2_reg, tmp1_reg, dst_reg, 0)); - else - EMIT(PPC_RAW_LWARX(tmp2_reg, tmp1_reg, dst_reg, 0)); - - /* Save old value in _R0 */ - if (imm & BPF_FETCH) - EMIT(PPC_RAW_MR(_R0, tmp2_reg)); - - switch (imm) { - case BPF_ADD: - case BPF_ADD | BPF_FETCH: - EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg)); - break; - case BPF_AND: - case BPF_AND | BPF_FETCH: - EMIT(PPC_RAW_AND(tmp2_reg, tmp2_reg, src_reg)); - break; - case BPF_OR: - case BPF_OR | BPF_FETCH: - EMIT(PPC_RAW_OR(tmp2_reg, tmp2_reg, src_reg)); - break; - case BPF_XOR: - case BPF_XOR | BPF_FETCH: - EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg)); - break; - case BPF_CMPXCHG: - /* - * Return old value in BPF_REG_0 for BPF_CMPXCHG & - * in src_reg for other cases. - */ - ret_reg =3D bpf_to_ppc(BPF_REG_0); - - /* Compare with old value in BPF_R0 */ - if (size =3D=3D BPF_DW) - EMIT(PPC_RAW_CMPD(bpf_to_ppc(BPF_REG_0), tmp2_reg)); - else - EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), tmp2_reg)); - /* Don't set if different from old value */ - PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4); - fallthrough; - case BPF_XCHG: - save_reg =3D src_reg; - break; - default: - pr_err_ratelimited( - "eBPF filter atomic op code %02x (@%d) unsupported\n", - code, i); - return -EOPNOTSUPP; - } - - /* store new value */ - if (size =3D=3D BPF_DW) - EMIT(PPC_RAW_STDCX(save_reg, tmp1_reg, dst_reg)); - else - EMIT(PPC_RAW_STWCX(save_reg, tmp1_reg, dst_reg)); - /* we're done if this succeeded */ - PPC_BCC_SHORT(COND_NE, tmp_idx); - - if (imm & BPF_FETCH) { - /* Emit 'sync' to enforce full ordering */ - if (IS_ENABLED(CONFIG_SMP)) - EMIT(PPC_RAW_SYNC()); - EMIT(PPC_RAW_MR(ret_reg, _R0)); - /* - * Skip unnecessary zero-extension for 32-bit cmpxchg. - * For context, see commit 39491867ace5. - */ - if (size !=3D BPF_DW && imm =3D=3D BPF_CMPXCHG && - insn_is_zext(&insn[i + 1])) - addrs[++i] =3D ctx->idx * 4; + ret =3D bpf_jit_emit_atomic_ops(image, ctx, &insn[i], + &jmp_off, &tmp_idx, &addrs[i + 1]); + if (ret) { + if (ret =3D=3D -EOPNOTSUPP) { + pr_err_ratelimited( + "eBPF filter atomic op code %02x (@%d) unsupported\n", + code, i); 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Tue, 5 Aug 2025 06:28:39 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1BC2020043; Tue, 5 Aug 2025 06:28:39 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6329920040; Tue, 5 Aug 2025 06:28:32 +0000 (GMT) Received: from li-621bac4c-27c7-11b2-a85c-c2bf7c4b3c07.ibm.com.com (unknown [9.43.39.141]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 5 Aug 2025 06:28:32 +0000 (GMT) From: Saket Kumar Bhaskar To: bpf@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Cc: hbathini@linux.ibm.com, sachinpb@linux.ibm.com, venkat88@linux.ibm.com, andrii@kernel.org, eddyz87@gmail.com, mykolal@fb.com, ast@kernel.org, daniel@iogearbox.net, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, john.fastabend@gmail.com, kpsingh@kernel.org, sdf@fomichev.me, haoluo@google.com, jolsa@kernel.org, christophe.leroy@csgroup.eu, naveen@kernel.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, memxor@gmail.com, iii@linux.ibm.com, shuah@kernel.org Subject: [bpf-next 5/6] bpf,powerpc: Implement PROBE_ATOMIC instructions Date: Tue, 5 Aug 2025 11:57:46 +0530 Message-ID: <20250805062747.3479221-6-skb99@linux.ibm.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250805062747.3479221-1-skb99@linux.ibm.com> References: <20250805062747.3479221-1-skb99@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: cMapiujoCaDYWPc6M9nlonA3aMn4IR7W X-Authority-Analysis: v=2.4 cv=M65NKzws c=1 sm=1 tr=0 ts=6891a49c cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=2OwXVqhp2XgA:10 a=VnNF1IyMAAAA:8 a=I9DJoMOgBESJXZyRRMQA:9 X-Proofpoint-ORIG-GUID: DOHj20Ewu0d5mY2NQXm-zlLvBjAbqg4q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA1MDA0NSBTYWx0ZWRfX2QrxuUck/E// pm7s8+xq1uWVnBtf9t2bH3Kneh1Bb63rmsIOD95BH3gxQM+Pc985+bb4HndNDkwTmGoqgOrPYxG d8qMdGKj9ZW8g5LayUOuDwk+aH+9CgBlhMnGAoQJdC3APy0CEx9TDnCZUMX892mP0ttHd2Anw/Y q8pRZZNbXMXxGCpvx5L4f49ZitFtvg8O68weQmLnQG35tXVqRC5i+Ee8mgKpwtvPKm/ynXAP1yD k1k9m8Qzzof2ScW/OKUK5b3jse/IA1yan1hMezltVPHRfnfJu0YAHjxw2J/fdiLacrS8k3B3tq7 voPGUfbsFyf753FSWqkC+282qbFYnRDi5p8lMhbnXd0PHmNEl9nrix1kuA2UYVtLVs7psBpSXIz eKn5+1b8ZzjWGndjbnWLt3xTLqo341TKynpYzdomYdeFDVSkF6OlFdODY8qpy6MY2HKcte0y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-05_01,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 mlxscore=0 phishscore=0 priorityscore=1501 mlxlogscore=896 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508050045 Content-Type: text/plain; charset="utf-8" powerpc supports BPF atomic operations using a loop around Load-And-Reserve(LDARX/LWARX) and Store-Conditional(STDCX/STWCX) instructions gated by sync instructions to enforce full ordering. To implement arena_atomics, arena vm start address is added to the dst_reg to be used for both the LDARX/LWARX and STDCX/STWCX instructions. Further, an exception table entry is added for LDARX/LWARX instruction to land after the loop on fault. At the end of sequence, dst_reg is restored by subtracting arena vm start address. bpf_jit_supports_insn() is introduced to selectively enable instruction support as in other architectures like x86 and arm64. Signed-off-by: Saket Kumar Bhaskar --- arch/powerpc/net/bpf_jit_comp.c | 16 ++++++++++++++++ arch/powerpc/net/bpf_jit_comp64.c | 26 ++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_com= p.c index 2b3f90930c27..69232ee56c6a 100644 --- a/arch/powerpc/net/bpf_jit_comp.c +++ b/arch/powerpc/net/bpf_jit_comp.c @@ -452,6 +452,22 @@ bool bpf_jit_supports_far_kfunc_call(void) return IS_ENABLED(CONFIG_PPC64); } =20 +bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) +{ + if (!in_arena) + return true; + switch (insn->code) { + case BPF_STX | BPF_ATOMIC | BPF_H: + case BPF_STX | BPF_ATOMIC | BPF_B: + case BPF_STX | BPF_ATOMIC | BPF_W: + case BPF_STX | BPF_ATOMIC | BPF_DW: + if (bpf_atomic_is_load_store(insn)) + return false; + return IS_ENABLED(CONFIG_PPC64); + } + return true; +} + void *arch_alloc_bpf_trampoline(unsigned int size) { return bpf_prog_pack_alloc(size, bpf_jit_fill_ill_insns); diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_c= omp64.c index 6a85cd847075..8931bded97f4 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -1164,6 +1164,32 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *ima= ge, u32 *fimage, struct code =20 break; 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Tue, 5 Aug 2025 06:28:46 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3B7C920040; Tue, 5 Aug 2025 06:28:46 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8934B20043; Tue, 5 Aug 2025 06:28:39 +0000 (GMT) Received: from li-621bac4c-27c7-11b2-a85c-c2bf7c4b3c07.ibm.com.com (unknown [9.43.39.141]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 5 Aug 2025 06:28:39 +0000 (GMT) From: Saket Kumar Bhaskar To: bpf@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Cc: hbathini@linux.ibm.com, sachinpb@linux.ibm.com, venkat88@linux.ibm.com, andrii@kernel.org, eddyz87@gmail.com, mykolal@fb.com, ast@kernel.org, daniel@iogearbox.net, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, john.fastabend@gmail.com, kpsingh@kernel.org, sdf@fomichev.me, haoluo@google.com, jolsa@kernel.org, christophe.leroy@csgroup.eu, naveen@kernel.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, memxor@gmail.com, iii@linux.ibm.com, shuah@kernel.org Subject: [bpf-next 6/6] selftests/bpf: Fix arena_spin_lock selftest failure Date: Tue, 5 Aug 2025 11:57:47 +0530 Message-ID: <20250805062747.3479221-7-skb99@linux.ibm.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250805062747.3479221-1-skb99@linux.ibm.com> References: <20250805062747.3479221-1-skb99@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MHtfuhSBX86H1GS-EDUE7_iMFDkm4UOi X-Authority-Analysis: v=2.4 cv=M65NKzws c=1 sm=1 tr=0 ts=6891a4a3 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=2OwXVqhp2XgA:10 a=VnNF1IyMAAAA:8 a=JZnv35P8lLju3lMB9JkA:9 X-Proofpoint-ORIG-GUID: RLgM9aYmcIzILwAR7Iotf-RVGtxWO2zm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA1MDA0NSBTYWx0ZWRfX1K7J+oUmd5nL mfCZkWQLhWPVY9M222gUMff3yf4Zg+BRL0jXdtdHhtkRVXWByE6K8Uh1KpHEC7LoLklxpQGD/r9 hIimr1BHSV7ECIDd6qkwC4BRM/cedilc7J58riP9sgBy/RBTa31HyO4ui6C7VHH/gohDCwhI3AL 3krUVIZFugLWIcW3NsTJAIzSAQh8/ddSezjMSMmPZRPQep/931tnHC+X+0HOfPH83KwVp/82iUP F7z6aVpGcFdwdZeaSOuSQW+zdompotUc+Q34c3lO5X8yREM553guktYZzyAksnNR2ToJybF33kn zAvMFtPrgIdtWoWhJ32V3HR9xtldl8cJssl1j0X8D2MgUVn2Yxb43rla10I6c0JNNOG7cDxbBjW 34enIJSqdMAGf20IWycsqEe9nNXw2euxgZ98BCDMleohl3EHgxqVI3Br6cMRfzxWpOQswMIa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-05_01,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 mlxscore=0 phishscore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508050045 Content-Type: text/plain; charset="utf-8" For systems having CONFIG_NR_CPUS set to > 1024 in kernel config the selftest fails even though the current number of online cpus is less. For example, on powerpc the default value for CONFIG_NR_CPUS is set to 8192. get_nprocs() is used to get the number of available cpus in test driver code and the same is passed to the bpf program using rodata. Also the selftest is skipped incase bpf program returns EOPNOTSUPP, with a descriptive message logged. Signed-off-by: Saket Kumar Bhaskar --- .../bpf/prog_tests/arena_spin_lock.c | 23 +++++++++++++++++-- .../selftests/bpf/progs/arena_spin_lock.c | 8 ++++++- .../selftests/bpf/progs/bpf_arena_spin_lock.h | 4 +--- 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/bpf/prog_tests/arena_spin_lock.c b/too= ls/testing/selftests/bpf/prog_tests/arena_spin_lock.c index 0223fce4db2b..fa0b4f0240a3 100644 --- a/tools/testing/selftests/bpf/prog_tests/arena_spin_lock.c +++ b/tools/testing/selftests/bpf/prog_tests/arena_spin_lock.c @@ -40,8 +40,13 @@ static void *spin_lock_thread(void *arg) =20 err =3D bpf_prog_test_run_opts(prog_fd, &topts); ASSERT_OK(err, "test_run err"); + + if (topts.retval =3D=3D -EOPNOTSUPP) + goto end; + ASSERT_EQ((int)topts.retval, 0, "test_run retval"); =20 +end: pthread_exit(arg); } =20 @@ -60,9 +65,16 @@ static void test_arena_spin_lock_size(int size) return; } =20 - skel =3D arena_spin_lock__open_and_load(); - if (!ASSERT_OK_PTR(skel, "arena_spin_lock__open_and_load")) + skel =3D arena_spin_lock__open(); + if (!ASSERT_OK_PTR(skel, "arena_spin_lock__open")) return; + + skel->rodata->nr_cpus =3D get_nprocs(); + + err =3D arena_spin_lock__load(skel); + if (!ASSERT_OK(err, "arena_spin_lock__load")) + goto end; + if (skel->data->test_skip =3D=3D 2) { test__skip(); goto end; @@ -86,6 +98,13 @@ static void test_arena_spin_lock_size(int size) goto end_barrier; } =20 + if (skel->data->test_skip =3D=3D 2) { + printf("%s:SKIP: %d online CPUs exceed the maximum supported by arena sp= inlock\n", + __func__, get_nprocs()); + test__skip(); + goto end_barrier; + } + ASSERT_EQ(skel->bss->counter, repeat * nthreads, "check counter value"); =20 end_barrier: diff --git a/tools/testing/selftests/bpf/progs/arena_spin_lock.c b/tools/te= sting/selftests/bpf/progs/arena_spin_lock.c index c4500c37f85e..9ed5a3281fd4 100644 --- a/tools/testing/selftests/bpf/progs/arena_spin_lock.c +++ b/tools/testing/selftests/bpf/progs/arena_spin_lock.c @@ -4,6 +4,9 @@ #include #include #include "bpf_misc.h" + +const volatile int nr_cpus; + #include "bpf_arena_spin_lock.h" =20 struct { @@ -37,8 +40,11 @@ int prog(void *ctx) #if defined(ENABLE_ATOMICS_TESTS) && defined(__BPF_FEATURE_ADDR_SPACE_CAST) unsigned long flags; =20 - if ((ret =3D arena_spin_lock_irqsave(&lock, flags))) + if ((ret =3D arena_spin_lock_irqsave(&lock, flags))) { + if (ret =3D=3D -EOPNOTSUPP) + test_skip =3D 2; return ret; + } if (counter !=3D limit) counter++; bpf_repeat(cs_count); diff --git a/tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h b/tool= s/testing/selftests/bpf/progs/bpf_arena_spin_lock.h index d67466c1ff77..752131161315 100644 --- a/tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h +++ b/tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h @@ -20,8 +20,6 @@ #define __arena __attribute__((address_space(1))) #endif =20 -extern unsigned long CONFIG_NR_CPUS __kconfig; - /* * Typically, we'd just rely on the definition in vmlinux.h for qspinlock,= but * PowerPC overrides the definition to define lock->val as u32 instead of @@ -494,7 +492,7 @@ static __always_inline int arena_spin_lock(arena_spinlo= ck_t __arena *lock) { int val =3D 0; =20 - if (CONFIG_NR_CPUS > 1024) + if (nr_cpus > 1024) return -EOPNOTSUPP; =20 bpf_preempt_disable(); --=20 2.43.5