From nobody Sun Oct 5 12:51:00 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D0A4274B32 for ; Tue, 5 Aug 2025 11:56:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754395021; cv=none; b=rVrcmV/zbeNmoNOdZMjop0tniwqFAn85UQuOXblPnBbw5TeYNy8HrCMujDrczlAzLkw3yTjMuDWNcVQ0l0/yTzKfxJ/E+v4ws59+gCatFene7yNOc5kdceL6f4Yp+AdhtXI2N0jMyRzVu/zOwzskapqwgyivIbzoE/XT+afvy1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754395021; c=relaxed/simple; bh=xMXen/bHQmq8eILCFZkOq3t0CKOepKADVu7/ZOwpRaE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oUPRjSmu2UuaUItkJJje21ffZ3+EgwH/eBh8rGib3yp8N/ukWbVaIdJnCm/1k7xAjjVttuOvYJp6PwrF2OiI+ZjGkG7X2g5s2KZJjnauSB5yqBekTFkQBNeh6vKYNFtc9GN1aecwFr243U0+DtRmn/XzVOwDfv3NyX1SO7QpJN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=hBRYKf5x; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="hBRYKf5x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754395017; bh=xMXen/bHQmq8eILCFZkOq3t0CKOepKADVu7/ZOwpRaE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hBRYKf5xtHx5sucEvqK4GD538m/d/Y5W5uoF0SNFq2XenO30SQSs0/oUg9TtkxhrO ddFsvwxiZszzR51Uo+3MEdgbtaXBeuJWnsru/lxGeJ+EugIaUmauagRBHs69gcrbGH GbVQWL+ijOSF8B8PwlkECi3lUDA/gcH8l6McdKmILSWqLDWPCghhelk6PABV0050Sm W7Ivyk29NpYcgp3IZHhqvHntSNcmKc0Ibi/aQnMFSZ93dyFIYgo5J5lRi++IQMBHWu vRV7lo2tOUVs5kVP6XTtzB6ugt9wpvUv7UOyaESrjnzahoYKiPXg2djS01wvv3O1Gs BbTAN3DLOHQvg== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 69E8C17E0202; Tue, 5 Aug 2025 13:56:57 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 05 Aug 2025 14:56:55 +0300 Subject: [PATCH v2 13/14] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250805-phy-hdptx-frl-v2-13-d118bd4b6e0b@collabora.com> References: <20250805-phy-hdptx-frl-v2-0-d118bd4b6e0b@collabora.com> In-Reply-To: <20250805-phy-hdptx-frl-v2-0-d118bd4b6e0b@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In order to facilitate introduction of HDMI 2.1 FRL support and to avoid recomputing the link rate after verifying the HDMI configuration given as input, extend rk_hdptx_phy_verify_hdmi_config() by providing an optional output parameter to store the validated configuration. For improved code readability, also rename the existing hdmi input parameter. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 35 ++++++++++++-------= ---- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index a44614bc73e9461d4d38663776f547f595169c3b..58eac67cc3b21c17939c303bbea= 3fcdc5e6b0518 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1472,25 +1472,24 @@ static int rk_hdptx_phy_power_off(struct phy *phy) } =20 static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, - struct phy_configure_opts_hdmi *hdmi) + struct phy_configure_opts_hdmi *hdmi_in, + struct rk_hdptx_hdmi_cfg *hdmi_out) { int i; =20 - if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) + if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) - if (hdmi->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) + if (hdmi_in->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) break; =20 if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && - !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) + !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL)) return -EINVAL; =20 - if (!hdmi->bpc) - hdmi->bpc =3D 8; - - switch (hdmi->bpc) { + switch (hdmi_in->bpc) { + case 0: case 8: case 10: case 12: @@ -1500,6 +1499,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, return -EINVAL; } =20 + if (hdmi_out) { + hdmi_out->rate =3D hdmi_in->tmds_char_rate; + hdmi_out->bpc =3D hdmi_in->bpc ?: 8; + } + return 0; } =20 @@ -1765,17 +1769,15 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt int ret; =20 if (mode !=3D PHY_MODE_DP) { - ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, &hdptx->hdmi= _cfg); if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->hdmi_cfg.rate =3D opts->hdmi.tmds_char_rate; - hdptx->hdmi_cfg.bpc =3D opts->hdmi.bpc; hdptx->restrict_rate_change =3D true; + dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); } =20 - dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); return ret; } =20 @@ -1819,7 +1821,7 @@ static int rk_hdptx_phy_validate(struct phy *phy, enu= m phy_mode mode, struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); =20 if (mode !=3D PHY_MODE_DP) - return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, NULL); =20 return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); } @@ -1959,12 +1961,11 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_= hw *hw, unsigned long rate, struct phy_configure_opts_hdmi hdmi =3D { .tmds_char_rate =3D rate, }; - int ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi); + + int ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi, &hdptx->hdmi_c= fg); =20 if (ret) return ret; - - hdptx->hdmi_cfg.rate =3D rate; } =20 /* --=20 2.50.0