From nobody Sun Oct 5 12:36:01 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F51252286 for ; Mon, 4 Aug 2025 23:25:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754349918; cv=none; b=G8mpoonDZM8eKqv593higrD5UVA7UFO+qcK/3smMVn1bSQQpqQQ9M+7XjaC/Bu8E8lfcEeV+wqM0zQM4ImErjnzUWKEHRhfrr8oDq81vlOwnAMG/qEqux5JbOCAUV8EY/pQ5U7I9obgY1KwNVkauxESKxo8LipARd1Ya587GwYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754349918; c=relaxed/simple; bh=QRkYReBKbhL3C6JHSPQLpNjm/3h07MrTwDuUpSUppFk=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=QClr6EdB4RoJz9MlbztoPCgeAaPL2DRqARkrjRWegA4Dgz6aJyT+qnLshlhJyYtGKG9Ity6fZDrG+jzI1Uvgic2gAFkJAPPiXttv4M2cnJ+HcAGtBq+yN4eIaERxRcELP5cOYcr6YXd1zTTjAzjt6U1z+KQOnLMZyOtgYVpm6EY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=DRJUaohc; arc=none smtp.client-ip=210.118.77.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="DRJUaohc" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20250804232514euoutp019dbe8ddbc393c9c89940761ff7e26fa0~Ys-O-46Cs0925209252euoutp01D for ; Mon, 4 Aug 2025 23:25:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20250804232514euoutp019dbe8ddbc393c9c89940761ff7e26fa0~Ys-O-46Cs0925209252euoutp01D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1754349914; bh=XgtuGVmgQ4duTRcu7yxrlM+/W0pETlvqiX9sxjj/NBQ=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=DRJUaohc8Rj2YNKz+VHJIIZ5eb57RsgKgeI94qSpZhUJhewZ9YN2ePFyIlU7trcgK eJj9eQSnhipFsg2E+2jPaZPesyugZlpN9aZ6jYwDe6xNd2gQZNChhzViuNv0Afqvxi 9e4gkOypUKsdQGVI81BUgfjU08H9zoUj7qvyxKeE= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250804232512eucas1p27563ded6cc0f01c9e3a38f000a0d2584~Ys-NhyGc42562425624eucas1p2L; Mon, 4 Aug 2025 23:25:12 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250804232511eusmtip291cff0ab1246c9c2c9c3eb2cb93f318a~Ys-MkM7wC0897408974eusmtip2N; Mon, 4 Aug 2025 23:25:11 +0000 (GMT) From: Michal Wilczynski Date: Tue, 05 Aug 2025 01:25:01 +0200 Subject: [PATCH v11 1/4] drm/imagination: Use pwrseq for TH1520 GPU power management Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250805-apr_14_for_sending-v11-1-b7eecefcfdc0@samsung.com> In-Reply-To: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250804232512eucas1p27563ded6cc0f01c9e3a38f000a0d2584 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250804232512eucas1p27563ded6cc0f01c9e3a38f000a0d2584 X-EPHeader: CA X-CMS-RootMailID: 20250804232512eucas1p27563ded6cc0f01c9e3a38f000a0d2584 References: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> Update the Imagination PVR DRM driver to leverage the pwrseq framework for managing the complex power sequence of the GPU on the T-HEAD TH1520 SoC. To cleanly separate platform-specific logic from the generic driver, this patch introduces an `init` callback to the `pwr_power_sequence_ops` struct. This allows for different power management strategies to be selected at probe time based on the device's compatible string. A `pvr_device_data` struct, associated with each compatible in the of_device_id table, points to the appropriate ops table (manual or pwrseq). At probe time, the driver now calls the `->init()` op. For pwrseq-based platforms, this callback calls `devm_pwrseq_get("gpu-power")`, deferring probe if the sequencer is not yet available. For other platforms, it falls back to the existing manual clock and reset handling. The runtime PM callbacks continue to call the appropriate functions via the ops table. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/pvr_device.c | 22 +--- drivers/gpu/drm/imagination/pvr_device.h | 22 ++++ drivers/gpu/drm/imagination/pvr_drv.c | 27 ++++- drivers/gpu/drm/imagination/pvr_power.c | 174 ++++++++++++++++++++++++---= ---- drivers/gpu/drm/imagination/pvr_power.h | 15 +++ 5 files changed, 201 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 8b9ba4983c4cb5bc40342fcafc4259078bc70547..294b6019b4155bb7fdb7de73ccf= 7fa8ad867811f 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -121,21 +122,6 @@ static int pvr_device_clk_init(struct pvr_device *pvr_= dev) return 0; } =20 -static int pvr_device_reset_init(struct pvr_device *pvr_dev) -{ - struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); - struct reset_control *reset; - - reset =3D devm_reset_control_get_optional_exclusive(drm_dev->dev, NULL); - if (IS_ERR(reset)) - return dev_err_probe(drm_dev->dev, PTR_ERR(reset), - "failed to get gpu reset line\n"); - - pvr_dev->reset =3D reset; - - return 0; -} - /** * pvr_device_process_active_queues() - Process all queue related events. * @pvr_dev: PowerVR device to check @@ -618,6 +604,9 @@ pvr_device_init(struct pvr_device *pvr_dev) struct device *dev =3D drm_dev->dev; int err; =20 + /* Get the platform-specific data based on the compatible string. */ + pvr_dev->device_data =3D of_device_get_match_data(dev); + /* * Setup device parameters. We do this first in case other steps * depend on them. @@ -631,8 +620,7 @@ pvr_device_init(struct pvr_device *pvr_dev) if (err) return err; =20 - /* Get the reset line for the GPU */ - err =3D pvr_device_reset_init(pvr_dev); + err =3D pvr_dev->device_data->pwr_ops->init(pvr_dev); if (err) return err; =20 diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 7cb01c38d2a9c3fc71effe789d4dfe54eddd93ee..0c970255f90805a569d7d19e35e= c5f4ca7f02f7a 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -37,6 +37,9 @@ struct clk; /* Forward declaration from . */ struct firmware; =20 +/* Forward declaration from */ +struct pwrseq_desc; + /** * struct pvr_gpu_id - Hardware GPU ID information for a PowerVR device * @b: Branch ID. @@ -57,6 +60,14 @@ struct pvr_fw_version { u16 major, minor; }; =20 +/** + * struct pvr_device_data - Platform specific data associated with a compa= tible string. + * @pwr_ops: Pointer to a structure with platform-specific power functions. + */ +struct pvr_device_data { + const struct pvr_power_sequence_ops *pwr_ops; +}; + /** * struct pvr_device - powervr-specific wrapper for &struct drm_device */ @@ -98,6 +109,9 @@ struct pvr_device { /** @fw_version: Firmware version detected at runtime. */ struct pvr_fw_version fw_version; =20 + /** @device_data: Pointer to platform-specific data. */ + const struct pvr_device_data *device_data; + /** @regs_resource: Resource representing device control registers. */ struct resource *regs_resource; =20 @@ -148,6 +162,14 @@ struct pvr_device { */ struct reset_control *reset; =20 + /** + * @pwrseq: Pointer to a power sequencer, if one is used. + * + * Note: This member should only be accessed when + * IS_ENABLED(CONFIG_POWER_SEQUENCING) is true. + */ + struct pwrseq_desc *pwrseq; + /** @irq: IRQ number. */ int irq; =20 diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index b058ec183bb30ab5c3db17ebaadf2754520a2a1f..af830e565646daf19555197df49= 2438ef48d5e44 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1480,15 +1480,37 @@ static void pvr_remove(struct platform_device *plat= _dev) pvr_power_domains_fini(pvr_dev); } =20 +static const struct pvr_device_data pvr_device_data_manual =3D { + .pwr_ops =3D &pvr_power_sequence_ops_manual, +}; + +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) +static const struct pvr_device_data pvr_device_data_pwrseq =3D { + .pwr_ops =3D &pvr_power_sequence_ops_pwrseq, +}; +#endif + static const struct of_device_id dt_match[] =3D { - { .compatible =3D "img,img-rogue", .data =3D NULL }, +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) + { + .compatible =3D "thead,th1520-gpu", + .data =3D &pvr_device_data_pwrseq, + }, +#endif + { + .compatible =3D "img,img-rogue", + .data =3D &pvr_device_data_manual, + }, =20 /* * This legacy compatible string was introduced early on before the more = generic * "img,img-rogue" was added. Keep it around here for compatibility, but = never use * "img,img-axe" in new devicetrees. */ - { .compatible =3D "img,img-axe", .data =3D NULL }, + { + .compatible =3D "img,img-axe", + .data =3D &pvr_device_data_manual, + }, {} }; MODULE_DEVICE_TABLE(of, dt_match); @@ -1513,4 +1535,5 @@ MODULE_DESCRIPTION(PVR_DRIVER_DESC); MODULE_LICENSE("Dual MIT/GPL"); MODULE_IMPORT_NS("DMA_BUF"); MODULE_FIRMWARE("powervr/rogue_33.15.11.3_v1.fw"); +MODULE_FIRMWARE("powervr/rogue_36.52.104.182_v1.fw"); MODULE_FIRMWARE("powervr/rogue_36.53.104.796_v1.fw"); diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index 187a07e0bd9adb2f0713ac2c8e091229f4027354..58e0e812894de19c834e1dfca42= 7208b343eaa1c 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -18,6 +18,9 @@ #include #include #include +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) +#include +#endif #include #include #include @@ -234,6 +237,132 @@ pvr_watchdog_init(struct pvr_device *pvr_dev) return 0; } =20 +static int pvr_power_init_manual(struct pvr_device *pvr_dev) +{ + struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); + struct reset_control *reset; + + reset =3D devm_reset_control_get_optional_exclusive(drm_dev->dev, NULL); + if (IS_ERR(reset)) + return dev_err_probe(drm_dev->dev, PTR_ERR(reset), + "failed to get gpu reset line\n"); + + pvr_dev->reset =3D reset; + + return 0; +} + +static int pvr_power_on_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err =3D clk_prepare_enable(pvr_dev->core_clk); + if (err) + return err; + + err =3D clk_prepare_enable(pvr_dev->sys_clk); + if (err) + goto err_core_clk_disable; + + err =3D clk_prepare_enable(pvr_dev->mem_clk); + if (err) + goto err_sys_clk_disable; + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + err =3D reset_control_deassert(pvr_dev->reset); + if (err) + goto err_mem_clk_disable; + + return 0; + +err_mem_clk_disable: + clk_disable_unprepare(pvr_dev->mem_clk); + +err_sys_clk_disable: + clk_disable_unprepare(pvr_dev->sys_clk); + +err_core_clk_disable: + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + +static int pvr_power_off_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err =3D reset_control_assert(pvr_dev->reset); + + clk_disable_unprepare(pvr_dev->mem_clk); + clk_disable_unprepare(pvr_dev->sys_clk); + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + +const struct pvr_power_sequence_ops pvr_power_sequence_ops_manual =3D { + .init =3D pvr_power_init_manual, + .power_on =3D pvr_power_on_sequence_manual, + .power_off =3D pvr_power_off_sequence_manual, +}; + +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) +static int pvr_power_init_pwrseq(struct pvr_device *pvr_dev) +{ + struct device *dev =3D from_pvr_device(pvr_dev)->dev; + + pvr_dev->pwrseq =3D devm_pwrseq_get(dev, "gpu-power"); + if (IS_ERR(pvr_dev->pwrseq)) { + /* + * This platform requires a sequencer. If we can't get it, we + * must return the error (including -EPROBE_DEFER to wait for + * the provider to appear) + */ + return dev_err_probe(dev, PTR_ERR(pvr_dev->pwrseq), + "Failed to get required power sequencer\n"); + } + + return 0; +} + +static int pvr_power_on_sequence_pwrseq(struct pvr_device *pvr_dev) +{ + return pwrseq_power_on(pvr_dev->pwrseq); +} + +static int pvr_power_off_sequence_pwrseq(struct pvr_device *pvr_dev) +{ + return pwrseq_power_off(pvr_dev->pwrseq); +} + +const struct pvr_power_sequence_ops pvr_power_sequence_ops_pwrseq =3D { + .init =3D pvr_power_init_pwrseq, + .power_on =3D pvr_power_on_sequence_pwrseq, + .power_off =3D pvr_power_off_sequence_pwrseq, +}; +#else /* IS_ENABLED(CONFIG_POWER_SEQUENCING) */ +static int pvr_power_sequence_stub(struct pvr_device *pvr_dev) +{ + WARN_ONCE(1, "pwrseq support not enabled in kernel config\n"); + return -EOPNOTSUPP; +} + +const struct pvr_power_sequence_ops pvr_power_sequence_ops_pwrseq =3D { + .init =3D pvr_power_sequence_stub, + .power_on =3D pvr_power_sequence_stub, + .power_off =3D pvr_power_sequence_stub, +}; +#endif /* IS_ENABLED(CONFIG_POWER_SEQUENCING) */ + int pvr_power_device_suspend(struct device *dev) { @@ -252,11 +381,7 @@ pvr_power_device_suspend(struct device *dev) goto err_drm_dev_exit; } =20 - clk_disable_unprepare(pvr_dev->mem_clk); - clk_disable_unprepare(pvr_dev->sys_clk); - clk_disable_unprepare(pvr_dev->core_clk); - - err =3D reset_control_assert(pvr_dev->reset); + err =3D pvr_dev->device_data->pwr_ops->power_off(pvr_dev); =20 err_drm_dev_exit: drm_dev_exit(idx); @@ -276,53 +401,22 @@ pvr_power_device_resume(struct device *dev) if (!drm_dev_enter(drm_dev, &idx)) return -EIO; =20 - err =3D clk_prepare_enable(pvr_dev->core_clk); + err =3D pvr_dev->device_data->pwr_ops->power_on(pvr_dev); if (err) goto err_drm_dev_exit; =20 - err =3D clk_prepare_enable(pvr_dev->sys_clk); - if (err) - goto err_core_clk_disable; - - err =3D clk_prepare_enable(pvr_dev->mem_clk); - if (err) - goto err_sys_clk_disable; - - /* - * According to the hardware manual, a delay of at least 32 clock - * cycles is required between de-asserting the clkgen reset and - * de-asserting the GPU reset. Assuming a worst-case scenario with - * a very high GPU clock frequency, a delay of 1 microsecond is - * sufficient to ensure this requirement is met across all - * feasible GPU clock speeds. - */ - udelay(1); - - err =3D reset_control_deassert(pvr_dev->reset); - if (err) - goto err_mem_clk_disable; - if (pvr_dev->fw_dev.booted) { err =3D pvr_power_fw_enable(pvr_dev); if (err) - goto err_reset_assert; + goto err_power_off; } =20 drm_dev_exit(idx); =20 return 0; =20 -err_reset_assert: - reset_control_assert(pvr_dev->reset); - -err_mem_clk_disable: - clk_disable_unprepare(pvr_dev->mem_clk); - -err_sys_clk_disable: - clk_disable_unprepare(pvr_dev->sys_clk); - -err_core_clk_disable: - clk_disable_unprepare(pvr_dev->core_clk); +err_power_off: + pvr_dev->device_data->pwr_ops->power_off(pvr_dev); =20 err_drm_dev_exit: drm_dev_exit(idx); diff --git a/drivers/gpu/drm/imagination/pvr_power.h b/drivers/gpu/drm/imag= ination/pvr_power.h index ada85674a7ca762dcf92df40424230e1c3910342..b853d092242cc90cb98cf661006= 79a309055a1dc 100644 --- a/drivers/gpu/drm/imagination/pvr_power.h +++ b/drivers/gpu/drm/imagination/pvr_power.h @@ -41,4 +41,19 @@ pvr_power_put(struct pvr_device *pvr_dev) int pvr_power_domains_init(struct pvr_device *pvr_dev); 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Mon, 4 Aug 2025 23:25:13 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250804232512eusmtip297551e7beaa82db199120ff132a6625d~Ys-Nl6uvT0793707937eusmtip2Q; Mon, 4 Aug 2025 23:25:12 +0000 (GMT) From: Michal Wilczynski Date: Tue, 05 Aug 2025 01:25:02 +0200 Subject: [PATCH v11 2/4] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250805-apr_14_for_sending-v11-2-b7eecefcfdc0@samsung.com> In-Reply-To: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250804232513eucas1p18bfc7473db5b8269fbc905f2dedd31a0 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250804232513eucas1p18bfc7473db5b8269fbc905f2dedd31a0 X-EPHeader: CA X-CMS-RootMailID: 20250804232513eucas1p18bfc7473db5b8269fbc905f2dedd31a0 References: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> Rework the PowerVR Rogue GPU binding to use an explicit, per variant style for defining power domain properties and add support for the T-HEAD TH1520 SoC's GPU. To improve clarity and precision, the binding is refactored so that power domain items are listed explicitly for each variant [1]. The previous method relied on an implicit, positional mapping between the `power-domains` and `power-domain-names` properties. This change replaces the generic rules with self contained if/then blocks for each GPU variant, making the relationship between power domains and their names explicit and unambiguous. The generic if block for img,img-rogue, which previously required power-domains and power-domain-names for all variants, is removed. Instead, each specific GPU variant now defines its own power domain requirements within a self-contained if/then block, making the schema more explicit. This new structure is then used to add support for the `thead,th1520-gpu`. While its BXM-4-64 IP has two conceptual power domains, the TH1520 SoC integrates them behind a single power gate. The new binding models this with a specific rule that enforces a single `power-domains` entry and disallows the `power-domain-names` property. Link: https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@lina= ro.org/ [1] Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michal Wilczynski --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 37 +++++++++++++++++-= ---- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..c87d7bece0ecd6331fc7d1a479b= bdaf68bac6e6d 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -21,6 +21,11 @@ properties: # work with newer dts. - const: img,img-axe - const: img,img-rogue + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue - items: - enum: - ti,j721s2-gpu @@ -77,14 +82,18 @@ required: additionalProperties: false =20 allOf: - # Constraints added alongside the new compatible strings that would othe= rwise - # create an ABI break. - if: properties: compatible: contains: - const: img,img-rogue + const: img,img-axe-1-16m then: + properties: + power-domains: + items: + - description: Power domain A + power-domain-names: + maxItems: 1 required: - power-domains - power-domain-names @@ -93,13 +102,20 @@ allOf: properties: compatible: contains: - const: img,img-axe-1-16m + const: thead,th1520-gpu then: properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 power-domains: - maxItems: 1 - power-domain-names: - maxItems: 1 + items: + - description: The single, unified power domain for the GPU on= the + TH1520 SoC, integrating all internal IP power domains. + power-domain-names: false + required: + - power-domains =20 - if: properties: @@ -109,9 +125,14 @@ allOf: then: properties: power-domains: - minItems: 2 + items: + - description: Power domain A + - description: Power domain B power-domain-names: minItems: 2 + required: + - power-domains + - power-domain-names =20 - if: properties: --=20 2.34.1 From nobody Sun Oct 5 12:36:01 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DAC291C34 for ; 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Mon, 4 Aug 2025 23:25:15 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250804232513eusmtip2099a05f69aac35b12b1c3b39f738ccad~Ys-OqHXu90897408974eusmtip2O; Mon, 4 Aug 2025 23:25:13 +0000 (GMT) From: Michal Wilczynski Date: Tue, 05 Aug 2025 01:25:03 +0200 Subject: [PATCH v11 3/4] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250805-apr_14_for_sending-v11-3-b7eecefcfdc0@samsung.com> In-Reply-To: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250804232515eucas1p26edd0d7e64497af4ea5af20bc513de00 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250804232515eucas1p26edd0d7e64497af4ea5af20bc513de00 X-EPHeader: CA X-CMS-RootMailID: 20250804232515eucas1p26edd0d7e64497af4ea5af20bc513de00 References: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be controlled programatically. Reviewed-by: Ulf Hansson Reviewed-by: Drew Fustini Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 42724bf7e90e08fac326c464d0f080e3bd2cd59b..6ae5c632205ba63248c0a119c03= bdfc084aac7a0 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 { #clock-cells =3D <0>; }; =20 + gpu_mem_clk: mem-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + clock-output-names =3D "gpu_mem_clk"; + #clock-cells =3D <0>; + }; + stmmac_axi_config: stmmac-axi-config { snps,wr_osr_lmt =3D <15>; snps,rd_osr_lmt =3D <15>; @@ -500,6 +507,20 @@ clk: clock-controller@ffef010000 { #clock-cells =3D <1>; }; =20 + gpu: gpu@ffef400000 { + compatible =3D "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; 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Mon, 4 Aug 2025 23:25:15 +0000 (GMT) From: Michal Wilczynski Date: Tue, 05 Aug 2025 01:25:04 +0200 Subject: [PATCH v11 4/4] drm/imagination: Enable PowerVR driver for RISC-V Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250805-apr_14_for_sending-v11-4-b7eecefcfdc0@samsung.com> In-Reply-To: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250804232516eucas1p1c50313f830f44571e409fba8c5d5fe79 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250804232516eucas1p1c50313f830f44571e409fba8c5d5fe79 X-EPHeader: CA X-CMS-RootMailID: 20250804232516eucas1p1c50313f830f44571e409fba8c5d5fe79 References: <20250805-apr_14_for_sending-v11-0-b7eecefcfdc0@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. The RISC-V support is restricted to 64-bit systems (RISCV && 64BIT) as the driver currently has an implicit dependency on a 64-bit platform. Add a dependency on MMU to fix a build warning on RISC-V configurations without an MMU. Reviewed-by: Ulf Hansson Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imaginat= ion/Kconfig index 3bfa2ac212dccb73c53bdc2bc259bcba636e7cfc..682dd2633d0c012df18d0f7144d= 029b67a14d241 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,8 +3,9 @@ =20 config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Gra= phics" - depends on ARM64 + depends on (ARM64 || RISCV && 64BIT) depends on DRM + depends on MMU depends on PM select DRM_EXEC select DRM_GEM_SHMEM_HELPER --=20 2.34.1