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[2001:b011:7005:5e00:dd65:4c2e:14df:36e2]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-241e899adc3sm113990615ad.118.2025.08.04.09.03.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Aug 2025 09:03:47 -0700 (PDT) From: Haru Zheng To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Markus Schneider-Pargmann , CK Hu , Guillaume Ranquet Cc: Bo-Chen Chen , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Haru Zheng Subject: [PATCH v2] drm/mediatek: dp: Fix suspend/resume training failure Date: Tue, 5 Aug 2025 00:03:36 +0800 Message-Id: <20250804160336.7615-1-towwy321@gmail.com> X-Mailer: git-send-email 2.23.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When suspending and resuming DisplayPort via Type-C, link training will be fail. This patch backports the software IRQ handling for DP, as eDP uses hardware IRQ while DP uses software IRQ. Additionally, cable_plugged_in is flipped in mtk_dp_hpd_event to ensure correct hotplug detection during resume. These changes fix the DP training failure after suspend/resume. Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver") Signed-off-by: Haru Zheng --- Changes since v1: - Fixed indentation to use tabs - Simplified swirq_enable() logic with ternary - Removed unnecessary memset() - Replaced dev_info() with dev_dbg() - Add mtk_dp_bridge_hpd_notify() declaration to struct drm_bridge_funcs mtk= _dp_bridge_funcs - Removed IRQ enable from probe() to avoid enabling IRQ for eDP - Corrected HW/SW IRQ logic: * eDP uses hardware IRQ, DP uses software IRQ * Previously some logic was reversed causing issues - Fixed hotplug detection logic in mtk_dp_hpd_event: * cable_plugged_in flag inverted to ensure correct detection on resume Code flow: - On suspend, DP disables training and IRQs accordingly. - On resume, IRQs for DP are re-enabled via software IRQ handler. - HPD events are processed with correct plug/unplug state, ensuring trainin= g succeeds. --- drivers/gpu/drm/mediatek/mtk_dp.c | 94 ++++++++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 3 + 2 files changed, 87 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c index bef6eeb30d3e..b0f96c7c279e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1012,6 +1012,12 @@ static u32 mtk_dp_swirq_get_clear(struct mtk_dp *mtk= _dp) return irq_status; } =20 +static void mtk_dp_swirq_enable(struct mtk_dp *mtk_dp, bool enable) +{ + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C4, enable ? 0 : 0xFFFF, + SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK); +} + static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp) { u32 irq_status =3D (mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3418) & @@ -2031,8 +2037,8 @@ static irqreturn_t mtk_dp_hpd_event(int hpd, void *de= v) spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags); =20 if (cable_sta_chg) { - if (!!(mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414) & - HPD_DB_DP_TRANS_P0_MASK)) + if (!(mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414) & + HPD_DB_DP_TRANS_P0_MASK)) mtk_dp->train_info.cable_plugged_in =3D true; else mtk_dp->train_info.cable_plugged_in =3D false; @@ -2252,7 +2258,7 @@ static ssize_t mtk_dp_aux_transfer(struct drm_dp_aux = *mtk_aux, to_access, &msg->reply); =20 if (ret) { - dev_info(mtk_dp->dev, + dev_dbg(mtk_dp->dev, "Failed to do AUX transfer: %d\n", ret); goto err; } @@ -2265,6 +2271,35 @@ static ssize_t mtk_dp_aux_transfer(struct drm_dp_aux= *mtk_aux, return ret; } =20 +static void mtk_dp_swirq_hpd(struct mtk_dp *mtk_dp, u8 conn) +{ + u32 data; + + data =3D mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414); + + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3414, + HPD_OVR_EN_DP_TRANS_P0_MASK, + HPD_OVR_EN_DP_TRANS_P0_MASK); + + if (conn) + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3414, + HPD_SET_DP_TRANS_P0_MASK, + HPD_SET_DP_TRANS_P0_MASK); + else + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3414, + 0, + HPD_SET_DP_TRANS_P0_MASK); +} + +static void mtk_dp_swirq_hpd_interrupt_set(struct mtk_dp *mtk_dp, u8 statu= s) +{ + dev_dbg(mtk_dp->dev, "[DPTX] status:%d [2:DISCONNECT, 4:CONNECT]\n", stat= us); + + mtk_dp_swirq_hpd(mtk_dp, status =3D=3D MTK_DP_HPD_CONNECT ? TRUE : FALSE); + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C0, status, + SW_IRQ_SET_DP_TRANS_P0_MASK); +} + static int mtk_dp_poweron(struct mtk_dp *mtk_dp) { int ret; @@ -2326,7 +2361,13 @@ static int mtk_dp_bridge_attach(struct drm_bridge *b= ridge, if (mtk_dp->bridge.type !=3D DRM_MODE_CONNECTOR_eDP) { irq_clear_status_flags(mtk_dp->irq, IRQ_NOAUTOEN); enable_irq(mtk_dp->irq); + /* eDP does use HW IRQs */ mtk_dp_hwirq_enable(mtk_dp, true); + mtk_dp_swirq_enable(mtk_dp, false); + } else { + /* DP does use SW IRQs */ + mtk_dp_hwirq_enable(mtk_dp, false); + mtk_dp_swirq_enable(mtk_dp, true); } =20 return 0; @@ -2534,7 +2575,7 @@ static int mtk_dp_bridge_atomic_check(struct drm_brid= ge *bridge, =20 dev_dbg(mtk_dp->dev, "input format 0x%04x, output format 0x%04x\n", bridge_state->input_bus_cfg.format, - bridge_state->output_bus_cfg.format); + bridge_state->output_bus_cfg.format); =20 if (input_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) mtk_dp->info.format =3D DP_PIXELFORMAT_YUV422; @@ -2552,6 +2593,30 @@ static int mtk_dp_bridge_atomic_check(struct drm_bri= dge *bridge, return 0; } =20 +static void mtk_dp_bridge_hpd_notify(struct drm_bridge *bridge, + enum drm_connector_status status) +{ + struct mtk_dp *mtk_dp =3D mtk_dp_from_bridge(bridge); + struct mtk_dp_train_info *train_info =3D &mtk_dp->train_info; + + if (mtk_dp->bridge.type !=3D DRM_MODE_CONNECTOR_eDP) { + if (mtk_dp->hpd_state !=3D status) { + if (status =3D=3D connector_status_disconnected) { + train_info->cable_plugged_in =3D false; + } else { + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3414, + HPD_OVR_EN_DP_TRANS_P0_MASK, + HPD_OVR_EN_DP_TRANS_P0_MASK); + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3414, + HPD_SET_DP_TRANS_P0_MASK, + HPD_SET_DP_TRANS_P0_MASK); + train_info->cable_plugged_in =3D true; + } + mtk_dp->hpd_state =3D status; + } + } +} + static const struct drm_bridge_funcs mtk_dp_bridge_funcs =3D { .atomic_check =3D mtk_dp_bridge_atomic_check, .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, @@ -2566,6 +2631,7 @@ static const struct drm_bridge_funcs mtk_dp_bridge_fu= ncs =3D { .mode_valid =3D mtk_dp_bridge_mode_valid, .edid_read =3D mtk_dp_edid_read, .detect =3D mtk_dp_bdg_detect, + .hpd_notify =3D mtk_dp_bridge_hpd_notify, }; =20 static void mtk_dp_debounce_timer(struct timer_list *t) @@ -2800,9 +2866,6 @@ static int mtk_dp_probe(struct platform_device *pdev) mtk_dp_initialize_aux_settings(mtk_dp); mtk_dp_power_enable(mtk_dp); =20 - /* Disable HW interrupts: we don't need any for eDP */ - mtk_dp_hwirq_enable(mtk_dp, false); - /* * Power on the AUX to allow reading the EDID from aux-bus: * please note that it is necessary to call power off in the @@ -2861,10 +2924,15 @@ static int mtk_dp_suspend(struct device *dev) struct mtk_dp *mtk_dp =3D dev_get_drvdata(dev); =20 mtk_dp_power_disable(mtk_dp); - if (mtk_dp->bridge.type !=3D DRM_MODE_CONNECTOR_eDP) + + if (mtk_dp->bridge.type =3D=3D DRM_MODE_CONNECTOR_eDP) { mtk_dp_hwirq_enable(mtk_dp, false); - pm_runtime_put_sync(dev); + } else { + mtk_dp_swirq_hpd_interrupt_set(mtk_dp, MTK_DP_HPD_DISCONNECT); + mtk_dp_swirq_enable(mtk_dp, false); + } =20 + pm_runtime_put_sync(dev); return 0; } =20 @@ -2874,8 +2942,14 @@ static int mtk_dp_resume(struct device *dev) =20 pm_runtime_get_sync(dev); mtk_dp_init_port(mtk_dp); - if (mtk_dp->bridge.type !=3D DRM_MODE_CONNECTOR_eDP) + + if (mtk_dp->bridge.type =3D=3D DRM_MODE_CONNECTOR_eDP) { mtk_dp_hwirq_enable(mtk_dp, true); + } else { + mtk_dp_swirq_hpd_interrupt_set(mtk_dp, MTK_DP_HPD_CONNECT); + mtk_dp_swirq_enable(mtk_dp, true); + } + mtk_dp_power_enable(mtk_dp); =20 return 0; diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediat= ek/mtk_dp_reg.h index 8ad7a9cc259e..7c97e230be50 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -286,7 +286,10 @@ #define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK BIT(9) #define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK BIT(10) #define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK BIT(11) +#define MTK_DP_TRANS_P0_35C0 0x35c0 +#define MTK_DP_TRANS_P0_35C4 0x35c4 #define MTK_DP_TRANS_P0_35C8 0x35c8 +#define SW_IRQ_SET_DP_TRANS_P0_MASK GENMASK(15, 0) #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0) #define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0) #define MTK_DP_TRANS_P0_35D0 0x35d0 --=20 2.23.0