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charset="utf-8" From: Sricharan Ramabadhran The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran [ Added interconnect related changes ] Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski --- v5: Remove previous maintainers Change clock@fa80000 to clock-controller@fa80000 in example Have one item per line for clocks and clock-names in example v4: Add self to 'maintainers' s/gpll0/clk_ref/ in clock-names s/apss-clock/clock/ in example's node name v2: Add #interconnect-cells to help enable L3 pll as ICC clock Add master/slave ids --- .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 63 +++++++++++++++++++ include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++ .../dt-bindings/interconnect/qcom,ipq5424.h | 3 + 3 files changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-ap= ss-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.= yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml new file mode 100644 index 000000000000..0154016075de --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APSS IPQ5424 Clock Controller + +maintainers: + - Varadarajan Narayanan + +description: + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. + The RCG and PLL have a separate register space from the GCC. + +properties: + compatible: + enum: + - qcom,ipq5424-apss-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference to the XO clock. + - description: Reference to the GPLL0 clock. + + clock-names: + items: + - const: xo + - const: clk_ref + + '#clock-cells': + const: 1 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include + + apss_clk: clock-controller@fa80000 { + compatible =3D "qcom,ipq5424-apss-clk"; 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charset="utf-8" From: Sricharan Ramabadhran CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. Add support for the APSS PLL, RCG and clock enable for ipq5424. The PLL, RCG register space are clubbed. Hence adding new APSS driver for both PLL and RCG/CBC control. Also the L3 cache has a separate pll and needs to be scaled along with the CPU and is modeled as an ICC clock. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran [ Removed clock notifier, moved L3 pll to icc-clk, used existing alpha pll structure ] Signed-off-by: Varadarajan Narayanan --- v5: Use enums instead of clock names in clock struct Add 'sync_state =3D icc_sync_state' v4: s/gpll0/clk_ref/g v3: Use the qcom_cc_driver_data framework to trim down apss_ipq5424_probe Rearrange structures to use in other structures v2: Model L3 pll as ICC clock and add relevant structures Use CLK_ALPHA_PLL_TYPE_HUAYRA_2290 register offsets instead of duplicate ipq5424_pll_offsets definition. Inline clock rates. Fix MODULE_LICENSE --- drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq5424.c | 267 ++++++++++++++++++++++++++++++++ 3 files changed, 275 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq5424.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6cb6cd3e1778..dae89599a40e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -208,6 +208,13 @@ config IPQ_CMN_PLL Say Y or M if you want to support CMN PLL clock on the IPQ based devices. =20 +config IPQ_APSS_5424 + tristate "IPQ APSS Clock Controller" + help + Support for APSS Clock controller on Qualcom IPQ5424 platform. + Say Y if you want to support CPU frequency scaling on ipq based + devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ddb7e06fae40..98de55eb6402 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) +=3D tcsrcc-x1e80100.o obj-$(CONFIG_CLK_X1P42100_GPUCC) +=3D gpucc-x1p42100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) +=3D gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) +=3D apss-ipq-pll.o +obj-$(CONFIG_IPQ_APSS_5424) +=3D apss-ipq5424.o obj-$(CONFIG_IPQ_APSS_6018) +=3D apss-ipq6018.o obj-$(CONFIG_IPQ_CMN_PLL) +=3D ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) +=3D gcc-ipq4019.o diff --git a/drivers/clk/qcom/apss-ipq5424.c b/drivers/clk/qcom/apss-ipq542= 4.c new file mode 100644 index 000000000000..e5674a884f46 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq5424.c @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" + +enum { + DT_XO, + DT_CLK_REF, +}; + +enum { + P_XO, + P_GPLL0, + P_APSS_PLL_EARLY, + P_L3_PLL, +}; + +struct apss_clk { + struct notifier_block cpu_clk_notifier; + struct clk_hw *hw; + struct device *dev; + struct clk *l3_clk; +}; + +static const struct alpha_pll_config apss_pll_config =3D { + .l =3D 0x3b, + .config_ctl_val =3D 0x08200920, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x04000000, + .user_ctl_val =3D 0xf, +}; + +static struct clk_alpha_pll ipq5424_apss_pll =3D { + .offset =3D 0x0, + .config =3D &apss_pll_config, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "apss_pll", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_XO, + }, + .parent_names =3D (const char *[]){ "xo-board-clk"}, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct clk_parent_data parents_apss_silver_clk_src[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_CLK_REF }, + { .hw =3D &ipq5424_apss_pll.clkr.hw }, +}; + +static const struct parent_map parents_apss_silver_clk_src_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +static const struct freq_tbl ftbl_apss_clk_src[] =3D { + F(816000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1416000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1800000000, P_APSS_PLL_EARLY, 1, 0, 0), + { } +}; + +static struct clk_rcg2 apss_silver_clk_src =3D { + .cmd_rcgr =3D 0x0080, + .freq_tbl =3D ftbl_apss_clk_src, + .hid_width =3D 5, + .parent_map =3D parents_apss_silver_clk_src_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "apss_silver_clk_src", + .parent_data =3D parents_apss_silver_clk_src, + .num_parents =3D ARRAY_SIZE(parents_apss_silver_clk_src), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch apss_silver_core_clk =3D { + .halt_reg =3D 0x008c, + .clkr =3D { + .enable_reg =3D 0x008c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "apss_silver_core_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &apss_silver_clk_src.clkr.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static const struct alpha_pll_config l3_pll_config =3D { + .l =3D 0x29, + .config_ctl_val =3D 0x08200920, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x04000000, + .user_ctl_val =3D 0xf, +}; + +static struct clk_alpha_pll ipq5424_l3_pll =3D { + .offset =3D 0x10000, + .config =3D &l3_pll_config, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "l3_pll", + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xo-board-clk", + }, + .parent_names =3D (const char *[]){ "xo-board-clk"}, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct clk_parent_data parents_l3_clk_src[] =3D { + { .fw_name =3D "xo-board-clk" }, + { .fw_name =3D "clk_ref" }, + { .hw =3D &ipq5424_l3_pll.clkr.hw }, +}; + +static const struct parent_map parents_l3_clk_src_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_L3_PLL, 5 }, +}; + +static const struct freq_tbl ftbl_l3_clk_src[] =3D { + F(816000000, P_L3_PLL, 1, 0, 0), + F(984000000, P_L3_PLL, 1, 0, 0), + F(1272000000, P_L3_PLL, 1, 0, 0), + { } +}; + +static struct clk_rcg2 l3_clk_src =3D { + .cmd_rcgr =3D 0x10080, + .freq_tbl =3D ftbl_l3_clk_src, + .hid_width =3D 5, + .parent_map =3D parents_l3_clk_src_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "l3_clk_src", + .parent_data =3D parents_l3_clk_src, + .num_parents =3D ARRAY_SIZE(parents_l3_clk_src), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch l3_core_clk =3D { + .halt_reg =3D 0x1008c, + .clkr =3D { + .enable_reg =3D 0x1008c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "l3_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &l3_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static const struct regmap_config apss_ipq5424_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x20000, + .fast_io =3D true, +}; + +static struct clk_regmap *apss_ipq5424_clks[] =3D { + [APSS_PLL_EARLY] =3D &ipq5424_apss_pll.clkr, + [APSS_SILVER_CLK_SRC] =3D &apss_silver_clk_src.clkr, + [APSS_SILVER_CORE_CLK] =3D &apss_silver_core_clk.clkr, + [L3_PLL] =3D &ipq5424_l3_pll.clkr, + [L3_CLK_SRC] =3D &l3_clk_src.clkr, + [L3_CORE_CLK] =3D &l3_core_clk.clkr, + +}; + +static struct clk_alpha_pll *ipa5424_apss_plls[] =3D { + &ipq5424_l3_pll, + &ipq5424_apss_pll, +}; + +static struct qcom_cc_driver_data ipa5424_apss_driver_data =3D { + .alpha_plls =3D ipa5424_apss_plls, + .num_alpha_plls =3D ARRAY_SIZE(ipa5424_apss_plls), +}; + +#define IPQ_APPS_PLL_ID (5424 * 3) /* some unique value */ + +static const struct qcom_icc_hws_data icc_ipq5424_cpu_l3[] =3D { + { MASTER_CPU, SLAVE_L3, L3_CORE_CLK }, +}; + +static const struct qcom_cc_desc apss_ipq5424_desc =3D { + .config =3D &apss_ipq5424_regmap_config, + .clks =3D apss_ipq5424_clks, + .num_clks =3D ARRAY_SIZE(apss_ipq5424_clks), + .icc_hws =3D icc_ipq5424_cpu_l3, + .num_icc_hws =3D ARRAY_SIZE(icc_ipq5424_cpu_l3), + .icc_first_node_id =3D IPQ_APPS_PLL_ID, + .driver_data =3D &ipa5424_apss_driver_data, +}; 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charset="utf-8" From: Md Sadre Alam IPQ5424 have different OPPs available for the CPU based on SoC variant. This can be determined through use of an eFuse register present in the silicon. Added support for ipq5424 on nvmem driver which helps to determine OPPs at runtime based on the eFuse register which has the CPU frequency limits. opp-supported-hw dt binding can be used to indicate the available OPPs for each limit. nvmem driver also creates the "cpufreq-dt" platform_device after passing the version matching data to the OPP framework so that the cpufreq-dt handles the actual cpufreq implementation. Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran Acked-by: Viresh Kumar Reviewed-by: Konrad Dybcio [ Changed '!=3D' based check to '=3D=3D' based check ] Signed-off-by: Varadarajan Narayanan --- v5: Add 'Acked-by: Viresh Kumar' --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index 015dd393eaba..de1769649368 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -191,6 +191,7 @@ static const struct of_device_id blocklist[] __initcons= t =3D { { .compatible =3D "ti,am62p5", }, =20 { .compatible =3D "qcom,ipq5332", }, + { .compatible =3D "qcom,ipq5424", }, { .compatible =3D "qcom,ipq6018", }, { .compatible =3D "qcom,ipq8064", }, { .compatible =3D "qcom,ipq8074", }, diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cp= ufreq-nvmem.c index 54f8117103c8..765a5bb81829 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -200,6 +200,10 @@ static int qcom_cpufreq_kryo_name_version(struct devic= e *cpu_dev, case QCOM_ID_IPQ9574: drv->versions =3D 1 << (unsigned int)(*speedbin); break; + case QCOM_ID_IPQ5424: + case QCOM_ID_IPQ5404: + drv->versions =3D (*speedbin =3D=3D 0x3b) ? BIT(1) : BIT(0); + break; case QCOM_ID_MSM8996SG: case QCOM_ID_APQ8096SG: drv->versions =3D 1 << ((unsigned int)(*speedbin) + 4); @@ -591,6 +595,7 @@ static const struct of_device_id qcom_cpufreq_match_lis= t[] __initconst __maybe_u { .compatible =3D "qcom,msm8996", .data =3D &match_data_kryo }, { .compatible =3D "qcom,qcs404", .data =3D &match_data_qcs404 }, { .compatible =3D "qcom,ipq5332", .data =3D &match_data_kryo }, + { .compatible =3D "qcom,ipq5424", .data =3D &match_data_kryo }, { .compatible =3D "qcom,ipq6018", .data =3D &match_data_ipq6018 }, { .compatible =3D "qcom,ipq8064", .data =3D &match_data_ipq8064 }, { .compatible =3D "qcom,ipq8074", .data =3D &match_data_ipq8074 }, --=20 2.34.1 From nobody Sun Oct 5 12:52:25 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AAA02580DE; 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charset="utf-8" From: Sricharan Ramabadhran Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for CPU clock scaling. Signed-off-by: Sricharan Ramabadhran [ Added interconnect related entries, fix dt-bindings errors ] Signed-off-by: Varadarajan Narayanan --- v5: Add opp-816000000 Have one item per line for clocks and clock-names v4: s/gpll0/clk_ref/ in clock-names s/apss-clock/clock/ in node name v3: Remove L3_CORE_CLK from cpu node as it comes through icc-clk v2: Add 'interconnects' to cpu nodes Add 'opp-peak-kBps' to opp table Add '#interconnect-cells' to apss_clk Remove unnecessary comment Fix dt-binding-errors in qfprom node --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 71 +++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 2eea8a078595..0bc46734e8b4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -52,6 +53,11 @@ cpu0: cpu@0 { reg =3D <0x0>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -72,6 +78,10 @@ cpu1: cpu@100 { enable-method =3D "psci"; reg =3D <0x100>; next-level-cache =3D <&l2_100>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -87,6 +97,10 @@ cpu2: cpu@200 { enable-method =3D "psci"; reg =3D <0x200>; next-level-cache =3D <&l2_200>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -102,6 +116,10 @@ cpu3: cpu@300 { enable-method =3D "psci"; reg =3D <0x300>; next-level-cache =3D <&l2_300>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -119,6 +137,36 @@ scm { }; }; =20 + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells =3D <&cpu_speed_bin>; + + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-microvolt =3D <1>; + opp-supported-hw =3D <0x3>; + clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <1>; + opp-supported-hw =3D <0x3>; + clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <984000>; + }; + + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <2>; + opp-supported-hw =3D <0x1>; + clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1272000>; + }; + }; + memory@80000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -388,6 +436,18 @@ system-cache-controller@800000 { interrupts =3D ; }; =20 + qfprom@a6000 { + compatible =3D "qcom,ipq5424-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x000a6000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_speed_bin: cpu-speed-bin@234 { + reg =3D <0x234 0x1>; + bits =3D <0 8>; + }; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5424-tlmm"; reg =3D <0 0x01000000 0 0x300000>; @@ -730,6 +790,17 @@ frame@f42d000 { }; }; =20 + apss_clk: clock-controller@fa80000 { + compatible =3D "qcom,ipq5424-apss-clk"; + reg =3D <0x0 0x0fa80000 0x0 0x20000>; + clocks =3D <&xo_board>, + <&gcc GPLL0>; + clock-names =3D "xo", + "clk_ref"; + #clock-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + pcie3: pcie@40000000 { compatible =3D "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg =3D <0x0 0x40000000 0x0 0xf1c>, --=20 2.34.1