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Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index d08d773b1cc5..2e20a7532c03 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -32,6 +32,42 @@ cpu0: cpu@0 { device_type =3D "cpu"; clocks =3D <&pmc PMC_TYPE_CORE PMC_CPUPLL>; clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-90000000 { + opp-hz =3D /bits/ 64 <90000000>; + opp-microvolt =3D <1050000 1050000 1225000>; + clock-latency-ns =3D <320000>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + opp-microvolt =3D <1050000 1050000 1225000>; + clock-latency-ns =3D <320000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <1050000 1050000 1225000>; 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Mon, 4 Aug 2025 03:02:41 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:02:35 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 02/15] nvmem: microchip-otpc: rework to access packets based on tag Date: Mon, 4 Aug 2025 15:32:06 +0530 Message-ID: <20250804100219.63325-3-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework the driver to change the packet access technique based on the TAG instead of the currently in use "id". Since there is no way of knowing the OTP memory mapping in advance or the changes it can go through with time, the id based approach is not reliable. Accessing the packets based on the associated tags is a fail-proof approach. This method is aided by adding a table of contents to store the payload information which makes it easier to traverse through the OTP memory and read the data of the intended packet. The stride of the nvmem device is adjusted to 1 to support the TAG being treated as an offset. The only reliable way to recognize a packet without being aware of the flashed contents of the OTP memory is the TAG of the packet. Signed-off-by: Varshini Rajendran --- drivers/nvmem/microchip-otpc.c | 130 +++++++++++++++++++++++++-------- 1 file changed, 101 insertions(+), 29 deletions(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index df979e8549fd..e922c882af72 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -18,16 +18,27 @@ #define MCHP_OTPC_CR_READ BIT(6) #define MCHP_OTPC_MR (0x4) #define MCHP_OTPC_MR_ADDR GENMASK(31, 16) +#define MCHP_OTPC_MR_EMUL BIT(7) #define MCHP_OTPC_AR (0x8) #define MCHP_OTPC_SR (0xc) #define MCHP_OTPC_SR_READ BIT(6) #define MCHP_OTPC_HR (0x20) #define MCHP_OTPC_HR_SIZE GENMASK(15, 8) +#define MCHP_OTPC_HR_PACKET_TYPE GENMASK(2, 0) #define MCHP_OTPC_DR (0x24) =20 #define MCHP_OTPC_NAME "mchp-otpc" #define MCHP_OTPC_SIZE (11 * 1024) =20 +enum packet_type { + PACKET_TYPE_REGULAR =3D 1, + PACKET_TYPE_KEY =3D 2, + PACKET_TYPE_BOOT_CONFIG =3D 3, + PACKET_TYPE_SECURE_BOOT_CONFIG =3D 4, + PACKET_TYPE_HARDWARE_CONFIG =3D 5, + PACKET_TYPE_CUSTOM =3D 6, +}; + /** * struct mchp_otpc - OTPC private data structure * @base: base address @@ -42,6 +53,25 @@ struct mchp_otpc { u32 npackets; }; =20 +/** + * struct mchp_otpc_payload_info - OTP packet's payload information + * retrieved from the packet's header + * @id: driver assigned packet ID + * @packet_offset: offset address of the packet to be written in the + * register OTPC_MR.ADDR to access the packet + * @payload_length: length of the packet's payload + * @packet_type: type of the packet + * @packet_tag: TAG corresponding to the packet. Applicable for most + * of the regular packets + */ +struct mchp_otpc_payload_info { + u32 id; + u32 packet_offset; + u32 payload_length; + u32 packet_type; + u32 packet_tag; +}; + /** * struct mchp_otpc_packet - OTPC packet data structure * @list: list head @@ -50,20 +80,16 @@ struct mchp_otpc { */ struct mchp_otpc_packet { struct list_head list; - u32 id; - u32 offset; + struct mchp_otpc_payload_info payload_info; }; =20 -static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *o= tpc, - u32 id) +static struct mchp_otpc_packet *mchp_otpc_tag_to_packet(struct mchp_otpc *= otpc, + u32 tag) { struct mchp_otpc_packet *packet; =20 - if (id >=3D otpc->npackets) - return NULL; - list_for_each_entry(packet, &otpc->packets, list) { - if (packet->id =3D=3D id) + if (packet->payload_info.packet_tag =3D=3D tag) return packet; } =20 @@ -140,8 +166,27 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *ot= pc, * offset returned by hardware. * * For this, the read function will return the first requested bytes in the - * packet. The user will have to be aware of the memory footprint before d= oing - * the read request. + * packet. The user won't have to be aware of the memory footprint before = doing + * the read request since it is abstracted and taken care by this driver. + * + * There is no way of knowing the Mapping of the OTP memory table in advan= ce. In + * this read function the offset requested is treated as the identifier st= ring + * i.e., Packet TAG, to acquire the payload with reliability. The packet T= ag + * is the only way to recognize a packet without being aware of the flashed + * OTP memory map table. + */ + +/** + * mchp_otpc_read() - Read the OTP packets and fill the buffer based on th= e TAG + * of the packet treated as the offset. + * @priv: Pointer to device structure. + * @off: offset of the OTP packet to be read. In this case, the TAG of the + * corresponding packet. + * @val: Pointer to data buffer + * @bytes: length of the buffer + * + * A value of zero will be returned on success, a negative errno will be + * returned in error cases. */ static int mchp_otpc_read(void *priv, unsigned int off, void *val, size_t bytes) @@ -154,30 +199,23 @@ static int mchp_otpc_read(void *priv, unsigned int of= f, void *val, int ret, payload_size; =20 /* - * We reach this point with off being multiple of stride =3D 4 to - * be able to cross the subsystem. Inside the driver we use continuous - * unsigned integer numbers for packet id, thus divide off by 4 - * before passing it to mchp_otpc_id_to_packet(). + * From this point the packet tag received as the offset has to be transl= ated + * into the actual packet. For this we traverse the table of contents sto= red + * in a list "packet" and look for the tag. */ - packet =3D mchp_otpc_id_to_packet(otpc, off / 4); + + packet =3D mchp_otpc_tag_to_packet(otpc, off); if (!packet) return -EINVAL; - offset =3D packet->offset; + offset =3D packet->payload_info.packet_offset; =20 - while (len < bytes) { + if (len < bytes) { ret =3D mchp_otpc_prepare_read(otpc, offset); if (ret) return ret; =20 - /* Read and save header content. */ - *buf++ =3D readl_relaxed(otpc->base + MCHP_OTPC_HR); - len +=3D sizeof(*buf); - offset++; - if (len >=3D bytes) - break; - /* Read and save payload content. */ - payload_size =3D FIELD_GET(MCHP_OTPC_HR_SIZE, *(buf - 1)); + payload_size =3D packet->payload_info.payload_length; writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR); do { *buf++ =3D readl_relaxed(otpc->base + MCHP_OTPC_DR); @@ -190,6 +228,20 @@ static int mchp_otpc_read(void *priv, unsigned int off= , void *val, return 0; } =20 +static int mchp_otpc_read_packet_tag(struct mchp_otpc *otpc, unsigned int = offset, unsigned int *val) +{ + int ret; + + ret =3D mchp_otpc_prepare_read(otpc, offset); + if (ret) + return ret; + + writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR); + *val =3D readl_relaxed(otpc->base + MCHP_OTPC_DR); + + return 0; +} + static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size) { struct mchp_otpc_packet *packet; @@ -213,8 +265,15 @@ static int mchp_otpc_init_packets_list(struct mchp_otp= c *otpc, u32 *size) if (!packet) return -ENOMEM; =20 - packet->id =3D id++; - packet->offset =3D word_pos; + packet->payload_info.id =3D id++; + packet->payload_info.packet_offset =3D word_pos; + packet->payload_info.payload_length =3D payload_size; + packet->payload_info.packet_type =3D FIELD_GET(MCHP_OTPC_HR_PACKET_TYPE,= word); + + if (packet->payload_info.packet_type =3D=3D PACKET_TYPE_REGULAR) + ret =3D mchp_otpc_read_packet_tag(otpc, packet->payload_info.packet_off= set, + &packet->payload_info.packet_tag); + INIT_LIST_HEAD(&packet->list); list_add_tail(&packet->list, &otpc->packets); =20 @@ -236,7 +295,7 @@ static struct nvmem_config mchp_nvmem_config =3D { .type =3D NVMEM_TYPE_OTP, .read_only =3D true, .word_size =3D 4, - .stride =3D 4, + .stride =3D 1, .reg_read =3D mchp_otpc_read, }; =20 @@ -244,8 +303,9 @@ static int mchp_otpc_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; struct mchp_otpc *otpc; - u32 size; + u32 size, tmp; int ret; + bool emul_enable; =20 otpc =3D devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL); if (!otpc) @@ -256,10 +316,22 @@ static int mchp_otpc_probe(struct platform_device *pd= ev) return PTR_ERR(otpc->base); =20 otpc->dev =3D &pdev->dev; + + tmp =3D readl_relaxed(otpc->base + MCHP_OTPC_MR); + emul_enable =3D tmp & MCHP_OTPC_MR_EMUL; + if (emul_enable) + dev_info(otpc->dev, "Emulation mode enabled\n"); + ret =3D mchp_otpc_init_packets_list(otpc, &size); if (ret) return ret; =20 + if (size =3D=3D 0) { + dev_err(otpc->dev, "Cannot access OTP memory !\n"); + if (!emul_enable) + dev_err(otpc->dev, "Boot packet not configured & Emulation mode not ena= bled !\n"); + } + mchp_nvmem_config.dev =3D otpc->dev; mchp_nvmem_config.add_legacy_fixed_of_cells =3D true; mchp_nvmem_config.size =3D size; --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEC39248871; 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charset="utf-8" Update the example binding according to the new driver implementation. Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc= .yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml index cc25f2927682..e9059dce85ef 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -42,9 +42,8 @@ examples: reg =3D <0xe8c00000 0xec>; #address-cells =3D <1>; #size-cells =3D <1>; - - temperature_calib: calib@1 { - reg =3D ; + temperature_calib: calib@41435354 { + reg =3D <0x41435354 0x4c>; /* Temp calib data packet TA= G */ }; }; =20 --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9458124E4C3; Mon, 4 Aug 2025 10:03:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301796; cv=none; b=Ia9oeL1x9/4cOOKWk+jTloPzeiL/sXAKHBZzEMaPTmOiwQ58JMBDDjHe5+VRH7HzW+5Jj6uLBD62pdJp+jV1IQVnv+cJ7sJPyrR+Ssq2hKeY6LOL61DOkSd2vlhGnTQWnEjwlkjS+gyf9A+2wwiL0fJDe5lOxCglDb2rNO+mhoo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301796; c=relaxed/simple; bh=Co7gfwT4mHYrZjebZQxjjmc0VfEU+S5rAP9qwyGGqg8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=s+Arcwktjn029zjKUlVrv+ikeF7f3R8mcXZsrvgS92e0TxjMQcLYTjScKdKJWjCEEX2Ec6OVx43f2gjgh2Hq4t8tWoGxzazhxRTbw4JbwdH3HRkZVd2FyC9YiAgx+dlpkIFmTAbyXXL843DxHLQ1Py6wQ26PzbpKprArZ+yG9AQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=JoCXiucg; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="JoCXiucg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301794; x=1785837794; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Co7gfwT4mHYrZjebZQxjjmc0VfEU+S5rAP9qwyGGqg8=; b=JoCXiucgXHGfXMpq+zCct1UMFDNtwYqKgxx+S3dpQbQD3rORFr5aDHBN uCFLb7V3JAkm+Jr/2lvQ9TrWOur46PfkaC1BRs7ROSAcgNXGutlkLvzEH qqe0r2pgkDjQzNfXZOU2i1bN6dkE2zqSO79rNrtknGwZcGFQ9eK9/bROd /LQ5w2M4aZk13EN7w7/UzXfqv9YI3iCqyTdziFuWUGvPfutVTqXeJX2P6 aSa1HNfNFWNbLPV/N8XjgeLP+Ud45T5jQClhxD8pt34ftn6elLxG8nnsv 7AnaQ8LMWWcFhb3m9SzjqyLeaAftVs4iZOtGeHPzzNw8YpdE6I8OdaVXX w==; X-CSE-ConnectionGUID: Liqowa5KRuKZ85yXFKRAhg== X-CSE-MsgGUID: V6sbAXJ8TPW8PGSA1Xm7yg== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="50182876" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:03:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:02:54 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:02:48 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 04/15] iio: adc: at91-sama5d2_adc: update calibration index, validation condition Date: Mon, 4 Aug 2025 15:32:08 +0530 Message-ID: <20250804100219.63325-5-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add additional condition for validating the calibration data read from the OTP through nvmem device interface. Adjust the calibration indexes of sama7g5 according to the buffer received from the OTP memory. Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index c3450246730e..d952109a64a9 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -445,6 +445,14 @@ static const struct at91_adc_reg_layout sama7g5_layout= =3D { #define at91_adc_writel(st, reg, val) \ writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg) =20 +/* + * The calibration data has a TAG to recognize the packet + * The tag has a constant value "ACST" with the ASCII + * equivalent 0x41435354. This is used to validate the + * calibration data obtained from the OTP. + */ +#define AT91_TEMP_CALIB_TAG 0x41435354 + /** * struct at91_adc_platform - at91-sama5d2 platform information struct * @layout: pointer to the reg layout struct @@ -504,10 +512,10 @@ struct at91_adc_temp_sensor_clb { * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet = in OTP */ enum at91_adc_ts_clb_idx { - AT91_ADC_TS_CLB_IDX_P1 =3D 2, - AT91_ADC_TS_CLB_IDX_P4 =3D 5, - AT91_ADC_TS_CLB_IDX_P6 =3D 7, - AT91_ADC_TS_CLB_IDX_MAX =3D 19, + AT91_ADC_TS_CLB_IDX_P1 =3D 1, + AT91_ADC_TS_CLB_IDX_P4 =3D 4, + AT91_ADC_TS_CLB_IDX_P6 =3D 6, + AT91_ADC_TS_CLB_IDX_MAX =3D 18, }; =20 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperatu= re. */ @@ -2281,7 +2289,7 @@ static int at91_adc_temp_sensor_init(struct at91_adc_= state *st, dev_err(dev, "Failed to read calibration data!\n"); return PTR_ERR(buf); } - if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) { + if (len < AT91_ADC_TS_CLB_IDX_MAX * 4 || buf[0] !=3D AT91_TEMP_CALIB_TAG= ) { dev_err(dev, "Invalid calibration data!\n"); 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charset="utf-8" Add packet tag as offset to access temperature calibration data from otp memory for sama7g5. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7g5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/m= icrochip/sama7g5.dtsi index 17bcdcf0cf4a..62f946f3f894 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -1023,8 +1023,8 @@ otpc: efuse@e8c00000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 - temperature_calib: calib@1 { - reg =3D ; + temperature_calib: calib@41435354 { + reg =3D <0x41435354 0x4c>; /* Temp calib data packet TAG */ }; }; =20 --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FD6D254AF0; Mon, 4 Aug 2025 10:03:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301798; cv=none; b=FVItOIC79D+2hPZ87qWcuENFE0Dc1ARgP2DEKU4Kst4l/h3j3gNzPiJn1u0rvBuoCf0113RuCvm8b19H4NL07MZNvS4bXHSdzDHnncj1G3MIBSMrCeDj177rzAE90ZalIcoda4T1Cm1I9UC+g7gXV+UAhH6UdvG7/u6iToSj0G0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301798; c=relaxed/simple; bh=rExnJEsUclWRnuXGTLi8ZjxHecMNknzyT1tPuf5PI9I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=it+GEB6fH/Qu4G/JjJNXl3UYOBsEjV1o/4p5fm5oK64HV/9dwnWRVDg5uUN4oI0vn0sAsUe8Ek8DC9wlwj3w70qhDJOS/PIPSEWfat32VMyXlC5B0IjDxklyQURdBBJ57VENsyQSJ7bTVerUuwauYDimE8dXVDI9KlW91nogqgo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=bysfvyQZ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="bysfvyQZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301797; x=1785837797; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rExnJEsUclWRnuXGTLi8ZjxHecMNknzyT1tPuf5PI9I=; b=bysfvyQZrs2FL0/0xqgMBLwM4hZeFEioyjAPo2PqRlej+8V8httAQtpk O40t3Dat8mhSxGQhNM4jvndwf/FZwn7mIiTdttPmLAQs0zxfofkcGiOIJ Itf7qQBsGrzW106O89a+RZQc7+Q78eTGSGqmZ55HBi34Fy7bHi5rLdoy1 wq+54rA1cGGS3xhG9WdhNJsCYUC/tJdF1G1jibOa3diWOcApiPZCih8D0 Wnb1RSR53A551hGiWi9W32K8CSb+njHTNEEXvpRfdkU0KWtTseIvSeMgg cSuk2rQCWSe9sjZydQXlT4ahPIwyvG2O9qQ4CMpqQ9De8yKGKZxg9IEQ6 A==; X-CSE-ConnectionGUID: QrHuXWrSRt6GNRSNglLzJg== X-CSE-MsgGUID: BPr72ON8RL2cJ2k6co4c9Q== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="44245504" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:03:15 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:03:06 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:03:01 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 06/15] dt-bindings: nvmem: microchip-otpc: remove stride details Date: Mon, 4 Aug 2025 15:32:10 +0530 Message-ID: <20250804100219.63325-7-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Removed stride details from the bindings header as they are not relevant anymore since the access method of OTP packets is changed to TAG approach. Update the example binding according to the new changes. Signed-off-by: Varshini Rajendran --- include/dt-bindings/nvmem/microchip,sama7g5-otpc.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/d= t-bindings/nvmem/microchip,sama7g5-otpc.h index f570b23165a2..682b040675fd 100644 --- a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h +++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h @@ -3,10 +3,4 @@ #ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H #define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H =20 -/* - * Need to have it as a multiple of 4 as NVMEM memory is registered with - * stride =3D 4. - */ -#define OTP_PKT(id) ((id) * 4) - #endif --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4AFE2566DD; Mon, 4 Aug 2025 10:03:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301799; cv=none; b=lh4ALMzvY5nQPYl5hKaRvHI/qMXN1FxocGo66YK+JxrIR258Bk9vJvS3YbyCLyNI/zdfHQZj5Q/ZcozYVFTIEOXKWhX/WpurKSYPxHVq2j1Ao4NzYT/sMUefpaiFQICZWjYDKCT8mEflVhKTqT96JbNcSoDpwh9AGq337vPIWVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301799; c=relaxed/simple; bh=NHU+4lXLdo/vKM5ziZuHEbn4fKMpkU+mkRMJySUxKhU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V+Mx7pO9vxT16kL/L6tPNYPcVrKeXg7qiqXuiF6acjk8yQVFXcT7k7QjOlMEaj20yAQdrfZ7XkQMG8DlbdTpO0/U8byQ5ZGQZJVkQUa9A2nKgEQVbG++Q05ByFI6Zttce7C5gKGWPBsJ0WkFGBSppZ/eY4uz30UFtFSSmXXVBiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=L5YS01e+; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="L5YS01e+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301797; x=1785837797; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NHU+4lXLdo/vKM5ziZuHEbn4fKMpkU+mkRMJySUxKhU=; b=L5YS01e+9R9WN0YiSPnyAqGvAFeUjwnXimjqhD2v8srSY+pRbwreQIWv kVcSnUnBff/Wyv6YqKKf6pzqSBz0qrd/wGwyhvFdKKIYkOiZX4ZMSEo1N ZlXwbwlgWJ6w75gYGpZ25SUkkZ+J8avTJFRPhHO24FMEmGxZ3a4rRtohM UX884Ay/NtDcS5SH7x0XdSdcGElH25xj1Am8f2XPLGwm4N4OcqgBQkesZ yYcXJJdmu0bDcT4XnbsZmNV6wI8PeVTBqjHyuTQN9Ordg9W3xnnFxMPDL NOxdfDPnBaGaplS4ckQVOpmjJwry1o7V/F7uLRRFxRXQg6wVz8bVHgqLW A==; X-CSE-ConnectionGUID: QrHuXWrSRt6GNRSNglLzJg== X-CSE-MsgGUID: d4QybLDHSbij9X24PZTrgw== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="44245505" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:03:15 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:03:12 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:03:07 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 07/15] iio: adc: at91-sama5d2_adc: add temp init function as callback Date: Mon, 4 Aug 2025 15:32:11 +0530 Message-ID: <20250804100219.63325-8-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adding the temperature sensor init function as a callback function. The temperature sensor initialisation sequence is handled differently for each platform. The same is added to the platform data of the corresponding device. This allows us to handle new devices like sama7d65. Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index d952109a64a9..916682e326c7 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -453,6 +453,10 @@ static const struct at91_adc_reg_layout sama7g5_layout= =3D { */ #define AT91_TEMP_CALIB_TAG 0x41435354 =20 +struct at91_adc_state; +static int at91_adc_temp_sensor_init(struct at91_adc_state *st, + struct device *dev); + /** * struct at91_adc_platform - at91-sama5d2 platform information struct * @layout: pointer to the reg layout struct @@ -472,6 +476,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { * @chan_realbits: realbits for registered channels * @temp_chan: temperature channel index * @temp_sensor: temperature sensor supported + * @temp_init: callback function to initialize the temperature sensor + * with its calibration data */ struct at91_adc_platform { const struct at91_adc_reg_layout *layout; @@ -489,6 +495,7 @@ struct at91_adc_platform { unsigned int chan_realbits; unsigned int temp_chan; bool temp_sensor; + int (*temp_init)(struct at91_adc_state *st, struct device *dev); }; =20 /** @@ -729,6 +736,7 @@ static const struct at91_adc_platform sama5d2_platform = =3D { .oversampling_avail =3D { 1, 4, 16, }, .oversampling_avail_no =3D 3, .chan_realbits =3D 14, + .temp_init =3D at91_adc_temp_sensor_init, }; =20 static const struct at91_adc_platform sama7g5_platform =3D { @@ -753,6 +761,7 @@ static const struct at91_adc_platform sama7g5_platform = =3D { .chan_realbits =3D 16, .temp_sensor =3D true, .temp_chan =3D AT91_SAMA7G5_ADC_TEMP_CHANNEL, + .temp_init =3D at91_adc_temp_sensor_init, }; =20 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -2328,7 +2337,7 @@ static int at91_adc_probe(struct platform_device *pde= v) =20 st->soc_info.platform =3D device_get_match_data(dev); =20 - ret =3D at91_adc_temp_sensor_init(st, &pdev->dev); + ret =3D st->soc_info.platform->temp_init(st, &pdev->dev); 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Mon, 4 Aug 2025 03:03:13 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 08/15] dt-bindings: iio: adc: at91-sama5d2: document sama7d65 Date: Mon, 4 Aug 2025 15:32:12 +0530 Message-ID: <20250804100219.63325-9-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt-binding documentation for sama7d65 ADC. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.ya= ml b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml index 4817b840977a..e8a65fdcd018 100644 --- a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml @@ -15,6 +15,7 @@ properties: - atmel,sama5d2-adc - microchip,sam9x60-adc - microchip,sama7g5-adc + - microchip,sama7d65-adc =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6622A2288EE; Mon, 4 Aug 2025 10:03:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301824; cv=none; b=ENaDSIbMC4h+Eeeck2JImSIye3gD5q6Ss9oOAslO8i/fE99gOHVAN0wD5D/O6qEit3ZpLMHDuSyS354VkxymCrwc2n99Nov0dS39JzbC3F4ZhLXKY39zWt2227A93G6v6DUbXq8GlKmSiclI+5UxWORZFdgAaRCKn5Xk1NKi/1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301824; c=relaxed/simple; bh=6W4F2tMrJ4fQ3+1dSbKRAr9IS7Qo3RdtktFxwVVRt40=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CZGG7fY3KkCYU5R3dhsOz8BfUTc2ENtJWyUK4gpzx6iVFiWX2UyaK8+u3TWkmMWtTlzaKtdJNtKhmkUsNxQ96pPj3QnBm26qGK5UVn3HO1CePYWDTE70yffhzmYPHvdpoFmg6h7zFQGpW4QQnrIYPCYS9rsOMjHi41/pqsEo85I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ENr7FJU8; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ENr7FJU8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301822; x=1785837822; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6W4F2tMrJ4fQ3+1dSbKRAr9IS7Qo3RdtktFxwVVRt40=; b=ENr7FJU828nLqgO/UEqDus4m2g9MW4xDkpS1oRXS/xdxWZz9EYkLoyOt 6fHgSwBMOJ0try/OgbUYZt+yqYbZkzfvgi3v5Kg+vxB3N09xQmKZsRQI/ Lk4dtN70CFAdi9p8p9eIc3UuIzKTsgvRsUxlF/ME8YcUc5JQBd/tNb2RC swjKArOplx+xgDHizTA+jWod7N173Wk1xmsezlpszNqUERKajmQqp8yM2 Uk6kU6eEpZQVaDZ7rw1lc+Tke1JLzkkqFfaEh6dNRZDIIGW44cvS8pOV1 qX83zaT8WRg00fSiA7O6XTQg4RGZW391tHgM7hgaZ+TGNIYhcedk4Cd+1 g==; X-CSE-ConnectionGUID: E6rlgp6tRPCj0Q8ccA/Yqg== X-CSE-MsgGUID: nhnyn57ETHaYkg3E28HNcw== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="44245519" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:03:40 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:03:25 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:03:19 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 09/15] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65 Date: Mon, 4 Aug 2025 15:32:13 +0530 Message-ID: <20250804100219.63325-10-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to sama7d65 ADC. The differences are highlighted with the compatible. The init and parsing of the temperature sensor and calibration indexes are the main differences. Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 94 ++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 916682e326c7..909841b84834 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -456,6 +456,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { struct at91_adc_state; static int at91_adc_temp_sensor_init(struct at91_adc_state *st, struct device *dev); +static int at91_sama7d65_adc_temp_sensor_init(struct at91_adc_state *st, + struct device *dev); =20 /** * struct at91_adc_platform - at91-sama5d2 platform information struct @@ -525,6 +527,20 @@ enum at91_adc_ts_clb_idx { AT91_ADC_TS_CLB_IDX_MAX =3D 18, }; =20 +/** + * enum at91_sama7d65_adc_ts_clb_idx - calibration indexes in sama7d65 NVM= EM buffer + * @AT91_SAMA7D65_ADC_TS_CLB_IDX_P1: index for FT1_TEMP equivalent to P1 *= (10 ^ 6) + * @AT91_SAMA7D65_ADC_TS_CLB_IDX_P4: index for FT1_VPAT equivalent to P4 + * @AT91_SAMA7D65_ADC_TS_CLB_IDX_P6: index for FT2_VBG equivalent to P6 + * @AT91_SAMA7D65_ADC_TS_CLB_IDX_MAX: max index for temperature calibratio= n packet in OTP + */ +enum at91_sama7d65_adc_ts_clb_idx { + AT91_SAMA7D65_ADC_TS_CLB_IDX_P1 =3D 2, + AT91_SAMA7D65_ADC_TS_CLB_IDX_P4 =3D 1, + AT91_SAMA7D65_ADC_TS_CLB_IDX_P6 =3D 4, + AT91_SAMA7D65_ADC_TS_CLB_IDX_MAX =3D 10, +}; + /* Temperature sensor calibration - Vtemp voltage sensitivity to temperatu= re. */ #define AT91_ADC_TS_VTEMP_DT (2080U) =20 @@ -764,6 +780,31 @@ static const struct at91_adc_platform sama7g5_platform= =3D { .temp_init =3D at91_adc_temp_sensor_init, }; =20 +static const struct at91_adc_platform sama7d65_platform =3D { + .layout =3D &sama7g5_layout, + .adc_channels =3D &at91_sama7g5_adc_channels, +#define AT91_SAMA7D65_SINGLE_CHAN_CNT 16 +#define AT91_SAMA7D65_DIFF_CHAN_CNT 8 +#define AT91_SAMA7D65_TEMP_CHAN_CNT 1 + .nr_channels =3D AT91_SAMA7D65_SINGLE_CHAN_CNT + + AT91_SAMA7D65_DIFF_CHAN_CNT + + AT91_SAMA7D65_TEMP_CHAN_CNT, +#define AT91_SAMA7D65_MAX_CHAN_IDX (AT91_SAMA7D65_SINGLE_CHAN_CNT + \ + AT91_SAMA7D65_DIFF_CHAN_CNT + \ + AT91_SAMA7D65_TEMP_CHAN_CNT) + .max_channels =3D ARRAY_SIZE(at91_sama7g5_adc_channels), + .max_index =3D AT91_SAMA7D65_MAX_CHAN_IDX, +#define AT91_SAMA7G5_HW_TRIG_CNT 3 + .hw_trig_cnt =3D AT91_SAMA7G5_HW_TRIG_CNT, + .osr_mask =3D GENMASK(18, 16), + .oversampling_avail =3D { 1, 4, 16, 64, 256, }, + .oversampling_avail_no =3D 5, + .chan_realbits =3D 16, + .temp_sensor =3D true, + .temp_chan =3D AT91_SAMA7G5_ADC_TEMP_CHANNEL, + .temp_init =3D at91_sama7d65_adc_temp_sensor_init, +}; + static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) { int i; @@ -2319,6 +2360,56 @@ static int at91_adc_temp_sensor_init(struct at91_adc= _state *st, return ret; } =20 +static int at91_sama7d65_adc_temp_sensor_init(struct at91_adc_state *st, + struct device *dev) +{ + struct at91_adc_temp_sensor_clb *clb =3D &st->soc_info.temp_sensor_clb; + struct nvmem_cell *temp_calib; + u32 *buf =3D NULL; + size_t len; + int ret =3D 0; + + if (!st->soc_info.platform->temp_sensor) + return 0; + + /* Get the calibration data from NVMEM. */ + temp_calib =3D devm_nvmem_cell_get(dev, "temperature_calib"); + if (IS_ERR(temp_calib)) { + ret =3D PTR_ERR(temp_calib); + if (ret !=3D -ENOENT) + dev_err(dev, "Failed to get temperature_calib cell!\n"); + return ret; + } + + buf =3D nvmem_cell_read(temp_calib, &len); + if (IS_ERR(buf)) { + dev_err(dev, "Failed to read calibration data!\n"); + return PTR_ERR(buf); + } + + if (len < AT91_SAMA7D65_ADC_TS_CLB_IDX_MAX * sizeof(u32) || + buf[0] !=3D AT91_TEMP_CALIB_TAG) { + dev_err(dev, "Invalid calibration data!\n"); + ret =3D -EINVAL; + goto free_buf; + } + + /* Store calibration data for later use. */ + clb->p1 =3D buf[AT91_SAMA7D65_ADC_TS_CLB_IDX_P1]; + clb->p4 =3D buf[AT91_SAMA7D65_ADC_TS_CLB_IDX_P4]; + clb->p6 =3D buf[AT91_SAMA7D65_ADC_TS_CLB_IDX_P6]; + + /* + * We prepare here the conversion to milli from micro to avoid + * doing it on hotpath. + */ + clb->p1 =3D clb->p1 / 1000; + +free_buf: + kfree(buf); + return ret; +} + static int at91_adc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -2633,6 +2724,9 @@ static const struct of_device_id at91_adc_dt_match[] = =3D { }, { .compatible =3D "microchip,sama7g5-adc", .data =3D (const void *)&sama7g5_platform, + }, { + .compatible =3D "microchip,sama7d65-adc", + .data =3D (const void *)&sama7d65_platform, }, { /* sentinel */ } --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 195292288EE; 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charset="utf-8" Add node for the ADC controller in sama7d65 SoC. Also add corresponding regulator and pinmux for the ADC. Signed-off-by: Romain Sioen Signed-off-by: Varshini Rajendran --- .../dts/microchip/at91-sama7d65_curiosity.dts | 23 +++++++++++++++ arch/arm/boot/dts/microchip/sama7d65.dtsi | 29 +++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch= /arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 7250823a6f59..7ecc748456ba 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -41,6 +41,14 @@ reg_5v: regulator-5v { =20 }; =20 +&adc { + vddana-supply =3D <&vddout25>; + vref-supply =3D <&vddout25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc_default &pinctrl_adtrg_default>; + status =3D "okay"; +}; + &dma0 { status =3D "okay"; }; @@ -278,6 +286,16 @@ &main_xtal { }; =20 &pioa { + pinctrl_adc_default: adc_default { + pinmux =3D ; + bias-disable; + }; + + pinctrl_adtrg_default: adtrg-default { + pinmux =3D ; + bias-pull-up; + }; + pinctrl_gmac0_default: gmac0-default { pinmux =3D , , @@ -373,3 +391,8 @@ input@0 { &slow_xtal { clock-frequency =3D <32768>; }; + +&vddout25 { + vin-supply =3D <&vdd_3v3>; + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 2e20a7532c03..1f249323d08a 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -83,6 +84,16 @@ slow_xtal: clock-slowxtal { }; }; =20 + vddout25: fixed-regulator-vddout25 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VDDOUT25"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-boot-on; + status =3D "disabled"; + }; + ns_sram: sram@100000 { compatible =3D "mmio-sram"; reg =3D <0x100000 0x20000>; @@ -199,6 +210,24 @@ chipid@e0020000 { reg =3D <0xe0020000 0x8>; }; =20 + adc: adc@e1000000 { + compatible =3D "microchip,sama7d65-adc"; + reg =3D <0xe1000000 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_GCK 25>; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 25>; + assigned-clock-rates =3D <100000000>; + clock-names =3D "adc_clk"; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(0)>; + dma-names =3D "rx"; + atmel,min-sample-rate-hz =3D <200000>; + atmel,max-sample-rate-hz =3D <20000000>; + atmel,trigger-edge-type =3D ; + atmel,startup-time-ms =3D <4>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + dma2: dma-controller@e1200000 { compatible =3D "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg =3D <0xe1200000 0x1000>; --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9D2E24BD1A; Mon, 4 Aug 2025 10:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; 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charset="utf-8" Add microchip,sama7d65-otpc to DT bindings documentation. Signed-off-by: Varshini Rajendran --- .../bindings/nvmem/microchip,sama7g5-otpc.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc= .yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml index e9059dce85ef..43625c9d6af5 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -20,9 +20,15 @@ allOf: =20 properties: compatible: - items: - - const: microchip,sama7g5-otpc - - const: syscon + oneOf: + - items: + - const: microchip,sama7g5-otpc + - const: syscon + - items: + - enum: + - microchip,sama7d65-otpc + - const: microchip,sama7g5-otpc + - const: syscon =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED45824C06A; Mon, 4 Aug 2025 10:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301847; cv=none; b=qii1iwzQV0EbrayadZMf3t31arcf1iGaJkQYpBmSk7sim8XOe2rKFo6dyhsyKQDbaoRXd68hh3Cxm16dcytiipExvAG3F5QZRJskTG3cEVnG2XBgPDdx1cil1u1wJun7w9sPt2BJ4958/uFec2QX1iyad+4cG7hJedVotpl2nrM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301847; c=relaxed/simple; bh=OO+4hFY4hrkvoHxCh16qXc+sfsnxcGj6fzpJBv4i9i0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JC6KaLVtM57ItOwy85kwpk94iU791xxo8hum8FjdgA0q3vjgwGxmikis5tkoMprQn4yaPeihCtAatU+8m+6hVob7djRfFHEoLf5IXdj0lu620yz5yH1CLYgQExNaepvpuUbpJD9dTvtfa9se3XZ1324+a4kY9kfCTaGujwwPkPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=vZhWsTjC; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="vZhWsTjC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301845; x=1785837845; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OO+4hFY4hrkvoHxCh16qXc+sfsnxcGj6fzpJBv4i9i0=; b=vZhWsTjC/n+ERRCOeXYrm8f8DLG3ypPZzLIK5rlpaWiDgPuI5b6rPVzC FbJE0u+9k4/DGbh+Gmv8zhOWy/Eod4avYY6Qyyk38WN3rNcPJXjyIB08d cUnzad/sz7uhcSKLb3N+RrZeNTZJ1n3cBP6h9UM5tDxxhvbNRh0N4zUdk HQiu1FZbCja8qAp04ZoaIyaJEj4DzOR93Y2/+C4jBymZbto1I0m7mMTHB 5kZ0bdCnQRPYKJuTfhYkLWqbNkNr+YuCNpovnk+m85IjbEI1SM46eFJa5 zkDerBA99PMcLbmABYX+r7n05I/+HYla7Qa/np7r6nT7wKOCjXbwa0Vv2 w==; X-CSE-ConnectionGUID: +866aF0tQ+SVcfcIeqWRcg== X-CSE-MsgGUID: WoN7XXpoTE6eoGfuANyu6A== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="44245549" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:04:05 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:03:45 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:03:38 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 12/15] ARM: dts: microchip: sama7d65: add otpc node Date: Mon, 4 Aug 2025 15:32:16 +0530 Message-ID: <20250804100219.63325-13-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OTPC node along with temperature calibration cell. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 1f249323d08a..1d3708c76202 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include =20 / { model =3D "Microchip SAMA7D65 family SoC"; @@ -638,6 +639,17 @@ ddr3phy: ddr3phy@e3804000 { reg =3D <0xe3804000 0x1000>; }; =20 + otpc: efuse@e8c00000 { + compatible =3D "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "sy= scon"; + reg =3D <0xe8c00000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + temperature_calib: calib@41435354 { + reg =3D <0x41435354 0x2c>; /* Temp calib data packet TAG */ + }; + }; + gic: interrupt-controller@e8c11000 { compatible =3D "arm,cortex-a7-gic"; reg =3D <0xe8c11000 0x1000>, --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3047224E4D4; Mon, 4 Aug 2025 10:04:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301848; cv=none; b=BzxcaqCpVoErtUqIuhvb/d86T8iDQawPR7Dmrk+6StKIBOklE60UefgGPHENGm61Ix7NP1rLCLZGgx/ZbGuoI8i0NHUidEJbDnDPafbgDvyD/N3OGlAzcZI8Ixy9zYLqbLr8cycHHSQw7dppNG/Tn+Fq8W/8HG5ZC/mbphix72E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301848; c=relaxed/simple; bh=Mijv1aZVie6s80Qf3VFPYS2QkPCgAnCI/m/Zfv+EXmE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XWDKcCPe09Z6hGa9iNgPIwRcX4AQ+M6cxvX79R0Y5vdnyzukq/yEPNFJX2zrp8XxCHx1FW7MKHISua8O4hEojTbQT5WxUXxWLrnKOjXAxoWkumCltsotxxnTG7IdyNLyKI0R5l5DRHGLmuK1QKBnNTnr6wYejzUo00za1nnsnuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=TVxGEMlT; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="TVxGEMlT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301847; x=1785837847; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mijv1aZVie6s80Qf3VFPYS2QkPCgAnCI/m/Zfv+EXmE=; b=TVxGEMlTanityD/qEIe6f2ysfRklmUcuzVjqew05wdnXiYKVaZTHWwDw sBuWg3dLrvGCkKHu6LxmB1hwcwet/llMwXFMGgqa2adVvWs3qBJs7c666 D5MLsPWY0DyOOZP2m2NKWzU5uviQN9/2iMAB+N2FYdnyOUCg95UPlYFGp BsC56/BUDXu3WzDHPzb6EPfeSoLa+lTjTVTPsPwiRr8N6vz68K+1I9XVQ NoOk/g474AXvFxijhSJM4IyqNB0Rl+ZpsPmKkV2JqJQJXgN0+fwpAd+CY p0j2N7tvNdmU2p47/GXIrCg0T31flrwWQ298YH6cMOeMrliAscoPBGrsM w==; X-CSE-ConnectionGUID: +866aF0tQ+SVcfcIeqWRcg== X-CSE-MsgGUID: tLRJaqVOQH28qBNXOUi4Lg== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="44245552" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:04:05 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:03:51 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:03:45 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 13/15] ARM: dts: microchip: sama7d65: add cells for temperature calibration Date: Mon, 4 Aug 2025 15:32:17 +0530 Message-ID: <20250804100219.63325-14-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add NVMEM cell to ADC for temperature calibration data. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 1d3708c76202..5d1f6684f64f 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -226,6 +226,8 @@ adc: adc@e1000000 { atmel,trigger-edge-type =3D ; atmel,startup-time-ms =3D <4>; #io-channel-cells =3D <1>; + nvmem-cells =3D <&temperature_calib>; + nvmem-cell-names =3D "temperature_calib"; status =3D "disabled"; }; =20 --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5E825A2C2; Mon, 4 Aug 2025 10:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301849; cv=none; b=inlXORxaItx1nU9xL7AR3c5WBd9NbzE0+elUCYaJbPtCucqWHfaJ6vhFKzs3H6O179vECJFpOQlq35ghE4VUchLke/KMOyRWN5IxrzFTaNp2m5/eJ6VoXFeWLvwv9vWQf4grCpwHAR5bkozL13lMfq34n1FedA2i5RbTfwHrITM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301849; c=relaxed/simple; bh=sNaoy8/stCR2oSveDjFYF8EHjZ9xs9dYDS7l9udDb0A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uPsX2C56WTsj1S5JQlG59gckxpUyDrM29rtqSV8bkrO000jJnfw64a9yqp+aEKg4ProkSLfEom9KqcOOZuJk8kumznpx6g3U5tElG/+kyeGMebHVuE5J1ozuUOlHZr7lPkxGSASgplxgjd8BVjBw37PqfoIWUN+DUn30HHPKpK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=kXyJBR7Z; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="kXyJBR7Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301848; x=1785837848; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sNaoy8/stCR2oSveDjFYF8EHjZ9xs9dYDS7l9udDb0A=; b=kXyJBR7ZP7Nxu25VnZ4YSYKBoLja+sl7IQKcuyb00Kh6ZpPNIPG0mD1U sUF0iFam4GfTky0wQrPg+agUDXIyxMSu0iREBBUCCGyLehGlRtwCvYdg2 FsIcVe8yxfFcfigmQjyV8XrUeQwVo92aJnzDngRUSR0oi+PiqNTcQmZ6t hBfMVFTpbjilgMK0MtmbS8PlCUEYXsH8AOAxA2Ef47+siMp1y3YNPckr3 zpDyawyOCzP6wBdr5ayr3wlo7FcdQyGix10s5jLYh6fukMIDpoa1ceUps pOW2J7FaJlIKzVSPrOTohqaLPKUgkBeaTQ6zft+ftkAnEMC2r4ht6L5z5 A==; X-CSE-ConnectionGUID: +866aF0tQ+SVcfcIeqWRcg== X-CSE-MsgGUID: +JNh/NbuT3a9KNh0rf8oGw== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="44245556" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:04:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:03:58 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:03:52 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 14/15] ARM: dts: microchip: sama7d65: add temperature sensor Date: Mon, 4 Aug 2025 15:32:18 +0530 Message-ID: <20250804100219.63325-15-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add temperature sensor node. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 5d1f6684f64f..aefdd72cb59c 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -103,6 +103,13 @@ ns_sram: sram@100000 { #size-cells =3D <1>; }; =20 + thermal_sensor: thermal-sensor { + compatible =3D "generic-adc-thermal"; + #thermal-sensor-cells =3D <0>; + io-channels =3D <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; + io-channel-names =3D "sensor-channel"; + }; + soc { compatible =3D "simple-bus"; ranges; --=20 2.34.1 From nobody Sun Oct 5 12:36:43 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F102512E6; Mon, 4 Aug 2025 10:04:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301889; cv=none; b=WnkSLDGBGySFHRaMF1ozQtOwWiyhnr3r2d7keid4JMygCYyA7iFEqN7i2dNww9tsk/UF0NS2a3eu9x5PkpA6en1vZhsn4k+3ClVJDvmWvz2m7swKp2zYavuV8TifRiUa1+Mt82+Vppq6DpWNaU3ob5l9FPWT1ORiYQ76XM3mZsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754301889; c=relaxed/simple; bh=0I0mIx+jCtAYkBXL2kVeCEA9sezb9K7m6lEQk5mGw1w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L1V/TJ50pwRET2fQ0iaGLr3ZfSXGZvK/NVUdaKej58XtTIzhZEcdmomPf4ahp4AIIpVtpkElY0RnzYTuOLOjMTWoEwoMT7cm3kbK2Jh4MdkC1Agvw3qVIM6YblNBWTGtii6xYANx6BX+CNa0SXvBbLGYbOvJzwbV82IMUrDskiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=M39levsm; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="M39levsm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1754301887; x=1785837887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0I0mIx+jCtAYkBXL2kVeCEA9sezb9K7m6lEQk5mGw1w=; b=M39levsmX9H+CV2G0mBcxkf5HUwSEsU79h6fZX3jRn70cB/9XZOzIMGh Pi3iIVknXGtByHgaFt8TKosld2IX406pYnuavJezbplu3Cqp2BKtu/JfA 14aFFqI6+W0odJkrn2alxHa0Wwfl0fSn1ekJKY5Tca02bb6N2BaDK2SNh OEdxzzbB6Vr/VYWbj/JKInXUt4Nzh+53dYUXikedQrYxuYFbNDgtfGkvW q1glv/BM86g9gmTWlUYID6oYjq8xZmUtWAKNt/4GEa/uY1euCRFjrsqSG E/IkmXaYHIYS9oOHGyb5lu9lZa0eIEaeI3Wt5dhc9koAtaPcLoOI7woYp g==; X-CSE-ConnectionGUID: wNfd+jCsRiWEXMNUBP5DNg== X-CSE-MsgGUID: n+pSyMdtR/KhPy3oIEgnMA== X-IronPort-AV: E=Sophos;i="6.17,258,1747724400"; d="scan'208";a="212197476" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2025 03:04:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 4 Aug 2025 03:04:04 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 4 Aug 2025 03:03:58 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , CC: Subject: [PATCH 15/15] ARM: dts: microchip: sama7d65: add thermal zones node Date: Mon, 4 Aug 2025 15:32:19 +0530 Message-ID: <20250804100219.63325-16-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250804100219.63325-1-varshini.rajendran@microchip.com> References: <20250804100219.63325-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add thermal zones node with its associated trips and cooling-maps. It uses CPUFreq as cooling device for temperatures in the interval [90, 100) degrees Celsius and describe the temperature of 100 degrees Celsius as critical temperature. System will be is shutting down when reaching critical temperature. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index aefdd72cb59c..a4e5ef6a9cf2 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include =20 / { model =3D "Microchip SAMA7D65 family SoC"; @@ -35,6 +36,7 @@ cpu0: cpu@0 { clocks =3D <&pmc PMC_TYPE_CORE PMC_CPUPLL>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; /* min followed by max */ }; }; =20 @@ -110,6 +112,46 @@ thermal_sensor: thermal-sensor { io-channel-names =3D "sensor-channel"; }; =20 + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <5000>; + thermal-sensors =3D <&thermal_sensor>; + + trips { + cpu_normal: cpu-alert0 { + temperature =3D <90000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + cpu_hot: cpu-alert1 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + cpu_critical: cpu-critical { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_normal>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip =3D <&cpu_hot>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible =3D "simple-bus"; ranges; --=20 2.34.1