From nobody Fri Oct 3 21:53:43 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A099124061F; Mon, 4 Aug 2025 08:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754295595; cv=none; b=DcxI2XDIeFQS9MdD36vgLb5gE5hAhABfga2eROvpyek9rjd55UhTX2Ih9A2Q6i9lxQgM8fNCD0ELbagJ/LAj8sQ5eczUVMiD9uQ/yPEGbTZnuXBtALdidVvqLAw3sS+/9GdB73PupCNOWATI/OUqO1ZT39OClNxRv+TVwKGpeGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754295595; c=relaxed/simple; bh=ML9f86fga0rWxdP6xgzsz3Q5IKb0hEn1AmRpdMyCVe8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QKcnttY1p5QdirWKQrocCxLzqTnnz26TsgspENfJ1CbVDOTEkTxZi/FAX8QwCqgPqTa/JDT601XWZtUXq4IGtUzLEzz1FJGn+9M81ycUzUoS1AgVQSCI9sTT71aUciVZfKqRKxQMNRTUq5CzFWiTSCJXGrJhVITebMNlV32r4Bw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxrOImbZBoBjk4AQ--.4724S3; Mon, 04 Aug 2025 16:19:50 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxE+QibZBoTUU1AA--.65480S3; Mon, 04 Aug 2025 16:19:48 +0800 (CST) From: Bibo Mao To: Huacai Chen , Jianmin Lv Cc: WANG Xuerui , Thomas Gleixner , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v4 1/2] irqchip/loongson-eiointc: Route interrupt parsed from bios table Date: Mon, 4 Aug 2025 16:19:45 +0800 Message-Id: <20250804081946.1456573-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250804081946.1456573-1-maobibo@loongson.cn> References: <20250804081946.1456573-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+QibZBoTUU1AA--.65480S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Interrupt controller eiointc routes irq to cpu interface IP0 - IP7, now it is hard-coded that eiointc routes irq to CPU started from IP1, however with function irq_create_mapping() parameter parent hwirq uses irq parsed from ACPI or DTS table. Routed interrupt pin need be the consistent with parent hwirq. Signed-off-by: Bibo Mao --- drivers/irqchip/irq-loongson-eiointc.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-l= oongson-eiointc.c index b2860eb2d32c..3e987d1232d2 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -68,6 +68,7 @@ struct eiointc_priv { struct fwnode_handle *domain_handle; struct irq_domain *eiointc_domain; int flags; + irq_hw_number_t parent_hwirq; }; =20 static struct eiointc_priv *eiointc_priv[MAX_IO_PICS]; @@ -211,7 +212,12 @@ static int eiointc_router_init(unsigned int cpu) } =20 for (i =3D 0; i < eiointc_priv[0]->vec_count / 32 / 4; i++) { - bit =3D BIT(1 + index); /* Route to IP[1 + index] */ + /* + * Route to interrupt pin, relative offset used here + * Offset 0 means routing to IP0 and so on + * Every 32 vector routing to one interrupt pin + */ + bit =3D BIT(eiointc_priv[index]->parent_hwirq - INT_HWI0); data =3D bit | (bit << 8) | (bit << 16) | (bit << 24); iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4); } @@ -495,7 +501,7 @@ int __init eiointc_acpi_init(struct irq_domain *parent, =20 priv->vec_count =3D VEC_COUNT; priv->node =3D acpi_eiointc->node; - + priv->parent_hwirq =3D acpi_eiointc->cascade; parent_irq =3D irq_create_mapping(parent, acpi_eiointc->cascade); =20 ret =3D eiointc_init(priv, parent_irq, acpi_eiointc->node_map); @@ -529,6 +535,7 @@ static int __init eiointc_of_init(struct device_node *o= f_node, { int parent_irq, ret; struct eiointc_priv *priv; + struct irq_data *irq_data; =20 priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -544,6 +551,12 @@ static int __init eiointc_of_init(struct device_node *= of_node, if (ret < 0) goto out_free_priv; =20 + irq_data =3D irq_get_irq_data(parent_irq); + if (!irq_data) { + ret =3D -ENODEV; + goto out_free_priv; + } + /* * In particular, the number of devices supported by the LS2K0500 * extended I/O interrupt vector is 128. @@ -552,7 +565,7 @@ static int __init eiointc_of_init(struct device_node *o= f_node, priv->vec_count =3D 128; else priv->vec_count =3D VEC_COUNT; - + priv->parent_hwirq =3D irqd_to_hwirq(irq_data); priv->node =3D 0; priv->domain_handle =3D of_fwnode_handle(of_node); =20 --=20 2.39.3 From nobody Fri Oct 3 21:53:43 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B2AE724169D; Mon, 4 Aug 2025 08:19:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754295596; cv=none; b=U4EzYhxsLEUbF5Sh2YEerKfJpMCkZVWupiQIPEQDwLwxTRWByJTeIucyqXA80A6Np40tPpD03TMgTU98OQig0Ngpm6CKwzmQbOPt3P2JdZbpae8f+6TSey3z0F5hL061/hZtjDcMbpfMjDVNX6IItO+ERdttwCOawxr3E2Zc6us= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754295596; c=relaxed/simple; bh=EKzbjCEqk8Zq/vTSVpCSgeMGR8CteBm7Ue5WS/8OIgk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gGaJZfIMyCI3xwdXjSQQf+NDMSNb+lEvAIgev5kTBZ/v9PdVqUTbXPXgRCyjTc0pXltTOymXmLawCQ96EsgVy6P+JuyvRWTjEXcvH9dp0F1Gpun32nGjfGRfsvtghe15T3wvoZTFqw9wXitGj8EXATjbG8SGfcnDurfIBmTkHy8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxaWonbZBoCzk4AQ--.49484S3; Mon, 04 Aug 2025 16:19:51 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxE+QibZBoTUU1AA--.65480S4; Mon, 04 Aug 2025 16:19:50 +0800 (CST) From: Bibo Mao To: Huacai Chen , Jianmin Lv Cc: WANG Xuerui , Thomas Gleixner , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v4 2/2] irqchip/loongson-eiointc: Add multiple interrupt pin routing support Date: Mon, 4 Aug 2025 16:19:46 +0800 Message-Id: <20250804081946.1456573-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250804081946.1456573-1-maobibo@loongson.cn> References: <20250804081946.1456573-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+QibZBoTUU1AA--.65480S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Eiointc interrupt controller support 256 interrupt vectors at most, and irq handler gets interrupt status from base register group EIOINTC_REG_ISR plus specific offset. It needs to read register group EIOINTC_REG_ISR four times to get all 256 interrupt vectors status. Eiointc registers including EIOINTC_REG_ISR is software emulated for VMs, there will be VM-exits when accessing eiointc registers. Here one method is introduced so that eiointc interrupt controller can route to different cpu interrupt pins for every 64 interrupt vectors. So irq handler knows interrupt pin information and reads specific EIOINTC_REG_ISR register. And there is only once EIOINTC_REG_ISR register access rather than four loop times, it reduces VM-exit times. Signed-off-by: Bibo Mao --- drivers/irqchip/irq-loongson-eiointc.c | 81 +++++++++++++++++++++++--- 1 file changed, 74 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-l= oongson-eiointc.c index 3e987d1232d2..081787ecdcdd 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -46,6 +46,7 @@ #define EIOINTC_ALL_ENABLE_VEC_MASK(vector) (EIOINTC_ALL_ENABLE & ~BIT(vec= tor & 0x1f)) #define EIOINTC_REG_ENABLE_VEC(vector) (EIOINTC_REG_ENABLE + ((vector >> = 5) << 2)) #define EIOINTC_USE_CPU_ENCODE BIT(0) +#define EIOINTC_ROUTE_MULT_IP BIT(1) =20 #define MAX_EIO_NODES (NR_CPUS / CORES_PER_EIO_NODE) =20 @@ -59,6 +60,13 @@ #define EIOINTC_REG_ROUTE_VEC_MASK(vector) (0xff << EIOINTC_REG_ROUTE_VEC_= SHIFT(vector)) =20 static int nr_pics; +struct eiointc_priv; +struct eiointc_ip_route { + struct eiointc_priv *priv; + /* Offset Routed destination IP */ + int start; + int end; +}; =20 struct eiointc_priv { u32 node; @@ -69,6 +77,7 @@ struct eiointc_priv { struct irq_domain *eiointc_domain; int flags; irq_hw_number_t parent_hwirq; + struct eiointc_ip_route route_info[VEC_REG_COUNT]; }; =20 static struct eiointc_priv *eiointc_priv[MAX_IO_PICS]; @@ -189,6 +198,7 @@ static int eiointc_router_init(unsigned int cpu) { int i, bit, cores, index, node; unsigned int data; + int hwirq, mask; =20 node =3D cpu_to_eio_node(cpu); index =3D eiointc_index(node); @@ -198,6 +208,13 @@ static int eiointc_router_init(unsigned int cpu) return -EINVAL; } =20 + /* Enable cpu interrupt pin from eiointc */ + hwirq =3D eiointc_priv[index]->parent_hwirq; + mask =3D BIT(hwirq); + if (eiointc_priv[index]->flags & EIOINTC_ROUTE_MULT_IP) + mask |=3D BIT(hwirq + 1) | BIT(hwirq + 2) | BIT(hwirq + 3); + set_csr_ecfg(mask); + if (!(eiointc_priv[index]->flags & EIOINTC_USE_CPU_ENCODE)) cores =3D CORES_PER_EIO_NODE; else @@ -215,10 +232,28 @@ static int eiointc_router_init(unsigned int cpu) /* * Route to interrupt pin, relative offset used here * Offset 0 means routing to IP0 and so on - * Every 32 vector routing to one interrupt pin + * + * If flags is set with EIOINTC_ROUTE_MULT_IP, + * every 64 vector routes to different consecutive + * IPs, otherwise all vector routes to the same IP */ - bit =3D BIT(eiointc_priv[index]->parent_hwirq - INT_HWI0); - data =3D bit | (bit << 8) | (bit << 16) | (bit << 24); + if (eiointc_priv[index]->flags & EIOINTC_ROUTE_MULT_IP) { + /* The first 64 vectors route to hwirq */ + bit =3D BIT(hwirq++ - INT_HWI0); + data =3D bit | (bit << 8); + + /* The second 64 vectors route to hwirq + 1 */ + bit =3D BIT(hwirq++ - INT_HWI0); + data |=3D (bit << 16) | (bit << 24); + + /* + * Route to hwirq + 2/hwirq + 3 separately + * in next loop + */ + } else { + bit =3D BIT(hwirq - INT_HWI0); + data =3D bit | (bit << 8) | (bit << 16) | (bit << 24); + } iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4); } =20 @@ -251,11 +286,18 @@ static void eiointc_irq_dispatch(struct irq_desc *des= c) u64 pending; bool handled =3D false; struct irq_chip *chip =3D irq_desc_get_chip(desc); - struct eiointc_priv *priv =3D irq_desc_get_handler_data(desc); + struct eiointc_ip_route *info =3D irq_desc_get_handler_data(desc); =20 chained_irq_enter(chip, desc); =20 - for (i =3D 0; i < eiointc_priv[0]->vec_count / VEC_COUNT_PER_REG; i++) { + /* + * If EIOINTC_ROUTE_MULT_IP is set, every 64 interrupt vectors in + * eiointc interrupt controller routes to different cpu interrupt pins + * + * Every cpu interrupt pin has its own irq handler, it is ok to + * read ISR for these 64 interrupt vectors rather than all vectors + */ + for (i =3D info->start; i < info->end; i++) { pending =3D iocsr_read64(EIOINTC_REG_ISR + (i << 3)); =20 /* Skip handling if pending bitmap is zero */ @@ -268,7 +310,7 @@ static void eiointc_irq_dispatch(struct irq_desc *desc) int bit =3D __ffs(pending); int irq =3D bit + VEC_COUNT_PER_REG * i; =20 - generic_handle_domain_irq(priv->eiointc_domain, irq); + generic_handle_domain_irq(info->priv->eiointc_domain, irq); pending &=3D ~BIT(bit); handled =3D true; } @@ -468,8 +510,33 @@ static int __init eiointc_init(struct eiointc_priv *pr= iv, int parent_irq, } =20 eiointc_priv[nr_pics++] =3D priv; + /* + * Only the first eiointc device on VM supports routing to + * different Interrupt Pins. The later eiointc devices use + * generic method if there are multiple eiointc devices in future + */ + if (cpu_has_hypervisor && (nr_pics =3D=3D 1)) { + priv->flags |=3D EIOINTC_ROUTE_MULT_IP; + priv->parent_hwirq =3D INT_HWI0; + } + + if (priv->flags & EIOINTC_ROUTE_MULT_IP) { + for (i =3D 0; i < priv->vec_count / VEC_COUNT_PER_REG; i++) { + priv->route_info[i].start =3D priv->parent_hwirq - INT_HWI0 + i; + priv->route_info[i].end =3D priv->route_info[i].start + 1; + priv->route_info[i].priv =3D priv; + parent_irq =3D get_percpu_irq(priv->parent_hwirq + i); + irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, + &priv->route_info[i]); + } + } else { + priv->route_info[0].start =3D 0; + priv->route_info[0].end =3D priv->vec_count / VEC_COUNT_PER_REG; + priv->route_info[0].priv =3D priv; + irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, + &priv->route_info[0]); + } eiointc_router_init(0); - irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv); =20 if (nr_pics =3D=3D 1) { register_syscore_ops(&eiointc_syscore_ops); --=20 2.39.3