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charset="utf-8" Add Operation State Manager (OSM) L3 interconnect provider binding for QCS615 SoC. As the OSM hardware in QCS615 and SM8150 are same, added a family-level compatible for SM8150 SoC. This shared fallback compatible allows grouping of SoCs with similar hardware, reducing the need to explicitly list each variant in the driver match table. Signed-off-by: Raviteja Laggyshetty --- .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index ab5a921c3495..4b9b98fbe8f2 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -41,6 +41,11 @@ properties: - qcom,qcs8300-epss-l3 - const: qcom,sa8775p-epss-l3 - const: qcom,epss-l3 + - items: + - enum: + - qcom,qcs615-osm-l3 + - const: qcom,sm8150-osm-l3 + - const: qcom,osm-l3 =20 reg: maxItems: 1 --=20 2.43.0 From nobody Sun Oct 5 12:52:24 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28A04153BED for ; Mon, 4 Aug 2025 05:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add Operation State Manager (OSM) L3 interconnect provide node and OPP tables required to scale DDR and L3 per freq-domain on QCS615 SoC. As QCS615 and SM8150 SoCs have same OSM hardware, added SM8150 compatible as fallback for QCS615 OSM device node. Signed-off-by: Raviteja Laggyshetty Signed-off-by: Imran Shaik --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 148 +++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index e033b53f0f0f..d81e7daf9b5c 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,10 @@ cpu0: cpu@0 { dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_0: l2-cache { compatible =3D "cache"; @@ -52,6 +57,10 @@ cpu1: cpu@100 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_100>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -71,6 +80,10 @@ cpu2: cpu@200 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_200>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -90,6 +103,10 @@ cpu3: cpu@300 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_300>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -109,6 +126,10 @@ cpu4: cpu@400 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_400>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_400: l2-cache { compatible =3D "cache"; @@ -128,6 +149,10 @@ cpu5: cpu@500 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_500>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_500: l2-cache { compatible =3D "cache"; @@ -148,6 +173,10 @@ cpu6: cpu@600 { dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_600>; #cooling-cells =3D <2>; + operating-points-v2 =3D <&cpu6_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_600: l2-cache { compatible =3D "cache"; @@ -167,6 +196,10 @@ cpu7: cpu@700 { capacity-dmips-mhz =3D <1740>; dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_700>; + operating-points-v2 =3D <&cpu6_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; =20 l2_700: l2-cache { compatible =3D "cache"; @@ -219,6 +252,111 @@ l3_0: l3-cache { }; }; =20 + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-peak-kBps =3D <(300000 * 4) (300000 * 16)>; + }; + + opp-576000000 { + opp-hz =3D /bits/ 64 <576000000>; + opp-peak-kBps =3D <(300000 * 4) (576000 * 16)>; + }; + + opp-748800000 { + opp-hz =3D /bits/ 64 <748800000>; + opp-peak-kBps =3D <(300000 * 4) (576000 * 16)>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + opp-peak-kBps =3D <(451000 * 4) (806400 * 16)>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + opp-peak-kBps =3D <(547000 * 4) (1017600 * 16)>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <(768000 * 4) (1209600 * 16)>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + opp-peak-kBps =3D <(768000 * 4) (1209600 * 16)>; + }; + + opp-1593600000 { + opp-hz =3D /bits/ 64 <1593600000>; + opp-peak-kBps =3D <(1017000 * 4) (1363200 * 16)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-peak-kBps =3D <(451000 * 4) (300000 * 16)>; + }; + + opp-652800000 { + opp-hz =3D /bits/ 64 <652800000>; + opp-peak-kBps =3D <(451000 * 4) (576000 * 16)>; + }; + + opp-768000000 { + opp-hz =3D /bits/ 64 <768000000>; + opp-peak-kBps =3D <(451000 * 4) (576000 * 16)>; + }; + + opp-979200000 { + opp-hz =3D /bits/ 64 <979200000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 16)>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 16)>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <109440000>; + opp-peak-kBps =3D <(1017600 * 4) (940800 * 16)>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + opp-peak-kBps =3D <(1017600 * 4) (1017600 * 16)>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 16)>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 16)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(1555000 * 4) (1363200 * 16)>; + }; + + opp-1900800000 { + opp-hz =3D /bits/ 64 <1900800000>; + opp-peak-kBps =3D <(1555000 * 4) (1363200 * 16)>; + }; + }; + dummy_eud: dummy-sink { compatible =3D "arm,coresight-dummy-sink"; =20 @@ -3624,6 +3762,16 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; =20 + osm_l3: interconnect@18321000 { + compatible =3D "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3= "; + reg =3D <0 0x18321000 0 0x1400>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #interconnect-cells =3D <1>; + }; + usb_1_hsphy: phy@88e2000 { compatible =3D "qcom,qcs615-qusb2-phy"; reg =3D <0x0 0x88e2000 0x0 0x180>; --=20 2.43.0