From nobody Sun Oct 5 16:14:13 2025 Received: from dvalin.narfation.org (dvalin.narfation.org [213.160.73.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0722E21D3F8; Sat, 2 Aug 2025 10:42:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.160.73.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754131346; cv=none; b=EiYFhE/ooPmUZOrhrrTmPuVs6WKwpoX2Zvhi9VYLzvwPNnHT+ofajGPLsy37srut8kpVHBMojekeKZHGdYudDO4owF0b7V4M9DVYgDW22eRD5ypijQiD3rvRHHLd6YTs4YN9R222qsJviOrFsojEwOChrEg+A8UGe9hcCtEQkZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754131346; c=relaxed/simple; bh=M0ExxDwTq+EgVN8lGTAmv4NykEunoEBCeVqoYoEzVV8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AAFyq5EUhzcUa19jqNyrgrSK9vBqCOq6SFrfFSXHFruaz0bPVCgh/RtXied0JusMQYg2gza4oYbcGCg+Z6jAcMLvV+ypSJbuOM3vTaVjJvD4GNJjhgtjULQ94btfegbT45IzB7TEgOe/3mogPCkri3whV7kPDOXXU4QaQ9x4dYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=narfation.org; spf=pass smtp.mailfrom=narfation.org; dkim=pass (1024-bit key) header.d=narfation.org header.i=@narfation.org header.b=fB40SNN2; arc=none smtp.client-ip=213.160.73.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=narfation.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=narfation.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=narfation.org header.i=@narfation.org header.b="fB40SNN2" Received: from sven-desktop.home.narfation.org (unknown [IPv6:2a00:1ca0:1d86:99fc::8c24]) by dvalin.narfation.org (Postfix) with UTF8SMTPSA id D22F721796; Sat, 2 Aug 2025 10:32:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=narfation.org; s=20121; t=1754130741; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EOSCWi+cF2PB35Nc47+WAwgactGXBAdhUs+k7UcT1bA=; b=fB40SNN2iRDnG8l+IM3I2mcVINhp60BhxnhHfIjixbAA/rtuD/6LXGfLsWfxGideg4meAX rQPV63+6+LislFRmCOS2Ui9SB8UmuJ9rgcC0d2LhbTvDjdHenwKosToBNU1aGmGF3tHiQy SVbSxM61nHvqZ2m5ar4EtPdhvVId7ro= From: Sven Eckelmann Date: Sat, 02 Aug 2025 12:32:00 +0200 Subject: [PATCH 1/4] i2c: rtl9300: Fix multi-byte I2C write Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250802-i2c-rtl9300-multi-byte-v1-1-5f687e0098e2@narfation.org> References: <20250802-i2c-rtl9300-multi-byte-v1-0-5f687e0098e2@narfation.org> In-Reply-To: <20250802-i2c-rtl9300-multi-byte-v1-0-5f687e0098e2@narfation.org> To: Chris Packham , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Jonas Jelonek , Harshal Gohel , Simon Wunderlich , Sven Eckelmann , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2587; i=sven@narfation.org; h=from:subject:message-id; bh=fvbdbX5YpMEdiI0iyuFqcxzjPuLZ5q8XQBDJiObeHFE=; b=owGbwMvMwCXmy1+ufVnk62nG02pJDBm9L026bW4tvJNXs/i02w/G8hPThRab8Qnd+vy6yNlwc 1Rq8uHTHaUsDGJcDLJiiix7ruSf38z+Vv7ztI9HYeawMoEMYeDiFICJhHoz/M++aXzb6K3FKsmS 9z522dPtJ29TW7olU/Pu8nn7OiRWXtrJyHBnnY/X4k8RS6xOlehJSQSIXTWOmtT1MiOTM/oDRz3 rDgYA X-Developer-Key: i=sven@narfation.org; a=openpgp; fpr=522D7163831C73A635D12FE5EC371482956781AF From: Harshal Gohel The RTL93xx I2C controller has 4 32 bit registers to store the bytes for the upcoming I2C transmission. The first byte is stored in the least-significant byte of the first register. And the last byte in the most significant byte of the last register. A map of the transferred bytes to their order in the registers is: reg 0: 04-03-02-01 reg 1: 08-07-06-05 reg 2: 0c-0b-0a-09 reg 3: 10-0f-0e-0d The i2c_read() function basically demonstrates how the hardware would pick up bytes from this register set. But the i2c_write() function was just pushing bytes one after another to the least significant byte of a register AFTER shifting the last one to the next more significant byte position. If you would then have tried to send a buffer with numbers 1-11 using i2c_write(), you would have ended up with following register content: reg 0: 01-02-03-04 reg 1: 05-06-07-08 reg 2: 00-09-0a-0b reg 3: 00-00-00-00 On the wire, you would then have seen: Sr Addr Rd/Wr [A] 04 A 03 A 02 A 01 A 08 A 07 A 06 A 05 A 0b A 0a A 09 A/= NA P But the correct data transmission was expected to be Sr Addr Rd/Wr [A] 01 A 02 A 03 A 04 A 05 A 06 A 07 A 08 A 09 A 0a A 0b A/= NA P Because of this multi-byte ordering problem, only single byte i2c_write() operations were executed correctly (on the wire). By shifting the byte directly to the correct end position in the register, it is possible to avoid this incorrect byte ordering and fix multi-byte transmissions. Cc: Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") Signed-off-by: Harshal Gohel Co-developed-by: Sven Eckelmann Signed-off-by: Sven Eckelmann --- drivers/i2c/busses/i2c-rtl9300.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9= 300.c index e064e8a4a1f0824abc82fa677866b85f99fbe4a7..1b3cbe3ea84a4fa480c5c00438e= ecc551d047348 100644 --- a/drivers/i2c/busses/i2c-rtl9300.c +++ b/drivers/i2c/busses/i2c-rtl9300.c @@ -143,10 +143,13 @@ static int rtl9300_i2c_write(struct rtl9300_i2c *i2c,= u8 *buf, int len) return -EIO; =20 for (i =3D 0; i < len; i++) { + unsigned int shift =3D (i % 4) * 8; + unsigned int reg =3D i / 4; + if (i % 4 =3D=3D 0) - vals[i/4] =3D 0; - vals[i/4] <<=3D 8; - vals[i/4] |=3D buf[i]; + vals[reg] =3D 0; + + vals[reg] |=3D buf[i] << shift; } =20 return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DAT= A_WORD0, --=20 2.47.2