From nobody Sun Oct 5 16:21:04 2025 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 961B11F463C; Fri, 1 Aug 2025 08:00:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754035246; cv=none; b=SMANxehJzOqGeEye3PfKZEq/IofFJA5X1RR0OTbN6bPzLIoUaXQm3F2noaFLwa1ZtzdjkK8/xl9CvEihY7nYS+/GElG7pQQmaHSggJ6OWBUJyRmGlb1rzAfZrED+JpFphawB+0G0Z/ISPvWwmhS2NVmTE2+HLoLYPPARcaxD6+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754035246; c=relaxed/simple; bh=2L39Ez1zOU0jFsZA/M795n6ybw7xsCMC+J217yfHENQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Kv10di6fi1tIoktttRxp1E2sl+Q7W4PQqd/bUoKiCaOLkCixDNPMWCL8JU4VdeXtFqeWzZ1jjxwbrF7GCrz8Yx13j4JhEwllwWtDp53UOwhImA+ufdzDmDPp+YsbkZLypeTypGaqayOZozGftoUFo3mwpB30vrl5P86XxNsbflI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from localhost.localdomain (unknown [119.122.213.139]) by smtp.qiye.163.com (Hmail) with ESMTP id 1dfa26365; Fri, 1 Aug 2025 16:00:32 +0800 (GMT+08:00) From: Chukun Pan To: Heiko Stuebner Cc: Yao Zi , Rob Herring , Chukun Pan , Jonas Karlman , Conor Dooley , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 1/1] arm64: dts: rockchip: rk3528: Add CPU frequency scaling support Date: Fri, 1 Aug 2025 16:00:25 +0800 Message-Id: <20250801080025.558935-2-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250801080025.558935-1-amadeus@jmu.edu.cn> References: <20250801080025.558935-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9864a5a04803a2kunm02af6e1563592 X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCQ09IVkJNSkxIS0sZQkpPS1YeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKSFVKSEJZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0tVSktLVU tZBg++ Content-Type: text/plain; charset="utf-8" By default, the CPUs on RK3528 operates at 1.5GHz. Add CPU frequency and voltage mapping to the device tree to enable dynamic scaling via cpufreq. The OPP values come from downstream kernel[1], using a voltage close to the actual frequency. Frequencies below 1.2GHz have been removed due to the same voltage. [1] https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/b= oot/dts/rockchip/rk3528.dtsi Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index 001a555c83b7..15fd9f99beaa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -53,6 +53,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; enable-method =3D "psci"; clocks =3D <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 cpu1: cpu@1 { @@ -61,6 +62,7 @@ cpu1: cpu@1 { device_type =3D "cpu"; enable-method =3D "psci"; clocks =3D <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 cpu2: cpu@2 { @@ -69,6 +71,7 @@ cpu2: cpu@2 { device_type =3D "cpu"; enable-method =3D "psci"; clocks =3D <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 cpu3: cpu@3 { @@ -77,6 +80,7 @@ cpu3: cpu@3 { device_type =3D "cpu"; enable-method =3D "psci"; clocks =3D <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 =3D <&cpu_opp_table>; }; }; =20 @@ -95,6 +99,41 @@ scmi_clk: protocol@14 { }; }; =20 + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <875000 875000 1100000>; + clock-latency-ns =3D <40000>; + }; + + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <925000 925000 1100000>; + clock-latency-ns =3D <40000>; + }; + + opp-1608000000 { + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <975000 975000 1100000>; + clock-latency-ns =3D <40000>; + }; + + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1037500 1037500 1100000>; + clock-latency-ns =3D <40000>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-microvolt =3D <1100000 1100000 1100000>; + clock-latency-ns =3D <40000>; + }; + }; + gpu_opp_table: opp-table-gpu { compatible =3D "operating-points-v2"; =20 --=20 2.25.1