From nobody Sun Oct 5 18:16:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFEBB1EF0B0; Fri, 1 Aug 2025 04:36:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754023011; cv=none; b=PciPoJxZkMC900GbBngSUAtlNviUKRwOH9993xwuqXhYDN1JBlbdkSapFx4f8M/X0m3vjSRWB1LWqt3/CTqFm0Z/+rxRyfqk8iEy00oI+xwXWXtqx7JhG1h+5pNFUoDBZjwPXKKRrk5Nw7L+5gxx+zU9nMLKeNQozkZa9C0nGbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754023011; c=relaxed/simple; bh=fMrb/PuPQ+UKs6MUav0oTfeMY0ykBikhZCJCGvSTauY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YDyCB9mCexOESBKgVfrAN63xlqRqVUsGcMPqCK6lRuTa17TQlCmRd0g5qypteq67gmXfkHPmC2QpPzMmVoBTD/BI4j4chgTZ2vq5HLiplTfm4Gj3zWPmxAok996/vE7CjGX9VI4ysfQoNyU3p/gU9MhHhXp25hceDVkjzcGYdlU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cce28Kmq; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cce28Kmq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754023010; x=1785559010; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fMrb/PuPQ+UKs6MUav0oTfeMY0ykBikhZCJCGvSTauY=; b=cce28KmqBgXUFrnipD/j+PfDsY04WqJlrBSEy7I+xZxWSIZ+JKEz2xpG MCz5paIRR/qu+Nf9cPPcskmmeUGXj6Xtp6oRS5h6xC3wDQgI8mYF1yAbk zXu1HL+FpEpu3MKIWG8F3zSVyKgtQ87OTz3K54UD3gjMNBWbdRgVJxden FJ0ijVxEncvwGV4V6pf7AM9QFiZs+LH7+rc1/wnNWWI6i+KhM9ofiEbc6 IiDZ60uCnGDgTUCO5hYAFqSsHJrlbBQioBmdRtPR2GK7RE3LhX0uQxkk8 5IXSWi/yk9Z6eRXbx9sgX3s/ST8Ru91pR95Tt7QUJ2yPfgaTOM+kV1acY Q==; X-CSE-ConnectionGUID: hUPfMk3SR6ixAs/1L897Cw== X-CSE-MsgGUID: 527e7tPeR3eO1pydj6x/Cg== X-IronPort-AV: E=McAfee;i="6800,10657,11508"; a="73820181" X-IronPort-AV: E=Sophos;i="6.17,255,1747724400"; d="scan'208";a="73820181" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 21:36:44 -0700 X-CSE-ConnectionGUID: XvUMAi7iSKOQbBalD1WFgw== X-CSE-MsgGUID: 5qZAAxefTmGEOzKcjCI8lQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,255,1747724400"; d="scan'208";a="163796234" Received: from jf5300-b11a338t.jf.intel.com ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 31 Jul 2025 21:36:43 -0700 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosry.ahmed@linux.dev, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, 21cnbao@gmail.com, ying.huang@linux.alibaba.com, akpm@linux-foundation.org, senozhatsky@chromium.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, vinicius.gomes@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v11 04/24] crypto: iaa - Descriptor allocation timeouts with mitigations. Date: Thu, 31 Jul 2025 21:36:22 -0700 Message-Id: <20250801043642.8103-5-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20250801043642.8103-1-kanchana.p.sridhar@intel.com> References: <20250801043642.8103-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch modifies the descriptor allocation from blocking to non-blocking with bounded retries or "timeouts". This is necessary to prevent task blocked errors in high contention scenarios, for instance, when the platform has only 1 IAA device enabled. With 1 IAA device enabled per package on a dual-package Sapphire Rapids with 56 cores/package, there are 112 logical cores mapped to this single IAA device. In this scenario, the task blocked errors can occur because idxd_alloc_desc() is called with IDXD_OP_BLOCK. With batching, multiple descriptors will need to be allocated per batch. Any process that is able to do so, can cause contention for allocating descriptors for all other processes that share the use of the same sbitmap_queue. Under IDXD_OP_BLOCK, this causes compress/decompress jobs to stall in stress test scenarios (e.g. zswap_store() of 2M folios). In order to make the iaa_crypto driver be more fail-safe, this commit implements the following: 1) Change compress/decompress descriptor allocations to be non-blocking with retries ("timeouts"). 2) Return compress error to zswap if descriptor allocation with timeouts fails during compress ops. zswap_store() will return an error and the folio gets stored in the backing swap device. 3) Fallback to software decompress if descriptor allocation with timeouts fails during decompress ops. With these fixes, there are no task blocked errors seen under stress testing conditions, and no performance degradation observed. Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto.h | 5 ++ drivers/crypto/intel/iaa/iaa_crypto_main.c | 58 +++++++++++++++------- 2 files changed, 44 insertions(+), 19 deletions(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto.h b/drivers/crypto/intel/i= aa/iaa_crypto.h index 549ac98a9366e..cc76a047b54ad 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto.h +++ b/drivers/crypto/intel/iaa/iaa_crypto.h @@ -21,6 +21,9 @@ =20 #define IAA_COMPLETION_TIMEOUT 1000000 =20 +#define IAA_ALLOC_DESC_COMP_TIMEOUT 1000 +#define IAA_ALLOC_DESC_DECOMP_TIMEOUT 500 + #define IAA_ANALYTICS_ERROR 0x0a #define IAA_ERROR_DECOMP_BUF_OVERFLOW 0x0b #define IAA_ERROR_COMP_BUF_OVERFLOW 0x19 @@ -141,6 +144,8 @@ enum iaa_mode { =20 struct iaa_compression_ctx { enum iaa_mode mode; + u16 alloc_comp_desc_timeout; + u16 alloc_decomp_desc_timeout; bool verify_compress; bool async_mode; bool use_irq; diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index ed3325bb32918..1169cd44c8e78 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -1596,7 +1596,8 @@ static int iaa_compress_verify(struct crypto_tfm *tfm= , struct acomp_req *req, struct iaa_compression_ctx *ctx =3D crypto_tfm_ctx(tfm); u32 *compression_crc =3D acomp_request_ctx(req); struct iaa_device *iaa_device; - struct idxd_desc *idxd_desc; + struct idxd_desc *idxd_desc =3D ERR_PTR(-EAGAIN); + u16 alloc_desc_retries =3D 0; struct iax_hw_desc *desc; struct idxd_device *idxd; struct iaa_wq *iaa_wq; @@ -1612,7 +1613,11 @@ static int iaa_compress_verify(struct crypto_tfm *tf= m, struct acomp_req *req, =20 active_compression_mode =3D get_iaa_device_compression_mode(iaa_device, c= tx->mode); =20 - idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_BLOCK); + while ((idxd_desc =3D=3D ERR_PTR(-EAGAIN)) && (alloc_desc_retries++ < ctx= ->alloc_decomp_desc_timeout)) { + idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_NONBLOCK); + cpu_relax(); + } + if (IS_ERR(idxd_desc)) { dev_dbg(dev, "iaa compress_verify failed: idxd descriptor allocation fai= lure: ret=3D%ld\n", PTR_ERR(idxd_desc)); return -ENODEV; @@ -1772,7 +1777,8 @@ static int iaa_compress(struct crypto_tfm *tfm, struc= t acomp_req *req, struct iaa_compression_ctx *ctx =3D crypto_tfm_ctx(tfm); u32 *compression_crc =3D acomp_request_ctx(req); struct iaa_device *iaa_device; - struct idxd_desc *idxd_desc; + struct idxd_desc *idxd_desc =3D ERR_PTR(-EAGAIN); + u16 alloc_desc_retries =3D 0; struct iax_hw_desc *desc; struct idxd_device *idxd; struct iaa_wq *iaa_wq; @@ -1788,7 +1794,11 @@ static int iaa_compress(struct crypto_tfm *tfm, stru= ct acomp_req *req, =20 active_compression_mode =3D get_iaa_device_compression_mode(iaa_device, c= tx->mode); =20 - idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_BLOCK); + while ((idxd_desc =3D=3D ERR_PTR(-EAGAIN)) && (alloc_desc_retries++ < ctx= ->alloc_comp_desc_timeout)) { + idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_NONBLOCK); + cpu_relax(); + } + if (IS_ERR(idxd_desc)) { dev_dbg(dev, "iaa compress failed: idxd descriptor allocation failure: r= et=3D%ld\n", PTR_ERR(idxd_desc)); @@ -1863,7 +1873,8 @@ static int iaa_decompress(struct crypto_tfm *tfm, str= uct acomp_req *req, struct iaa_device_compression_mode *active_compression_mode; struct iaa_compression_ctx *ctx =3D crypto_tfm_ctx(tfm); struct iaa_device *iaa_device; - struct idxd_desc *idxd_desc; + struct idxd_desc *idxd_desc =3D ERR_PTR(-EAGAIN); + u16 alloc_desc_retries =3D 0; struct iax_hw_desc *desc; struct idxd_device *idxd; struct iaa_wq *iaa_wq; @@ -1879,12 +1890,17 @@ static int iaa_decompress(struct crypto_tfm *tfm, s= truct acomp_req *req, =20 active_compression_mode =3D get_iaa_device_compression_mode(iaa_device, c= tx->mode); =20 - idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_BLOCK); + while ((idxd_desc =3D=3D ERR_PTR(-EAGAIN)) && (alloc_desc_retries++ < ctx= ->alloc_decomp_desc_timeout)) { + idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_NONBLOCK); + cpu_relax(); + } + if (IS_ERR(idxd_desc)) { ret =3D -ENODEV; dev_dbg(dev, "%s: idxd descriptor allocation failed: ret=3D%ld\n", __fun= c__, PTR_ERR(idxd_desc)); - return ret; + idxd_desc =3D NULL; + goto fallback_software_decomp; } desc =3D idxd_desc->iax_hw; =20 @@ -1913,7 +1929,7 @@ static int iaa_decompress(struct crypto_tfm *tfm, str= uct acomp_req *req, ret =3D idxd_submit_desc(wq, idxd_desc); if (ret) { dev_dbg(dev, "submit_desc failed ret=3D%d\n", ret); - goto err; + goto fallback_software_decomp; } =20 /* Update stats */ @@ -1926,19 +1942,21 @@ static int iaa_decompress(struct crypto_tfm *tfm, s= truct acomp_req *req, } =20 ret =3D check_completion(dev, idxd_desc->iax_completion, false, false); + +fallback_software_decomp: if (ret) { - dev_dbg(dev, "%s: check_completion failed ret=3D%d\n", __func__, ret); - if (idxd_desc->iax_completion->status =3D=3D IAA_ANALYTICS_ERROR) { + dev_dbg(dev, "%s: desc allocation/submission/check_completion failed ret= =3D%d\n", __func__, ret); + if (idxd_desc && idxd_desc->iax_completion->status =3D=3D IAA_ANALYTICS_= ERROR) { pr_warn("%s: falling back to deflate-generic decompress, " "analytics error code %x\n", __func__, idxd_desc->iax_completion->error_code); - ret =3D deflate_generic_decompress(req); - if (ret) { - dev_dbg(dev, "%s: deflate-generic failed ret=3D%d\n", - __func__, ret); - goto err; - } - } else { + } + + ret =3D deflate_generic_decompress(req); + + if (ret) { + pr_err("%s: iaa decompress failed: deflate-generic fallback error ret= =3D%d\n", + __func__, ret); goto err; } } else { @@ -2119,6 +2137,8 @@ static int iaa_comp_adecompress(struct acomp_req *req) =20 static void compression_ctx_init(struct iaa_compression_ctx *ctx) { + ctx->alloc_comp_desc_timeout =3D IAA_ALLOC_DESC_COMP_TIMEOUT; + ctx->alloc_decomp_desc_timeout =3D IAA_ALLOC_DESC_DECOMP_TIMEOUT; ctx->verify_compress =3D iaa_verify_compress; ctx->async_mode =3D async_mode; ctx->use_irq =3D use_irq; @@ -2133,10 +2153,10 @@ static int iaa_comp_init_fixed(struct crypto_acomp = *acomp_tfm) struct crypto_tfm *tfm =3D crypto_acomp_tfm(acomp_tfm); struct iaa_compression_ctx *ctx =3D crypto_tfm_ctx(tfm); =20 - compression_ctx_init(ctx); - ctx->mode =3D IAA_MODE_FIXED; =20 + compression_ctx_init(ctx); + return 0; } =20 --=20 2.27.0