From nobody Sun Oct 5 14:35:20 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DCCB269AFB; Fri, 1 Aug 2025 14:14:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.205.8.231 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754057688; cv=none; b=jPDLjN2DajTcywkzFvn1wb5ZrE940V8qV8T8pT4JhuzGndZQXljPkdsGiMLhJmz1Ky89UY9Euy/CvFkBBnq9bUecJHLhdj5o7Jipp5IxWQCYpiatSCU9IEcBpUruj7BzGar98HEageFnPynekLpfc8wXEb80eond6nueWc4HuuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754057688; c=relaxed/simple; bh=X8bDc3mEF7A+jWR5/Mtli4JbbUPbP/jIzLwqkvh83zk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D+UwoXC9j7axk86GxTW1y2DHaAcFAPGCjcD5m+tj1Ye4wVZaxZhKB6/TUIlWcwSQ/IAXYOLV0zBKfHMf1GiZj8gzgeVdJrOhNCnJdcwVNr2ZDjM1tOtXuU0b0i0SHZ7Dan0JHXyjlw/SzAZNOEFtPWb8jr/5jVjtxTuJ61IcEtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=dujemihanovic.xyz; spf=pass smtp.mailfrom=dujemihanovic.xyz; dkim=pass (2048-bit key) header.d=dujemihanovic.xyz header.i=@dujemihanovic.xyz header.b=i6N0iP0B; arc=none smtp.client-ip=37.205.8.231 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=dujemihanovic.xyz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dujemihanovic.xyz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dujemihanovic.xyz header.i=@dujemihanovic.xyz header.b="i6N0iP0B" DKIM-Signature: a=rsa-sha256; bh=xg6p9F3CDjFSzSKSOC4/hpt/VNg4sb7Ukef6jTBb/9A=; c=relaxed/relaxed; d=dujemihanovic.xyz; h=Subject:Subject:Sender:To:To:Cc:Cc:From:From:Date:Date:MIME-Version:MIME-Version:Content-Type:Content-Type:Content-Transfer-Encoding:Content-Transfer-Encoding:Reply-To:In-Reply-To:In-Reply-To:Message-Id:Message-Id:References:References:Autocrypt:Openpgp; i=@dujemihanovic.xyz; s=default; t=1754057669; v=1; x=1754489669; b=i6N0iP0BaDHQLYoTpRhu7egSc/yKlvNRbElMuGsRpE7zntaKAQ1+33b1r6asHzmD1aWpomZ3 2o3BPdTPTFI5mQFgjwNyLiYWEZTB74htkkRxFxeBc0qfmc5PE+E9Pi9LCeKiXD/WdoIF9ZybHLf PIKoCUfTZGLQMWeUfLN9ZkiXm6p+OATclFc6EkOmXySJqCg0W0G4gxNVF03tz4muok/Pjgi9DMe hwlgEXWv8M2ELBwLiOGQI+0TLFavPSoiu2pgrsiq40t4xJKYvS8+E4vXrTb+4Tm6974bWL59zbq K8p9xtd4EbKdm3tsCZsPi9UJNwQuMG+Kpd5j0BdyxRLqw== Received: by mx.olsak.net (envelope-sender ) with ESMTPS id 2cca7fc8; Fri, 01 Aug 2025 16:14:29 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Fri, 01 Aug 2025 16:14:15 +0200 Subject: [PATCH RFC v2 1/2] dt-bindings: mmc: sdhci-pxa: add state_uhs pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250801-pxav3-uhs-v2-1-afc1c428c776@dujemihanovic.xyz> References: <20250801-pxav3-uhs-v2-0-afc1c428c776@dujemihanovic.xyz> In-Reply-To: <20250801-pxav3-uhs-v2-0-afc1c428c776@dujemihanovic.xyz> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter Cc: Karel Balej , David Wronek , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2667; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=X8bDc3mEF7A+jWR5/Mtli4JbbUPbP/jIzLwqkvh83zk=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBk9p4/4vskRf7H2/pumTTsil4g9/yYTUyNWzSo7g+F8g H3H1vasjlIWBjEuBlkxRZbc/47XeD+LbN2evcwAZg4rE8gQBi5OAZiI+EZGhiXyOXE+F3QWNR8I CrrfOSHxZrzxQYv82IlcPc4PS8v49jMy3K2uuP/90A3m4otf5ESEFy+QPm6tyJ23SehoDg/LL5a 7LAA= X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 On the pxav3 controller, increasing the drive strength of the data pins might be required to maintain stability on fast bus clocks (above 100 MHz). Add a state_uhs pinctrl to allow this. The existing state_cmd_gpio pinctrl is changed to apply only on pxav1 as it's unneeded on the other controllers. Signed-off-by: Duje Mihanovi=C4=87 Reviewed-by: Rob Herring (Arm) --- Changes in v2: - Newlines between properties in if: --- .../devicetree/bindings/mmc/sdhci-pxa.yaml | 47 +++++++++++++++++-= ---- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-pxa.yaml index 4869ddef36fd89265a1bfe96bb9663b553ac5084..fba1cc50fdf07cc25d42f45512c= 385a9b8207b9b 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -30,6 +30,41 @@ allOf: maxItems: 1 reg-names: maxItems: 1 + - if: + properties: + compatible: + contains: + const: mrvl,pxav1-mmc + then: + properties: + pinctrl-names: + description: + Optional for supporting PXA168 SDIO IRQ errata to switch CMD p= in between + SDIO CMD and GPIO mode. + items: + - const: default + - const: state_cmd_gpio + + pinctrl-1: + description: + Should switch CMD pin to GPIO mode as a high output. + - if: + properties: + compatible: + contains: + const: mrvl,pxav3-mmc + then: + properties: + pinctrl-names: + description: + Optional for increasing stability of the controller at fast bu= s clocks. + items: + - const: default + - const: state_uhs + + pinctrl-1: + description: + Should switch the drive strength of the data pins to high. =20 properties: compatible: @@ -62,21 +97,13 @@ properties: - const: io - const: core =20 - pinctrl-names: - description: - Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin bet= ween - SDIO CMD and GPIO mode. - items: - - const: default - - const: state_cmd_gpio + pinctrl-names: true =20 pinctrl-0: description: Should contain default pinctrl. =20 - pinctrl-1: - description: - Should switch CMD pin to GPIO mode as a high output. + pinctrl-1: true =20 mrvl,clk-delay-cycles: description: Specify a number of cycles to delay for tuning. --=20 2.50.1 From nobody Sun Oct 5 14:35:20 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 967A026A0D5; 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Fri, 01 Aug 2025 16:14:30 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Fri, 01 Aug 2025 16:14:16 +0200 Subject: [PATCH RFC v2 2/2] mmc: sdhci-pxav3: add state_uhs pinctrl setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250801-pxav3-uhs-v2-2-afc1c428c776@dujemihanovic.xyz> References: <20250801-pxav3-uhs-v2-0-afc1c428c776@dujemihanovic.xyz> In-Reply-To: <20250801-pxav3-uhs-v2-0-afc1c428c776@dujemihanovic.xyz> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter Cc: Karel Balej , David Wronek , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3797; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=foJl8uzAJuFQqQ+PCaXvTP3D2rE0lPDeDwyI/xMymi0=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBk9p4+ISEndjp27rmRaqRKrYsK6d/b+pstPMBsKJmzmO cnw4GpuRykLgxgXg6yYIkvuf8drvJ9Ftm7PXmYAM4eVCWQIAxenAExESZyRoeXlxAUi651y7DXn yhrcOujG8N/7zrZKEYdJ02dfrt54h4/hr9wpn1qB1efOXm2wN5vM9mz5/+ae+HUzXp6dvy63JcE 8gBMA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Different bus clocks require different pinctrl states to remain stable. Add support for selecting between a default and UHS state according to the bus clock. Signed-off-by: Duje Mihanovi=C4=87 --- Changes in v2: - Don't attempt to lookup pinstates if getting pinctrl fails - Only select pinstates if both of them are valid - dev_warn() -> dev_dbg() --- drivers/mmc/host/sdhci-pxav3.c | 31 +++++++++++++++++++++++++++++= +- include/linux/platform_data/pxa_sdhci.h | 7 +++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 3fb56face3d81259b693c8569682d05c95be2880..fc6018de92fb19f028b776df0f8= 7937846621e95 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -20,9 +20,11 @@ #include #include #include +#include #include #include #include +#include =20 #include "sdhci.h" #include "sdhci-pltfm.h" @@ -313,8 +315,23 @@ static void pxav3_set_power(struct sdhci_host *host, u= nsigned char mode, mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); } =20 +static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct platform_device *pdev =3D to_platform_device(mmc_dev(host->mmc)); + struct sdhci_pxa_platdata *pdata =3D pdev->dev.platform_data; + + if (!(IS_ERR(pdata->pinctrl) || IS_ERR(pdata->pins_default) || !IS_ERR(pd= ata->pins_uhs))) { + if (clock < 100 * HZ_PER_MHZ) + pinctrl_select_state(pdata->pinctrl, pdata->pins_default); + else + pinctrl_select_state(pdata->pinctrl, pdata->pins_uhs); + } + + sdhci_set_clock(host, clock); +} + static const struct sdhci_ops pxav3_sdhci_ops =3D { - .set_clock =3D sdhci_set_clock, + .set_clock =3D pxav3_set_clock, .set_power =3D pxav3_set_power, .platform_send_init_74_clocks =3D pxav3_gen_init_74_clocks, .get_max_clock =3D sdhci_pltfm_clk_get_max_clock, @@ -441,6 +458,18 @@ static int sdhci_pxav3_probe(struct platform_device *p= dev) host->mmc->pm_caps |=3D pdata->pm_caps; } =20 + pdata->pinctrl =3D devm_pinctrl_get(dev); + if (!IS_ERR(pdata->pinctrl)) { + pdata->pins_default =3D pinctrl_lookup_state(pdata->pinctrl, "default"); + if (IS_ERR(pdata->pins_default)) + dev_dbg(dev, "could not get default state: %ld\n", + PTR_ERR(pdata->pins_default)); + pdata->pins_uhs =3D pinctrl_lookup_state(pdata->pinctrl, "state_uhs"); + if (IS_ERR(pdata->pins_uhs)) + dev_dbg(dev, "could not get uhs state: %ld\n", PTR_ERR(pdata->pins_uhs)= ); + } else + dev_dbg(dev, "could not get pinctrl handle: %ld\n", PTR_ERR(pdata->pinct= rl)); + pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); diff --git a/include/linux/platform_data/pxa_sdhci.h b/include/linux/platfo= rm_data/pxa_sdhci.h index 899457cee425d33f82606f0b8c280003bc73d48d..540aa36db11243719707bdf22db= 23a8e2035674d 100644 --- a/include/linux/platform_data/pxa_sdhci.h +++ b/include/linux/platform_data/pxa_sdhci.h @@ -35,6 +35,9 @@ * @quirks: quirks of platfrom * @quirks2: quirks2 of platfrom * @pm_caps: pm_caps of platfrom + * @pinctrl: pinctrl handle + * @pins_default: default pinctrl state + * @pins_uhs: pinctrl state for fast (>100 MHz) bus clocks */ struct sdhci_pxa_platdata { unsigned int flags; @@ -47,5 +50,9 @@ struct sdhci_pxa_platdata { unsigned int quirks; unsigned int quirks2; unsigned int pm_caps; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_uhs; }; #endif /* _PXA_SDHCI_H_ */ --=20 2.50.1