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[125.227.29.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3209a850417sm3992725a91.35.2025.08.01.01.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Aug 2025 01:23:16 -0700 (PDT) From: Leo Wang X-Google-Original-From: Leo Wang Date: Fri, 01 Aug 2025 16:22:48 +0800 Subject: [PATCH v10 1/3] dt-bindings: arm: aspeed: add Meta Clemente board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250801-add-support-for-meta-clemente-bmc-v10-1-c1c27082583d@fii-foxconn.com> References: <20250801-add-support-for-meta-clemente-bmc-v10-0-c1c27082583d@fii-foxconn.com> In-Reply-To: <20250801-add-support-for-meta-clemente-bmc-v10-0-c1c27082583d@fii-foxconn.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, linux-renesas-soc@vger.kernel.org, leo.jt.wang@fii-foxconn.com, george.kw.lee@fii-foxconn.com, bruce.jy.hung@fii-foxconn.com, Leo Wang , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754036588; l=933; i=leo.jt.wang@fii-foxconn.com; s=20250618; h=from:subject:message-id; bh=UnfBA/U+nB3GVshcJhQl74M74uA3eyzQykqLq1TeLXk=; b=b1s0dY3wOYlRo25bgL2yW3RNY+qHI7/86y7H7T8KzTP9Zb9gw8I3bewSY5hsNYMx+JHrCQ7ZZ 9KoQpnFuP5HCVeQ6ga8sPILxNRyQvLe3FifzvyCLDcB+V/LhtjPANo2 X-Developer-Key: i=leo.jt.wang@fii-foxconn.com; a=ed25519; pk=x+DKjAtU/ZbbMkkAVdwfZzKpvNUVgiV1sLJbidVIwSQ= From: Leo Wang Document the new compatibles used on Meta Clemente. Acked-by: Conor Dooley Signed-off-by: Leo Wang --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 01333ac111fbb076582a6c0e801903c3500b459f..ff3fea63cecd99ec2dc56d3cf71= 403f897681a98 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -81,6 +81,7 @@ properties: - asus,x4tf-bmc - facebook,bletchley-bmc - facebook,catalina-bmc + - facebook,clemente-bmc - facebook,cloudripper-bmc - facebook,elbert-bmc - facebook,fuji-bmc --=20 2.43.0 From nobody Sun Oct 5 16:18:51 2025 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1D93221739; Fri, 1 Aug 2025 08:23:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Piccoli" , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, linux-renesas-soc@vger.kernel.org, leo.jt.wang@fii-foxconn.com, george.kw.lee@fii-foxconn.com, bruce.jy.hung@fii-foxconn.com, Leo Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754036588; l=992; i=leo.jt.wang@fii-foxconn.com; s=20250618; h=from:subject:message-id; bh=0XkYbizVBKY9WI9Q/nF7gZY7Z8IkaJEB3NQ1RTG/C8M=; b=yT4zUHaZRPVLgHM5/hrcwMugrlznwdbZhwsee67hhcUXifJSdMZLLxnZUJ4mD0vXlcKfTLteO f/3PIDkjuklAKPVwCn+AUPDVPBhMj6vPhHZK3iE/k848ZOE/ZZexxd/ X-Developer-Key: i=leo.jt.wang@fii-foxconn.com; a=ed25519; pk=x+DKjAtU/ZbbMkkAVdwfZzKpvNUVgiV1sLJbidVIwSQ= From: Leo Wang Add pinctrl nodes for NCSI3 and NCSI4 to the AST2600 pinctrl description, enabling support for RMII3 and RMII4 interfaces. Signed-off-by: Leo Wang --- arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boo= t/dts/aspeed/aspeed-g6-pinctrl.dtsi index 289668f051eb4271ac48ae3ce9b82587911548ee..e87c4b58994add33938792f7324= 20ade7ea5c23f 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -412,6 +412,16 @@ pinctrl_mdio4_default: mdio4_default { groups =3D "MDIO4"; }; =20 + pinctrl_ncsi3_default: ncsi3_default { + function =3D "RMII3"; + groups =3D "NCSI3"; + }; + + pinctrl_ncsi4_default: ncsi4_default { + function =3D "RMII4"; + groups =3D "NCSI4"; + }; + pinctrl_ncts1_default: ncts1_default { function =3D "NCTS1"; groups =3D "NCTS1"; --=20 2.43.0 From nobody Sun Oct 5 16:18:51 2025 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44469222591; 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[125.227.29.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3209a850417sm3992725a91.35.2025.08.01.01.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Aug 2025 01:23:24 -0700 (PDT) From: Leo Wang X-Google-Original-From: Leo Wang Date: Fri, 01 Aug 2025 16:22:50 +0800 Subject: [PATCH v10 3/3] ARM: dts: aspeed: clemente: add Meta Clemente BMC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250801-add-support-for-meta-clemente-bmc-v10-3-c1c27082583d@fii-foxconn.com> References: <20250801-add-support-for-meta-clemente-bmc-v10-0-c1c27082583d@fii-foxconn.com> In-Reply-To: <20250801-add-support-for-meta-clemente-bmc-v10-0-c1c27082583d@fii-foxconn.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, linux-renesas-soc@vger.kernel.org, leo.jt.wang@fii-foxconn.com, george.kw.lee@fii-foxconn.com, bruce.jy.hung@fii-foxconn.com, Leo Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754036588; l=27993; i=leo.jt.wang@fii-foxconn.com; s=20250618; h=from:subject:message-id; bh=JcnlzwPs1XO4QdsNp8xYybj+Q3PIbaxoHnP9UYt7MBU=; b=LWkL5n4GNPuaah5wx+E3JmY/PXj/stQ963AN98CgnCeQdmn08gGgDiw9NmLMXmFrw+EfwinLX SFbTJyzoLHaC+wASnykhOg3IVnwpL7/MXsZ5ZDj8qPIrZjGmRmdZyxg X-Developer-Key: i=leo.jt.wang@fii-foxconn.com; a=ed25519; pk=x+DKjAtU/ZbbMkkAVdwfZzKpvNUVgiV1sLJbidVIwSQ= From: Leo Wang Add linux device tree entry for Meta Clemente compute-tray BMC using AST2600 SoC. Signed-off-by: Leo Wang --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-facebook-clemente.dts | 1250 ++++++++++++++++= ++++ 2 files changed, 1251 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/M= akefile index 2e5f4833a073b6c25190fd4b6e89a11f9636fc84..904503f78f960d7bc14cad7cb45= 5bb8bb3138ccd 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-delta-ahe50dc.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-catalina.dtb \ + aspeed-bmc-facebook-clemente.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-elbert.dtb \ aspeed-bmc-facebook-fuji.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/ar= ch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts new file mode 100644 index 0000000000000000000000000000000000000000..fd32d41a75b43a61b15c9c662ba= 715bbe0b3335f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -0,0 +1,1250 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Facebook Inc. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include +#include +#include +#include + +/ { + model =3D "Facebook Clemente BMC"; + compatible =3D "facebook,clemente-bmc", "aspeed,ast2600"; + + aliases { + serial0 =3D &uart1; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + i2c16 =3D &i2c1mux0ch0; + i2c17 =3D &i2c1mux0ch1; + i2c18 =3D &i2c1mux0ch2; + i2c19 =3D &i2c1mux0ch3; + i2c20 =3D &i2c1mux0ch4; + i2c21 =3D &i2c1mux0ch5; + i2c22 =3D &i2c1mux0ch6; + i2c23 =3D &i2c1mux0ch7; + i2c24 =3D &i2c0mux0ch0; + i2c25 =3D &i2c0mux0ch1; + i2c26 =3D &i2c0mux0ch2; + i2c27 =3D &i2c0mux0ch3; + i2c28 =3D &i2c0mux1ch0; + i2c29 =3D &i2c0mux1ch1; + i2c30 =3D &i2c0mux1ch2; + i2c31 =3D &i2c0mux1ch3; + i2c32 =3D &i2c0mux2ch0; + i2c33 =3D &i2c0mux2ch1; + i2c34 =3D &i2c0mux2ch2; + i2c35 =3D &i2c0mux2ch3; + i2c36 =3D &i2c0mux3ch0; + i2c37 =3D &i2c0mux3ch1; + i2c38 =3D &i2c0mux3ch2; + i2c39 =3D &i2c0mux3ch3; + i2c40 =3D &i2c0mux4ch0; + i2c41 =3D &i2c0mux4ch1; + i2c42 =3D &i2c0mux4ch2; + i2c43 =3D &i2c0mux4ch3; + i2c44 =3D &i2c0mux5ch0; + i2c45 =3D &i2c0mux5ch1; + i2c46 =3D &i2c0mux5ch2; + i2c47 =3D &i2c0mux5ch3; + i2c48 =3D &i2c0mux0ch1mux0ch0; + i2c49 =3D &i2c0mux0ch1mux0ch1; + i2c50 =3D &i2c0mux0ch1mux0ch2; + i2c51 =3D &i2c0mux0ch1mux0ch3; + i2c52 =3D &i2c0mux3ch1mux0ch0; + i2c53 =3D &i2c0mux3ch1mux0ch1; + i2c54 =3D &i2c0mux3ch1mux0ch2; + i2c55 =3D &i2c0mux3ch1mux0ch3; + }; + + chosen { + stdout-path =3D "serial4:57600n8"; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + spi1_gpio: spi { + compatible =3D "spi-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects =3D <1>; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency =3D <33000000>; + reg =3D <0>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + label =3D "bmc_heartbeat_amber"; + gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led-1 { + label =3D "fp_id_amber"; + default-state =3D "off"; + gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label =3D "bmc_ready_noled"; + gpios =3D <&gpio0 ASPEED_GPIO(B, 3) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; + }; + + led-3 { + label =3D "bmc_ready_cpld_noled"; + gpios =3D <&gpio0 ASPEED_GPIO(P, 5) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; + }; + }; + + p1v8_bmc_aux: regulator-p1v8-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-name =3D "p1v8_bmc_aux"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + p2v5_bmc_aux: regulator-p2v5-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-name =3D "p2v5_bmc_aux"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + ramoops@b3e00000 { + compatible =3D "ramoops"; + reg =3D <0xbb000000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size =3D <0x8000>; + console-size =3D <0x8000>; + ftrace-size =3D <0x8000>; + pmsg-size =3D <0x8000>; + max-reason =3D <3>; + }; + }; + +}; + +&adc0 { + vref-supply =3D <&p1v8_bmc_aux>; + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref-supply =3D <&p2v5_bmc_aux>; + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc10_default>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&fmc { + status =3D "okay"; + flash@0 { + status =3D "okay"; + m25p,fast-read; + label =3D "bmc"; + spi-max-frequency =3D <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + flash@1 { + status =3D "okay"; + m25p,fast-read; + label =3D "alt-bmc"; + spi-max-frequency =3D <50000000>; + }; +}; + +&gpio0 { + gpio-line-names =3D + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BATTERY_DETECT","PRSNT1_HPM_SCM_N", + "BMC_I2C1_FPGA_ALERT_L","BMC_READY", + "IOEXP_INT_L","FM_ID_LED", + "","", + /*C0-C7*/ "BMC_GPIOC0","","","", + "PMBUS_REQ_N","PSU_FW_UPDATE_REQ_N", + "","BMC_I2C_SSIF_ALERT_L", + /*D0-D7*/ "","","","","BMC_GPIOD4","","","", + /*E0-E7*/ "BMC_GPIOE0","BMC_GPIOE1","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","", + "FM_DEBUG_PORT_PRSNT_N","FM_BMC_DBP_PRESENT_N", + /*H0-H7*/ "PWR_BRAKE_L","RUN_POWER_EN", + "SHDN_FORCE_L","SHDN_REQ_L", + "","","","", + /*I0-I7*/ "","","","", + "","FLASH_WP_STATUS", + "FM_PDB_HEALTH_N","RUN_POWER_PG", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "PCIE_EP_RST_EN","BMC_FRU_WP", + "SCM_HPM_STBY_RST_N","SCM_HPM_STBY_EN", + "STBY_POWER_PG_3V3","TH500_SHDN_OK_L","","", + /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1", + "LED_POSTCODE_2","LED_POSTCODE_3", + "LED_POSTCODE_4","LED_POSTCODE_5", + "LED_POSTCODE_6","LED_POSTCODE_7", + /*O0-O7*/ "HMC_I2C3_FPGA_ALERT_L","FPGA_READY_HMC", + "CHASSIS_AC_LOSS_L","BSM_PRSNT_R_N", + "PSU_SMB_ALERT_L","FM_TPM_PRSNT_0_N", + "","USBDBG_IPMI_EN_L", + /*P0-P7*/ "PWR_BTN_BMC_N","IPEX_CABLE_PRSNT_L", + "ID_RST_BTN_BMC_N","RST_BMC_RSTBTN_OUT_N", + "host0-ready","BMC_READY_CPLD","BMC_GPIOP6","BMC_HEARTBEAT_N", + /*Q0-Q7*/ "IRQ_PCH_TPM_SPI_N","USB_OC0_REAR_R_N", + "UART_MUX_SEL","I2C_MUX_RESET_L", + "RSVD_NV_PLT_DETECT","SPI_TPM_INT_L", + "CPU_JTAG_MUX_SELECT","THERM_BB_OVERT_L", + /*R0-R7*/ "THERM_BB_WARN_L","SPI_BMC_FPGA_INT_L", + "CPU_BOOT_DONE","PMBUS_GNT_L", + "CHASSIS_PWR_BRK_L","PCIE_WAKE_L", + "PDB_THERM_OVERT_L","HMC_I2C2_FPGA_ALERT_L", + /*S0-S7*/ "","","SYS_BMC_PWRBTN_R_N","FM_TPM_PRSNT_1_N", + "FM_BMC_DEBUG_SW_N","UID_LED_N", + "SYS_FAULT_LED_N","RUN_POWER_FAULT_L", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "L2_RST_REQ_OUT_L","L0L1_RST_REQ_OUT_L", + "BMC_ID_BEEP_SEL","BMC_I2C0_FPGA_ALERT_L", + "SMB_BMC_TMP_ALERT","PWR_LED_N", + "SYS_RST_OUT_L","IRQ_TPM_SPI_N", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","RST_BMC_SELF_HW", + "FM_FLASH_LATCH_N","BMC_EMMC_RST_N", + "BMC_GPIOY4","BMC_GPIOY5","","", + /*Z0-Z7*/ "","","","","","","BMC_GPIOZ6","BMC_GPIOZ7"; +}; + +&gpio1 { + gpio-line-names =3D + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B3*/ "","","","", + /*18B4-18B7*/ "FM_BOARD_BMC_REV_ID0","FM_BOARD_BMC_REV_ID1","FM_BOARD_BMC= _REV_ID2","", + /*18C0-18C7*/ "","","PI_BMC_BIOS_ROM_IRQ0_N","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","","AC_PWR_BMC_BTN_N","","","",""; +}; + +&i2c0 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9546"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c0mux0ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + // HDD FRU EEPROM + eeprom@56 { + compatible =3D "atmel,24c128"; + reg =3D <0x56>; + }; + + // E1.S Backplane + i2c0mux0ch1mux0: i2c-mux@74 { + compatible =3D "nxp,pca9546"; + reg =3D <0x74>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch1mux0ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c0mux0ch1mux0ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + i2c0mux0ch1mux0ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux0ch1mux0ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + }; + i2c0mux0ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux0ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux1ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c0mux1ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + // IO Mezz 0 IOEXP + io_expander7: gpio@20 { + compatible =3D "nxp,pca9535"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "RST_CX7_0", + "RST_CX7_1", + "CX0_SSD0_PRSNT_L", + "CX1_SSD1_PRSNT_L", + "CX_BOOT_CMPLT_CX0", + "CX_BOOT_CMPLT_CX1", + "CX_TWARN_CX0_L", + "CX_TWARN_CX1_L", + "CX_OVT_SHDN_CX0", + "CX_OVT_SHDN_CX1", + "FNP_L_CX0", + "FNP_L_CX1", + "", + "MCU_GPIO", + "MCU_RST_N", + "MCU_RECOVERY_N"; + }; + + // IO Mezz 0 FRU EEPROM + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; + + // OSFP 0 FRU EEPROM + eeprom@52 { + compatible =3D "atmel,24c128"; + reg =3D <0x52>; + }; + }; + i2c0mux1ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux1ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + + i2c-mux@73 { + compatible =3D "nxp,pca9546"; + reg =3D <0x73>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux2ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + // IOB0 NIC0 TEMP + temperature-sensor@1f { + compatible =3D "ti,tmp421"; + reg =3D <0x1f>; + }; + }; + i2c0mux2ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + i2c0mux2ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux2ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + // IOB0 NIC1 TEMP + temperature-sensor@1f { + compatible =3D "ti,tmp421"; + reg =3D <0x1f>; + }; + }; + }; + + i2c-mux@75 { + compatible =3D "nxp,pca9546"; + reg =3D <0x75>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux3ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c0mux3ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + // E1.S Backplane HDD FRU EEPROM + eeprom@56 { + compatible =3D "atmel,24c128"; + reg =3D <0x56>; + }; + + // E1.S Backplane MUX + i2c0mux3ch1mux0: i2c-mux@74 { + compatible =3D "nxp,pca9546"; + reg =3D <0x74>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux3ch1mux0ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c0mux3ch1mux0ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + i2c0mux3ch1mux0ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux3ch1mux0ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + }; + i2c0mux3ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux3ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + + i2c-mux@76 { + compatible =3D "nxp,pca9546"; + reg =3D <0x76>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux4ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c0mux4ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + // IO Mezz 1 IOEXP + io_expander8: gpio@21 { + compatible =3D "nxp,pca9535"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "SEC_RST_CX7_0", + "SEC_RST_CX7_1", + "SEC_CX0_SSD0_PRSNT_L", + "SEC_CX1_SSD1_PRSNT_L", + "SEC_CX_BOOT_CMPLT_CX0", + "SEC_CX_BOOT_CMPLT_CX1", + "SEC_CX_TWARN_CX0_L", + "SEC_CX_TWARN_CX1_L", + "SEC_CX_OVT_SHDN_CX0", + "SEC_CX_OVT_SHDN_CX1", + "SEC_FNP_L_CX0", + "SEC_FNP_L_CX1", + "", + "SEC_MCU_GPIO", + "SEC_MCU_RST_N", + "SEC_MCU_RECOVERY_N"; + }; + + // IO Mezz 1 FRU EEPROM + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; + + // OSFP 1 FRU EEPROM + eeprom@52 { + compatible =3D "atmel,24c128"; + reg =3D <0x52>; + }; + }; + i2c0mux4ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux4ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9546"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux5ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + // IOB1 NIC0 TEMP + temperature-sensor@1f { + compatible =3D "ti,tmp421"; + reg =3D <0x1f>; + }; + }; + i2c0mux5ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + i2c0mux5ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + i2c0mux5ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + // IOB1 NIC1 TEMP + temperature-sensor@1f { + compatible =3D "ti,tmp421"; + reg =3D <0x1f>; + }; + }; + }; +}; + +&i2c1 { + status =3D "okay"; + + // PDB + power-monitor@12 { + compatible =3D "ti,lm5066i"; + reg =3D <0x12>; + }; + + // PDB + power-monitor@14 { + compatible =3D "ti,lm5066i"; + reg =3D <0x14>; + }; + + // Module 0 + fanctl0: fan-controller@20{ + compatible =3D "maxim,max31790"; + reg =3D <0x20>; + }; + + // Module 0 + fanctl1: fan-controller@23{ + compatible =3D "maxim,max31790"; + reg =3D <0x23>; + }; + + // Module 1 + fanctl2: fan-controller@2c{ + compatible =3D "maxim,max31790"; + reg =3D <0x2c>; + }; + + // Module 1 + fanctl3: fan-controller@2f{ + compatible =3D "maxim,max31790"; + reg =3D <0x2f>; + }; + + // Module 0 Leak Sensor + adc@34 { + compatible =3D "maxim,max1363"; + reg =3D <0x34>; + }; + + // Module 1 Leak Sensor + adc@35 { + compatible =3D "maxim,max1363"; + reg =3D <0x35>; + }; + + // PDB TEMP SENSOR + temperature-sensor@4e { + compatible =3D "ti,tmp1075"; + reg =3D <0x4e>; + }; + + // PDB FRU EEPROM + eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + }; + + // PDB + vrm@60 { + compatible =3D "renesas,raa228004"; + reg =3D <0x60>; + }; + + // PDB + vrm@61 { + compatible =3D "renesas,raa228004"; + reg =3D <0x61>; + }; + + // Interposer + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + i2c-mux-idle-disconnect; + + i2c1mux0ch0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0>; + }; + i2c1mux0ch1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x1>; + }; + i2c1mux0ch2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x2>; + }; + i2c1mux0ch3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x3>; + }; + i2c1mux0ch4: i2c@4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x4>; + }; + i2c1mux0ch5: i2c@5 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x5>; + + // Interposer TEMP SENSOR + temperature-sensor@4f { + compatible =3D "ti,tmp75"; + reg =3D <0x4f>; + }; + + // Interposer FRU EEPROM + eeprom@54 { + compatible =3D "atmel,24c64"; + reg =3D <0x54>; + }; + }; + i2c1mux0ch6: i2c@6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x6>; + + // Interposer IOEXP + io_expander5: gpio@27 { + compatible =3D "nxp,pca9554"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "JTAG_MUX_SEL", + "IOX_BMC_RESET", + "RTC_CLR_L", + "RTC_U77_ALRT_N", + "", + "PSU_ALERT_N", + "", + "RST_P12V_STBY_N"; + }; + }; + i2c1mux0ch7: i2c@7 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x7>; + + // FIO TEMP SENSOR + temperature-sensor@4b { + compatible =3D "ti,tmp75"; + reg =3D <0x4b>; + }; + + // FIO FRU EEPROM + eeprom@51 { + compatible =3D "atmel,24c64"; + reg =3D <0x51>; + }; + }; + }; +}; + +&i2c2 { + status =3D "okay"; + // Module 0, Expander @0x20 + io_expander0: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "FPGA_THERM_OVERT_L-I", + "FPGA_READY_BMC-I", + "HMC_BMC_DETECT-O", + "HMC_PGOOD-O", + "", + "BMC_STBY_CYCLE-O", + "FPGA_EROT_FATAL_ERROR_L-I", + "WP_HW_EXT_CTRL_L-O", + "EROT_FPGA_RST_L-O", + "FPGA_EROT_RECOVERY_L-O", + "BMC_EROT_FPGA_SPI_MUX_SEL-O", + "USB2_HUB_RST_L-O", + "", + "SGPIO_EN_L-O", + "B2B_IOEXP_INT_L-I", + "I2C_BUS_MUX_RESET_L-O"; + }; + + // Module 1, Expander @0x21 + io_expander1: gpio@21 { + compatible =3D "nxp,pca9555"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "SEC_FPGA_THERM_OVERT_L", + "SEC_FPGA_READY_BMC", + "SEC_HMC_BMC_DETECT", + "SEC_HMC_PGOOD", + "", + "SEC_BMC_SELF_POWER_CYCLE", + "SEC_SEC_FPGA_EROT_FATAL_ERROR_L", + "SEC_WP_HW_EXT_CTRL_L", + "SEC_EROT_FPGA_RST_L", + "SEC_FPGA_EROT_RECOVERY_L", + "SEC_BMC_EROT_FPGA_SPI_MUX_SEL", + "SEC_USB2_HUB_RST_L", + "", + "SEC_SGPIO_EN_L", + "SEC_IOB_IOEXP_INT_L", + "SEC_I2C_BUS_MUX_RESET_L"; + }; + + // HMC Expander @0x27 + io_expander2: gpio@27 { + compatible =3D "nxp,pca9555"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "HMC_PRSNT_L-I", + "HMC_READY-I", + "HMC_EROT_FATAL_ERROR_L-I", + "I2C_MUX_SEL-O", + "HMC_EROT_SPI_MUX_SEL-O", + "HMC_EROT_RECOVERY_L-O", + "HMC_EROT_RST_L-O", + "GLOBAL_WP_HMC-O", + "FPGA_RST_L-O", + "USB2_HUB_RST-O", + "CPU_UART_MUX_SEL-O", + "", + "", + "", + "", + ""; + }; + + // Module 0 Aux EEPROM + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; + + // Module 1 Aux EEPROM + eeprom@51 { + compatible =3D "atmel,24c64"; + reg =3D <0x51>; + }; +}; + +&i2c3 { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; +}; + +&i2c6 { + status =3D "okay"; + io_expander3: gpio@21 { + compatible =3D "nxp,pca9555"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "RTC_MUX_SEL", + "PCI_MUX_SEL", + "TPM_MUX_SEL", + "FAN_MUX-SEL", + "SGMII_MUX_SEL", + "DP_MUX_SEL", + "UPHY3_USB_SEL", + "NCSI_MUX_SEL", + "BMC_PHY_RST", + "RTC_CLR_L", + "BMC_12V_CTRL", + "PS_RUN_IO0_PG", + "", + "", + "", + ""; + }; + + rtc@6f { + compatible =3D "nuvoton,nct3018y"; + reg =3D <0x6f>; + }; +}; + +&i2c7 { + status =3D "okay"; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2c9 { + status =3D "okay"; + // SCM TEMP SENSOR BOARD + temperature-sensor@4b { + compatible =3D "national,lm75b"; + reg =3D <0x4b>; + }; + + // SCM CPLD IOEXP + io_expander4: gpio@4f { + compatible =3D "nxp,pca9555"; + reg =3D <0x4f>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "stby_power_en_cpld", + "stby_power_gd_cpld", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + }; + + // SCM FRU EEPROM + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; + + // BSM FRU EEPROM + eeprom@56 { + compatible =3D "atmel,24c64"; + reg =3D <0x56>; + }; +}; + +&i2c10 { + status =3D "okay"; + multi-master; + mctp-controller; + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + // OCP NIC0 TEMP + temperature-sensor@1f { + compatible =3D "ti,tmp421"; + reg =3D <0x1f>; + }; + + // OCP NIC0 FRU EEPROM + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; +}; + +&i2c11 { + status =3D "okay"; + + ssif-bmc@10 { + compatible =3D "ssif-bmc"; + reg =3D <0x10>; + }; +}; + +&i2c12 { + status =3D "okay"; + multi-master; + + // HPM 1 FRU EEPROM + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; + // CBC 2 FRU + eeprom@54 { + compatible =3D "atmel,24c02"; + reg =3D <0x54>; + }; + // CBC 3 FRU + eeprom@55 { + compatible =3D "atmel,24c02"; + reg =3D <0x55>; + }; +}; + +&i2c13 { + status =3D "okay"; + multi-master; + + // HPM FRU EEPROM + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; + // CBC 0 FRU + eeprom@54 { + compatible =3D "atmel,24c02"; + reg =3D <0x54>; + }; + // CBC 1 FRU + eeprom@55 { + compatible =3D "atmel,24c02"; + reg =3D <0x55>; + }; + // HMC FRU EEPROM + eeprom@57 { + compatible =3D "atmel,24c02"; + reg =3D <0x57>; + }; +}; + +&i2c14 { + status =3D "okay"; + + // PDB CPLD IOEXP 0x10 + io_expander9: gpio@10 { + compatible =3D "nxp,pca9555"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + reg =3D <0x10>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "wSequence_Latch_State_N", + "wP12V_N1N2_RUNTIME_FLT_N", + "wP12V_FAN_RUNTIME_FLT_N", + "wP12V_AUX_RUNTIME_FLT_N", + "wHost_PERST_SEQPWR_FLT_N", + "wP12V_N1N2_SEQPWR_FLT_N", + "wP12V_FAN_SEQPWR_FLT_N", + "wP12V_AUX_SEQPWR_FLT_N", + "wP12V_RUNTIME_FLT_NIC1_N", + "wAUX_RUNTIME_FLT_NIC1_N", + "wP12V_SEQPWR_FLT_NIC1_N", + "wAUX_SEQPWR_FLT_NIC1_N", + "wP12V_RUNTIME_FLT_NIC0_N", + "wAUX_RUNTIME_FLT_NIC0_N", + "wP12V_SEQPWR_FLT_NIC0_N", + "wAUX_SEQPWR_FLT_NIC0_N"; + }; + + // PDB CPLD IOEXP 0x11 + io_expander10: gpio@11 { + compatible =3D "nxp,pca9555"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + reg =3D <0x11>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "FM_P12V_NIC1_FLTB_R_N", + "FM_P3V3_NIC1_FAULT_R_N", + "FM_P12V_NIC0_FLTB_R_N", + "FM_P3V3_NIC0_FAULT_R_N", + "P48V_HS2_FAULT_N_PLD", + "P48V_HS1_FAULT_N_PLD", + "P12V_AUX_FAN_OC_PLD_N", + "P12V_AUX_FAN_FAULT_PLD_N", + "", + "", + "", + "", + "", + "FM_SYS_THROTTLE_N", + "OCP_V3_2_PWRBRK_FROM_HOST_ISO_PLD_N", + "OCP_SFF_PWRBRK_FROM_HOST_ISO_PLD_N"; + }; + + // PDB CPLD IOEXP 0x12 + io_expander11: gpio@12 { + compatible =3D "nxp,pca9555"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + reg =3D <0x12>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "P12V_AUX_PSU_SMB_ALERT_R_L", + "P12V_SCM_SENSE_ALERT_R_N", + "P12V_AUX_NIC1_SENSE_ALERT_R_N", + "P12V_AUX_NIC0_SENSE_ALERT_R_N", + "NODEB_PSU_SMB_ALERT_R_L", + "NODEA_PSU_SMB_ALERT_R_L", + "P12V_AUX_FAN_ALERT_PLD_N", + "P52V_SENSE_ALERT_PLD_N", + "PRSNT_RJ45_FIO_N_R", + "FM_MAIN_PWREN_RMC_EN_ISO_R", + "CHASSIS3_LEAK_Q_N_PLD", + "CHASSIS2_LEAK_Q_N_PLD", + "CHASSIS1_LEAK_Q_N_PLD", + "CHASSIS0_LEAK_Q_N_PLD", + "", + "SMB_RJ45_FIO_TMP_ALERT"; + }; + + // PDB CPLD IOEXP 0x13 + io_expander12: gpio@13 { + compatible =3D "nxp,pca9555"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + reg =3D <0x13>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "FAN_7_PRESENT_N", + "FAN_6_PRESENT_N", + "FAN_5_PRESENT_N", + "FAN_4_PRESENT_N", + "FAN_3_PRESENT_N", + "FAN_2_PRESENT_N", + "FAN_1_PRESENT_N", + "FAN_0_PRESENT_N", + "HP_LVC3_OCP_V3_2_PRSNT2_PLD_N", + "HP_LVC3_OCP_V3_1_PRSNT2_PLD_N", + "PRSNT_HDDBD_POWER_CABLE_N", + "PRSNT_OSFP0_POWER_CABLE_N", + "PRSNT_CHASSIS3_LEAK_CABLE_R_N", + "PRSNT_CHASSIS2_LEAK_CABLE_R_N", + "PRSNT_CHASSIS1_LEAK_CABLE_R_N", + "PRSNT_CHASSIS0_LEAK_CABLE_R_N"; + }; + + // PDB CPLD IOEXP 0x14 + io_expander13: gpio@14 { + compatible =3D "nxp,pca9555"; + reg =3D <0x14>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "rmc_en_dc_pwr_on", + "", + "", + "", + "", + "", + "", + "", + "leak_config_0", + "leak_config_1", + "leak_config_2", + "leak_config_3", + "mfg_led_test_mode_l", + "small_leak_err_inj", + "large_leak_err_inj", + ""; + }; +}; + +&i2c15 { + status =3D "okay"; + multi-master; + mctp-controller; + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + // OCP NIC1 TEMP + temperature-sensor@1f { + compatible =3D "ti,tmp421"; + reg =3D <0x1f>; + }; + + // OCP NIC1 FRU EEPROM + eeprom@52 { + compatible =3D "atmel,24c64"; + reg =3D <0x52>; + }; +}; + +&mac2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ncsi3_default>; + use-ncsi; +}; + +&mac3 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ncsi4_default>; + use-ncsi; +}; + +&udma { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +&uart5 { + status =3D "okay"; +}; + +&wdt1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdtrst1_default>; + aspeed,reset-type =3D "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration =3D <256>; +}; + --=20 2.43.0