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Thu, 31 Jul 2025 17:38:58 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B26792004B; Thu, 31 Jul 2025 17:38:58 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 78EA920043; Thu, 31 Jul 2025 17:38:58 +0000 (GMT) Received: from tuxmaker.lnxne.boe (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 31 Jul 2025 17:38:58 +0000 (GMT) From: Gerd Bayer To: 18255117159@163.com, bhelgaas@google.com, helgaas@kernel.org Cc: gbayer@linux.ibm.com, agordeev@linux.ibm.com, borntraeger@linux.ibm.com, ilpo.jarvinen@linux.intel.com, jingoohan1@gmail.com, kwilczynski@kernel.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, linux-next@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, mani@kernel.org, robh@kernel.org, schnelle@linux.ibm.com Subject: [PATCH] PCI: Fix endianness issues in pci_bus_read_config() Date: Thu, 31 Jul 2025 19:38:58 +0200 Message-ID: <20250731173858.1173442-1-gbayer@linux.ibm.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <4e10bea3aa91ee721bb40e9388e8f72f930908fe.camel@linux.ibm.com> References: <4e10bea3aa91ee721bb40e9388e8f72f930908fe.camel@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: dTQDf-ePIRf2HCvROzeIzIwabYlVCwig X-Proofpoint-GUID: yAHBx8M0qM3OjVV29OTqZi3GqnvjhKax X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMxMDEyMCBTYWx0ZWRfX4s98G7dwl3i1 TteX2/43+G6a1sfSdSOQZmN6fOHbGRaiyrpx6jhmdiu0Q7wWQK++v/dLS7VeSUBgSoP+CHF0OcJ 53DFtZHyutJdx1dxRL2w7xtxl+4/V5Snwvcb+HYnsY93MsNI4pQVOhaW8eVG0Md2Q7uxZVs0t6Q aR0VvjYAVRC1kEFShEnWqfEpb9ymPYOyO8lrdlsc+KD8NtEkhknxcsXyJjWCn7eXRZ9H39GQe3x 58qpAl6BPVmuxg0cdfTo7PoNO+g+xjRjVNptK6TxWtX2NiL82IMqja6khPZhOs9CdhO/rBDtcFc DzsG76wQ0QCKZBWpE8Ft1xzEDlBTuTn9w0j3kLvAEU0xUQ94fr6MmZSbRcpkwwZs+mw5WaZXaU2 sk+mRsa62pHmJLkUNGiNwxDfAjUQY00N9TA+Ia9S0egdcoQJoG1AEk1x6gv3eSCMShxklKcL X-Authority-Analysis: v=2.4 cv=BJOzrEQG c=1 sm=1 tr=0 ts=688baa38 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=Byx-y9mGAAAA:8 a=VnNF1IyMAAAA:8 a=Pc6pn_66ZPNL0meD3e8A:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-31_03,2025-07-31_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 adultscore=0 clxscore=1011 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507310120 Content-Type: text/plain; charset="utf-8" Simple pointer-casts to map byte and word reads from PCI config space into dwords (i.e. u32) produce unintended results on big-endian systems. Add the necessary adjustments under compile-time switch CONFIG_CPU_BIG_ENDIAN. pci_bus_read_config() was just introduced with https://lore.kernel.org/all/20250716161203.83823-2-18255117159@163.com/ Signed-off-by: Gerd Bayer --- Hi Hans, hi Bjorn, Sorry to spill this endianness aware code into drivers/pci, feel free to suggest a cleaner approach. This has fixed the issues seen on s390 systems Otherwise it is just compile-tested for x86 and arm64. Since this is still sitting in the a pull-request for upstream, I'm not sur= e if this warrants a Fixes: tag. Thanks, Gerd --- drivers/pci/access.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index ba66f55d2524..77a73b772a28 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -89,15 +89,24 @@ int pci_bus_read_config(void *priv, unsigned int devfn,= int where, u32 size, u32 *val) { struct pci_bus *bus =3D priv; + int rc; =20 - if (size =3D=3D 1) - return pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); - else if (size =3D=3D 2) - return pci_bus_read_config_word(bus, devfn, where, (u16 *)val); - else if (size =3D=3D 4) - return pci_bus_read_config_dword(bus, devfn, where, val); - else - return PCIBIOS_BAD_REGISTER_NUMBER; + if (size =3D=3D 1) { + rc =3D pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); +#if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + *val =3D ((*val >> 24) & 0xff); +#endif + } else if (size =3D=3D 2) { + rc =3D pci_bus_read_config_word(bus, devfn, where, (u16 *)val); +#if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + *val =3D ((*val >> 16) & 0xffff); +#endif + } else if (size =3D=3D 4) { + rc =3D pci_bus_read_config_dword(bus, devfn, where, val); + } else { + rc =3D PCIBIOS_BAD_REGISTER_NUMBER; + } + return rc; } =20 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, --=20 2.48.1