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Thu, 31 Jul 2025 16:10:36 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 24E552004F; Thu, 31 Jul 2025 16:10:36 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D31382004B; Thu, 31 Jul 2025 16:10:32 +0000 (GMT) Received: from li-06431bcc-2712-11b2-a85c-a6fe68df28f9.ibm.com.com (unknown [9.39.19.108]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 31 Jul 2025 16:10:32 +0000 (GMT) From: Donet Tom To: Madhavan Srinivasan , Christophe Leroy , linuxppc-dev@lists.ozlabs.org Cc: Ritesh Harjani , linux-kernel@vger.kernel.org, Michael Ellerman , Nicholas Piggin , Vishal Chourasia , Donet Tom Subject: [PATCH] powerpc/mm: Switch MMU context on hash MMU if SLB preload cache is aged Date: Thu, 31 Jul 2025 21:40:27 +0530 Message-ID: <20250731161027.966196-1-donettom@linux.ibm.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: AQlI__8eaXMhKdwYoEHMRrMuB_H_qp-d X-Authority-Analysis: v=2.4 cv=Mbtsu4/f c=1 sm=1 tr=0 ts=688b9581 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=pGLkceISAAAA:8 a=VnNF1IyMAAAA:8 a=FINkVeRlo5BJDc_9tkUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: qTxxwih5DL7kS9UKzzfvZAzwrcxzWN2m X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMxMDEwOCBTYWx0ZWRfX26fCvGxZwzzh I7EzrPxxTYACk3kMHw2R3w7KCHVr01z2AIVO6WTYxkma9XK81vjHqZ3wlblz16eB4Fc9VV3405a wiIwDBpbVM/HmSuVCUfvvxltO1v0Ae74XSGAfu0fVx3e+WPKWPQnpz2clo7SzlwIR0nTzvViZm0 1Uq3262jFvAsaUIsBf7fxEehAq7uFlLQTawktjK8NIRj0s8X1ShGRUSH2dfGK6fX+vASSJNGT93 c5WCubiOKmfbFJfRTtWQKpUPekR+G6v671ngzZo2MvJsx6Mj64EThMRIcksP7Df/T+ttu6ADx3O QH4oheAFiVAnqRnAzRLqAowKiwlFRP2ExVjThaGyFKb8VTAOqQbESWpBhDeVbTsfEPOvZehvPza 80G2g7+WLC7dhkxn3dG/uiwU1+aUfsROheG2W2NdQ8Upj7+UEeA6I1yKt4Xg0vUuCJX8ykQs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-31_03,2025-07-31_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 adultscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 spamscore=0 mlxscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507310108 On systems using the hash MMU, there is a software SLB preload cache that mirrors the entries loaded into the hardware SLB buffer. This preload cache is subject to periodic eviction =E2=80=94 typically after every 256 c= ontext switches =E2=80=94 to remove old entry. Currently, the kernel skips the MMU context switch in switch_mm_irqs_off() if the prev and next mm_struct are the same, as an optimization. However, this behavior can lead to problems on hash MMU systems. Consider the following scenario: a process is running on CPU A and gets context-switched to CPU B. During this time, one of its SLB preload cache entries is evicted. Later, the process is rescheduled on CPU A, which was running swapper in the meantime, using the same mm_struct. Because prev =3D=3D next, the kernel skips the MMU context switch. As a result, the hardware SLB buffer still contains the entry, but the software preload cache does not. The absence of the entry in the preload cache causes it to attempt to reload the SLB. However, since the entry is already present in the hardware SLB, this leads to a SLB multi-hit error. To fix this issue, we add a code change to always switch the MMU context on hash MMU if the SLB preload cache has aged. With this change, the SLB multi-hit error no longer occurs. Fixes: 5434ae74629a ("powerpc/64s/hash: Add a SLB preload cache") Suggested-by: Ritesh Harjani (IBM) Signed-off-by: Donet Tom --- arch/powerpc/mm/book3s64/slb.c | 2 +- arch/powerpc/mm/mmu_context.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/mm/book3s64/slb.c b/arch/powerpc/mm/book3s64/slb.c index 6b783552403c..08daac3f978c 100644 --- a/arch/powerpc/mm/book3s64/slb.c +++ b/arch/powerpc/mm/book3s64/slb.c @@ -509,7 +509,7 @@ void switch_slb(struct task_struct *tsk, struct mm_stru= ct *mm) * SLB preload cache. */ tsk->thread.load_slb++; - if (!tsk->thread.load_slb) { + if (tsk->thread.load_slb =3D=3D U8_MAX) { unsigned long pc =3D KSTK_EIP(tsk); =20 preload_age(ti); diff --git a/arch/powerpc/mm/mmu_context.c b/arch/powerpc/mm/mmu_context.c index 3e3af29b4523..d7b9ac8c9971 100644 --- a/arch/powerpc/mm/mmu_context.c +++ b/arch/powerpc/mm/mmu_context.c @@ -84,7 +84,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm= _struct *next, switch_mm_pgdir(tsk, next); =20 /* Nothing else to do if we aren't actually switching */ - if (prev =3D=3D next) + if ((prev =3D=3D next) && (tsk->thread.load_slb !=3D U8_MAX)) return; =20 /* --=20 2.50.1