From nobody Sun Oct 5 16:18:50 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0767376; Thu, 31 Jul 2025 14:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973880; cv=none; b=X0YVP1CKsHMbTY9y0Juj7lbw6Azzytzb5FIeOwW6ppo4EfLQKwBO3uDng0PAjQtqqZSRFTnP/SuK3FNd4SoahBXQfx3Q/EDe0J0wBUlm5bmu/y7F75krobBSBcPQ7a9X29RGC1ojKWlvmgy6GFW2gG3eCJsaRNarfbp6vrY0B+4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973880; c=relaxed/simple; bh=jtzIxCjuAe722c28oO43NixgMqMHzIjgHvU43Zh3y5Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iFhseYCXfr/nWQIEub9GwgBUToCjxpEU1a4teOYAlqOTpqC39ENY4nSnOnScfpGwd0ZyqLUgeZ3NrWYYDZpkSu1QXNZaQvnOltFhLEkJwPVPnwPL21hcEIXvNF7aUNsg37dMHffR5mhHak6KMpooKHDbHIbZTKgXqVtwdUwuclo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Fx1fAw2N; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Fx1fAw2N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753973879; x=1785509879; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jtzIxCjuAe722c28oO43NixgMqMHzIjgHvU43Zh3y5Q=; b=Fx1fAw2NAyDH9H5gKBpDGv1rg355K+C37rUbXlu0wKuaoTd95iOmvaCC hYbYwKtMw6I+gqXjXxjTC2/s6pD+DGQoVt7k6pwRA1G2Q+z4m73qh6FUK iqF/Er/ZUvvMkI8j2wczkX7nvyVFeHmU+S30d4GHHG8hx/O/da9aVJN/f 6O+ycKyiFN77ZmzzMAzHB5WVoeK5wCW4PY88SpfGfJ+fWgQf3CFcHGCnr 1bnnRExS7logOeMzSOXs5B1XFu4doNPhzydz63QJW2ZNOos1JkTdF9kLS SFAZXO65qZMUnLiE6qpJvsGQ0939j2LCrmK2UaVXzDoqsJkjXe6/WNvni g==; X-CSE-ConnectionGUID: +bZd9o6bQp6qyCNAWQVNkQ== X-CSE-MsgGUID: FYO94KGsSAWgHjbpVFIgQQ== X-IronPort-AV: E=McAfee;i="6800,10657,11508"; a="56231734" X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="56231734" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:57:57 -0700 X-CSE-ConnectionGUID: X4XEjVthQZ2NFEHm7PUrBQ== X-CSE-MsgGUID: PJEvk+hVQVW3XTngy8olaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="163633341" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:57:55 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , James Morse , Mauro Carvalho Chehab , Robert Richter , Lai Yi , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] EDAC/{skx_common,skx}: Use configuration data, not global macros Date: Thu, 31 Jul 2025 22:55:28 +0800 Message-ID: <20250731145534.2759334-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> References: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use model-specific configuration data for the number of memory controllers per socket, channels per memory controller, and DIMMs per channel as intended, instead of relying on global macros for maximum values. No functional changes intended. Signed-off-by: Qiuxu Zhuo --- drivers/edac/skx_base.c | 33 ++++++++++++++++++++------------- drivers/edac/skx_common.c | 16 +++++++++------- drivers/edac/skx_common.h | 1 + 3 files changed, 30 insertions(+), 20 deletions(-) diff --git a/drivers/edac/skx_base.c b/drivers/edac/skx_base.c index 29897b21fb8e..078ddf95cc6e 100644 --- a/drivers/edac/skx_base.c +++ b/drivers/edac/skx_base.c @@ -33,6 +33,15 @@ static unsigned int nvdimm_count; #define MASK26 0x3FFFFFF /* Mask for 2^26 */ #define MASK29 0x1FFFFFFF /* Mask for 2^29 */ =20 +static struct res_config skx_cfg =3D { + .type =3D SKX, + .decs_did =3D 0x2016, + .busno_cfg_offset =3D 0xcc, + .ddr_imc_num =3D 2, + .ddr_chan_num =3D 3, + .ddr_dimm_num =3D 2, +}; + static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx) { struct skx_dev *d; @@ -52,7 +61,7 @@ enum munittype { =20 struct munit { u16 did; - u16 devfn[SKX_NUM_IMC]; + u16 devfn[2]; u8 busidx; u8 per_socket; enum munittype mtype; @@ -89,11 +98,11 @@ static int get_all_munits(const struct munit *m) if (!pdev) break; ndev++; - if (m->per_socket =3D=3D SKX_NUM_IMC) { - for (i =3D 0; i < SKX_NUM_IMC; i++) + if (m->per_socket =3D=3D skx_cfg.ddr_imc_num) { + for (i =3D 0; i < skx_cfg.ddr_imc_num; i++) if (m->devfn[i] =3D=3D pdev->devfn) break; - if (i =3D=3D SKX_NUM_IMC) + if (i =3D=3D skx_cfg.ddr_imc_num) goto fail; } d =3D get_skx_dev(pdev->bus, m->busidx); @@ -157,12 +166,6 @@ static int get_all_munits(const struct munit *m) return -ENODEV; } =20 -static struct res_config skx_cfg =3D { - .type =3D SKX, - .decs_did =3D 0x2016, - .busno_cfg_offset =3D 0xcc, -}; - static const struct x86_cpu_id skx_cpuids[] =3D { X86_MATCH_VFM(INTEL_SKYLAKE_X, &skx_cfg), { } @@ -186,11 +189,11 @@ static int skx_get_dimm_config(struct mem_ctl_info *m= ci, struct res_config *cfg) /* Only the mcmtr on the first channel is effective */ pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr); =20 - for (i =3D 0; i < SKX_NUM_CHANNELS; i++) { + for (i =3D 0; i < cfg->ddr_chan_num; i++) { ndimms =3D 0; pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap); pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg); - for (j =3D 0; j < SKX_NUM_DIMMS; j++) { + for (j =3D 0; j < cfg->ddr_dimm_num; j++) { dimm =3D edac_get_dimm(mci, i, j, 0); pci_read_config_dword(imc->chan[i].cdev, 0x80 + 4 * j, &mtr); @@ -620,6 +623,7 @@ static int __init skx_init(void) return -ENODEV; =20 cfg =3D (struct res_config *)id->driver_data; + skx_set_res_cfg(cfg); =20 rc =3D skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm); if (rc) @@ -652,10 +656,13 @@ static int __init skx_init(void) goto fail; =20 edac_dbg(2, "src_id =3D %d\n", src_id); - for (i =3D 0; i < SKX_NUM_IMC; i++) { + for (i =3D 0; i < cfg->ddr_imc_num; i++) { d->imc[i].mc =3D mc++; d->imc[i].lmc =3D i; d->imc[i].src_id =3D src_id; + d->imc[i].num_channels =3D cfg->ddr_chan_num; + d->imc[i].num_dimms =3D cfg->ddr_dimm_num; + rc =3D skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev, "Skylake Socket", EDAC_MOD_STR, skx_get_dimm_config, cfg); diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index c9ade45c1a99..d0f53a3a8a0b 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -320,10 +320,10 @@ static int get_width(u32 mtr) */ int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **li= st) { + int ndev =3D 0, imc_num =3D cfg->ddr_imc_num + cfg->hbm_imc_num; struct pci_dev *pdev, *prev; struct skx_dev *d; u32 reg; - int ndev =3D 0; =20 prev =3D NULL; for (;;) { @@ -354,8 +354,10 @@ int skx_get_all_bus_mappings(struct res_config *cfg, s= truct list_head **list) d->seg =3D GET_BITFIELD(reg, 16, 23); } =20 - edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n", - d->bus[0], d->bus[1], d->bus[2], d->bus[3]); + d->num_imc =3D imc_num; + + edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x, imcs %d\n", + d->bus[0], d->bus[1], d->bus[2], d->bus[3], imc_num); list_add_tail(&d->list, &dev_edac_list); prev =3D pdev; =20 @@ -541,10 +543,10 @@ int skx_register_mci(struct skx_imc *imc, struct pci_= dev *pdev, =20 /* Allocate a new MC control structure */ layers[0].type =3D EDAC_MC_LAYER_CHANNEL; - layers[0].size =3D NUM_CHANNELS; + layers[0].size =3D imc->num_channels; layers[0].is_virt_csrow =3D false; layers[1].type =3D EDAC_MC_LAYER_SLOT; - layers[1].size =3D NUM_DIMMS; + layers[1].size =3D imc->num_dimms; layers[1].is_virt_csrow =3D true; mci =3D edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers, sizeof(struct skx_pvt)); @@ -784,7 +786,7 @@ void skx_remove(void) =20 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) { list_del(&d->list); - for (i =3D 0; i < NUM_IMC; i++) { + for (i =3D 0; i < d->num_imc; i++) { if (d->imc[i].mci) skx_unregister_mci(&d->imc[i]); =20 @@ -794,7 +796,7 @@ void skx_remove(void) if (d->imc[i].mbase) iounmap(d->imc[i].mbase); =20 - for (j =3D 0; j < NUM_CHANNELS; j++) { + for (j =3D 0; j < d->imc[i].num_channels; j++) { if (d->imc[i].chan[j].cdev) pci_dev_put(d->imc[i].chan[j].cdev); } diff --git a/drivers/edac/skx_common.h b/drivers/edac/skx_common.h index ec4966f7ea40..3f6007a97267 100644 --- a/drivers/edac/skx_common.h +++ b/drivers/edac/skx_common.h @@ -134,6 +134,7 @@ struct skx_dev { struct pci_dev *uracu; /* for i10nm CPU */ struct pci_dev *pcu_cr3; /* for HBM memory detection */ u32 mcroute; + int num_imc; /* * Some server BIOS may hide certain memory controllers, and the * EDAC driver skips those hidden memory controllers. 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Move mc_mapping to be a field inside struct skx_imc to prepare for making the imc array of memory controller instances a flexible array. No functional changes intended. Suggested-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- drivers/edac/skx_common.c | 8 ++++---- drivers/edac/skx_common.h | 20 ++++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index d0f53a3a8a0b..94a66b28751a 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -131,7 +131,7 @@ static void skx_init_mc_mapping(struct skx_dev *d) * EDAC driver. */ for (int i =3D 0; i < NUM_IMC; i++) - d->mc_mapping[i] =3D i; + d->imc[i].mc_mapping =3D i; } =20 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc) @@ -139,16 +139,16 @@ void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8= lmc) edac_dbg(0, "Set the mapping of mc phy idx to logical idx: %02d -> %02d\n= ", pmc, lmc); =20 - d->mc_mapping[pmc] =3D lmc; + d->imc[pmc].mc_mapping =3D lmc; } EXPORT_SYMBOL_GPL(skx_set_mc_mapping); =20 static u8 skx_get_mc_mapping(struct skx_dev *d, u8 pmc) { edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d\n= ", - pmc, d->mc_mapping[pmc]); + pmc, d->imc[pmc].mc_mapping); =20 - return d->mc_mapping[pmc]; + return d->imc[pmc].mc_mapping; } =20 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source er= r_src) diff --git a/drivers/edac/skx_common.h b/drivers/edac/skx_common.h index 3f6007a97267..95d61d23f89e 100644 --- a/drivers/edac/skx_common.h +++ b/drivers/edac/skx_common.h @@ -135,16 +135,6 @@ struct skx_dev { struct pci_dev *pcu_cr3; /* for HBM memory detection */ u32 mcroute; int num_imc; - /* - * Some server BIOS may hide certain memory controllers, and the - * EDAC driver skips those hidden memory controllers. However, the - * ADXL still decodes memory error address using physical memory - * controller indices. The mapping table is used to convert the - * physical indices (reported by ADXL) to the logical indices - * (used the EDAC driver) of present memory controllers during the - * error handling process. - */ - u8 mc_mapping[NUM_IMC]; struct skx_imc { struct mem_ctl_info *mci; struct pci_dev *mdev; /* for i10nm CPU */ @@ -156,6 +146,16 @@ struct skx_dev { u8 mc; /* system wide mc# */ u8 lmc; /* socket relative mc# */ u8 src_id; + /* + * Some server BIOS may hide certain memory controllers, and the + * EDAC driver skips those hidden memory controllers. However, the + * ADXL still decodes memory error address using physical memory + * controller indices. The mapping table is used to convert the + * physical indices (reported by ADXL) to the logical indices + * (used the EDAC driver) of present memory controllers during the + * error handling process. + */ + u8 mc_mapping; struct skx_channel { struct pci_dev *cdev; struct pci_dev *edev; --=20 2.43.0 From nobody Sun Oct 5 16:18:50 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26EA61DC9BB; Thu, 31 Jul 2025 14:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973891; cv=none; b=KRwvisc/odjAwC7+X6P35YN76bc+UK6YH2HpAupLYiei1PpB4pjB3zXnmLHrp75CO3Bd3udajqE12LDzj7Hc1r23qZqTjyn4fnJE/keNjb+PbyfawzcIYyS1/cAm102XJJEZX9yILhjoZgel0DTqq+mLzmeJLrElN9+ZOqM2toA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973891; c=relaxed/simple; bh=kTWrovbKWg33ZgoJgUOfy8Y/8vnqhpN1y/lXj9BnxzY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FRsLfFmB7qKhH6LTnuY8JFckrv+sXp7P7BDkYpuIpQQCxtlcb7Py60s2T6F6i1QhqLGjtVhDT60H68VMNYJRjXoVo/MLhRxQ1IlUt4gfqhDznDe6ZZjAfh6QlFjYGVIF4h8KaszHmI/6a6Y41+iYG8Mo6z/+1tdbALmQ6DsV6qI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fLbCFBZI; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fLbCFBZI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753973890; x=1785509890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kTWrovbKWg33ZgoJgUOfy8Y/8vnqhpN1y/lXj9BnxzY=; b=fLbCFBZIaORvoP0JQBw4Q62KxxYSz9Q0cmGHxLhezYRgnhN42y2L7p9I IXdUSBYeoJmsNBqMtpZOsSMwcGNi2XJqg171ygaJCRfxTcKHsh4zjH8iH cejXqqdsD5TJWVLVS62PCVQHlSVUhhQ9fLMvfV+gk8vMltg4w6wuvJERo +VDhP/1C6I2IMa5jUwpO2XPl+YaDfNPCa3kJaC4UxWh0jrJEq8o3hHtnD xUH52FU9ajJS2+MocxhBim1F7OnM7necfXoK/IVNWLbGTE8Kjq90AJlus 3XMdV1X+CXqqlit5Lk9dhumpw2LT9IZaKFbDHsafVXrgjrHS/MLUIv+o+ w==; X-CSE-ConnectionGUID: wR/HiQzaSuyOzsYgCdRyTQ== X-CSE-MsgGUID: MnrckdwXReibtFp7W2AWhA== X-IronPort-AV: E=McAfee;i="6800,10657,11508"; a="56231762" X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="56231762" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:10 -0700 X-CSE-ConnectionGUID: jZYnWDyJSbGmJpZrMokKTw== X-CSE-MsgGUID: 8yZJEhskQhyhZt2fVJPlZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="163633447" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:08 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , James Morse , Mauro Carvalho Chehab , Robert Richter , Lai Yi , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] EDAC/skx_common: Swap memory controller index mapping Date: Thu, 31 Jul 2025 22:55:30 +0800 Message-ID: <20250731145534.2759334-4-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> References: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current mapping of memory controller indices is from physical index [1] to logical index [2], as show below: skx_dev->imc[pmc].mc_mapping =3D lmc Since skx_dev->imc[] is an array of present memory controller instances, mapping memory controller indices from logical index to physical index, as show below, is more reasonable. This is also a preparatory step for making skx_dev->imc[] a flexible array. skx_dev->imc[lmc].mc_mapping =3D pmc Both mappings are equivalent. No functional changes intended. [1] Indices for memory controllers include both those present to the OS and those disabled by BIOS. [2] Indices for memory controllers present to the OS. Signed-off-by: Qiuxu Zhuo --- drivers/edac/skx_common.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index 94a66b28751a..744706334b9d 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -130,7 +130,7 @@ static void skx_init_mc_mapping(struct skx_dev *d) * the logical indices of the memory controllers enumerated by the * EDAC driver. */ - for (int i =3D 0; i < NUM_IMC; i++) + for (int i =3D 0; i < d->num_imc; i++) d->imc[i].mc_mapping =3D i; } =20 @@ -139,22 +139,28 @@ void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8= lmc) edac_dbg(0, "Set the mapping of mc phy idx to logical idx: %02d -> %02d\n= ", pmc, lmc); =20 - d->imc[pmc].mc_mapping =3D lmc; + d->imc[lmc].mc_mapping =3D pmc; } EXPORT_SYMBOL_GPL(skx_set_mc_mapping); =20 -static u8 skx_get_mc_mapping(struct skx_dev *d, u8 pmc) +static int skx_get_mc_mapping(struct skx_dev *d, u8 pmc) { - edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d\n= ", - pmc, d->imc[pmc].mc_mapping); + for (int lmc =3D 0; lmc < d->num_imc; lmc++) { + if (d->imc[lmc].mc_mapping =3D=3D pmc) { + edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d= \n", + pmc, lmc); =20 - return d->imc[pmc].mc_mapping; + return lmc; + } + } + + return -1; } =20 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source er= r_src) { + int i, lmc, len =3D 0; struct skx_dev *d; - int i, len =3D 0; =20 if (res->addr >=3D skx_tohm || (res->addr >=3D skx_tolm && res->addr < BIT_ULL(32))) { @@ -218,7 +224,13 @@ static bool skx_adxl_decode(struct decoded_addr *res, = enum error_source err_src) return false; } =20 - res->imc =3D skx_get_mc_mapping(d, res->imc); + lmc =3D skx_get_mc_mapping(d, res->imc); + if (lmc < 0) { + skx_printk(KERN_ERR, "No lmc for imc %d\n", res->imc); + return false; + } + + res->imc =3D lmc; =20 for (i =3D 0; i < adxl_component_count; i++) { if (adxl_values[i] =3D=3D ~0x0ull) --=20 2.43.0 From nobody Sun Oct 5 16:18:50 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCFCB1C07C3; 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charset="utf-8" The current skx->imc[NUM_IMC] array of memory controller instances is sized using the macro NUM_IMC. Each time EDAC support is added for a new CPU, NUM_IMC needs to be updated to ensure it is greater than or equal to the number of memory controllers for the new CPU. This approach is inconvenient and results in memory waste for older CPUs with fewer memory controllers. To address this, make skx->imc[] a flexible array and determine its size from configuration data or at runtime. Suggested-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- drivers/edac/skx_common.c | 3 ++- drivers/edac/skx_common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index 744706334b9d..dffd75144060 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -343,7 +344,7 @@ int skx_get_all_bus_mappings(struct res_config *cfg, st= ruct list_head **list) if (!pdev) break; ndev++; - d =3D kzalloc(sizeof(*d), GFP_KERNEL); + d =3D kzalloc(struct_size(d, imc, imc_num), GFP_KERNEL); if (!d) { pci_dev_put(pdev); return -ENOMEM; diff --git a/drivers/edac/skx_common.h b/drivers/edac/skx_common.h index 95d61d23f89e..e7038fd45d06 100644 --- a/drivers/edac/skx_common.h +++ b/drivers/edac/skx_common.h @@ -172,7 +172,7 @@ struct skx_dev { u8 colbits; } dimms[NUM_DIMMS]; } chan[NUM_CHANNELS]; - } imc[NUM_IMC]; + } imc[]; }; =20 struct skx_pvt { --=20 2.43.0 From nobody Sun Oct 5 16:18:50 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 823C51F3FE9; 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a="56231840" X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="56231840" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:21 -0700 X-CSE-ConnectionGUID: Gs0pXgnZQBGutLeawivLeA== X-CSE-MsgGUID: ywXNU/UfS3WGFz0jVL0Q9w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="163633540" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:19 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , James Morse , Mauro Carvalho Chehab , Robert Richter , Lai Yi , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] EDAC/skx_common: Remove redundant upper bound check for res->imc Date: Thu, 31 Jul 2025 22:55:32 +0800 Message-ID: <20250731145534.2759334-6-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> References: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The following upper bound check for the memory controller physical index decoded by ADXL is the only place where use the macro 'NUM_IMC' is used: res->imc > NUM_IMC - 1 Since this check is already covered by skx_get_mc_mapping(), meaning no memory controller logical index exists for an invalid memory controller physical index decoded by ADXL, remove the redundant upper bound check so that the definition for 'NUM_IMC' can be cleaned up (in another patch). Signed-off-by: Qiuxu Zhuo --- drivers/edac/skx_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index dffd75144060..44f5b5402e31 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -207,7 +207,7 @@ static bool skx_adxl_decode(struct decoded_addr *res, e= num error_source err_src) res->cs =3D (int)adxl_values[component_indices[INDEX_CS]]; } =20 - if (res->imc > NUM_IMC - 1 || res->imc < 0) { + if (res->imc < 0) { skx_printk(KERN_ERR, "Bad imc %d\n", res->imc); return false; } --=20 2.43.0 From nobody Sun Oct 5 16:18:50 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F3731CF5C0; Thu, 31 Jul 2025 14:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973909; cv=none; b=a0f3VXKubrgIFN4Tq+ZojTUGYbMLzCHsVHh9U5dQTFWqP3aT+FmduGCAzMHBxBdUcuYdTLXoVfjXFcHhV7aSC4+deA8l5WKyZcEY4An1bNUW/qed0yjrHb8hNfaO5uRlus5NuXy5v1Ev5pLTC3mI2NNUd2xT56Kj8OmE91sEQDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973909; c=relaxed/simple; bh=6DVFCE09TQcKFTBk76h9iCXAZesWmZ9XWwRWAqxW2OU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pIkWqYuO5uzRxvmfEVhHUVmXsEzOOHZRxTcLN1nOM2E6LHKEDO/NHWDwQf4pyRzkD4xc/JkQhIxCbZO4chK0x6MIUXpdo4p7uX9X4OqCCJYdsUwnLSxi7G1ogNagOUMFSI1//cGGgwXlgRhMQdnGyWfTf7hkEa2trjtWccPlkh4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FGIHw0my; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FGIHw0my" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753973908; x=1785509908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6DVFCE09TQcKFTBk76h9iCXAZesWmZ9XWwRWAqxW2OU=; b=FGIHw0myeUmNLumaLlt5+o88Rs9ifSg06qn2+5s1PcFWhhfKgMgm8hJy S7KkcbBJZ0DG6NdERuMDnANJMXrSEaqVeFHA7zwLFoHla+MjMpjCsb5VA Co8jwpQRX5jQOE0CymcQ6qNe1YWrttnZkoZDOudIt4/8EVvR2e2ZZ+qvM fnY6dC9Hloz1p5mbk29U/zaVdtGzwEcNItmuw2KTqI33EeuVJ/dXJ2QS8 Uxl+GNQjLC6U0ZgZ9521oB5ugpYoOCfEq+YJaE7i2zkqS+k0fFf9YD9+U ie6XrpgBm9DBa5va57ujBkW1By1Scy8gAToDvf6Q6RyQoovqoN62AnmXB Q==; X-CSE-ConnectionGUID: P0TmDlwiQ4e8om1hcxcCfw== X-CSE-MsgGUID: rLQ4Uos1QtuJ0m8qSJ6Low== X-IronPort-AV: E=McAfee;i="6800,10657,11508"; a="56231877" X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="56231877" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:27 -0700 X-CSE-ConnectionGUID: MSuvZCpXRYiSbVxi2clMsQ== X-CSE-MsgGUID: RoPT7rLSTYWJM8kIFKe+MQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="163633571" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:24 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , James Morse , Mauro Carvalho Chehab , Robert Richter , Lai Yi , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] EDAC/i10nm: Reallocate skx_dev list if preconfigured cnt != runtime cnt Date: Thu, 31 Jul 2025 22:55:33 +0800 Message-ID: <20250731145534.2759334-7-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> References: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ideally, read the present DDR memory controller count first and then allocate the skx_dev list using this count. However, this approach requires adding a significant amount of code similar to skx_get_all_bus_mappings() to obtain the PCI bus mappings for the first socket and use these mappings along with the related PCI register offset to read the memory controller count. Given that the Granite Rapids CPU is the only one that can detect the count of memory controllers at runtime (other CPUs use the count in the configuration data), to reduce code complexity, reallocate the skx_dev list only if the preconfigured count of DDR memory controllers differs from the count read at runtime for Granite Rapids CPU. Signed-off-by: Qiuxu Zhuo --- drivers/edac/i10nm_base.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index a3fca2567752..d0218df66a34 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -467,17 +467,18 @@ static int i10nm_get_imc_num(struct res_config *cfg) return -ENODEV; } =20 - if (imc_num > I10NM_NUM_DDR_IMC) { - i10nm_printk(KERN_ERR, "Need to make I10NM_NUM_DDR_IMC >=3D %d\n", imc_= num); - return -EINVAL; - } - if (cfg->ddr_imc_num !=3D imc_num) { /* - * Store the number of present DDR memory controllers. + * Update the configuration data to reflect the number of + * present DDR memory controllers. */ cfg->ddr_imc_num =3D imc_num; edac_dbg(2, "Set DDR MC number: %d", imc_num); + + /* Release and reallocate skx_dev list with the updated number. */ + skx_remove(); + if (skx_get_all_bus_mappings(cfg, &i10nm_edac_list) <=3D 0) + return -ENODEV; } =20 return 0; --=20 2.43.0 From nobody Sun Oct 5 16:18:50 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 661A31DD543; Thu, 31 Jul 2025 14:58:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973913; cv=none; b=NhoEhbcVe4AaUOb6L0GCDzFzqP5aS22kairzLg7rUN84AqI7eHgt8YxL7V1n1pHNt//r0IU/lbtaUr/dgj0IVIe1SWSsFtqQVXV/iblmWqOuwGjaZYuDhKKeLKZ3P5jyjLCdr7MqSa4KA+OfGjUp9xzmcSxUrixMkoNaN+2cfVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753973913; c=relaxed/simple; bh=nqx9yQrbzlyUy8pgUZ438nvDoogRwJuQY/PaaUd8hYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I/+igQaBlO1A3Gg9YeMgF9AOMEdM7/o5LS4CppxmQpHUYWIWmxxW2mqYgmezRaeswU6VwKTD8mOgUKlfno6j27kJkVyUnCxBXX8EU851rdPepk06e+94yteN4TC9DOhyFwwG2Y5FlS+C+D6Hl8bmPrtIZeIqT1nWBEP4vc0qQaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FmO022tU; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FmO022tU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753973912; x=1785509912; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nqx9yQrbzlyUy8pgUZ438nvDoogRwJuQY/PaaUd8hYo=; b=FmO022tUpibCUUdCXUxpsKWhfiNzEAZraQ9T5w2gSD2kJvUAdbOqSGJx ZmbMa1COv+XXqf7tcDstCQ1DyE9HSINKfRbxaA2c7BRtPeFKcMUBrzCuZ Z90QyvkIhY8vmHRPXNWFfd/GoVWx3fGBrkApBERuu/4XNexF6EMfmzcMQ Q1SBdikIO2+JuhIptxAXPpJHU2G38uTuNgEujq/r2MheFCcJLlMBBwTCZ dvEUkn04w0cLQQ09foTqcmMX4JyjIxTIzcrO1EI9X7a677BfcgdNAXeuI bDkeywuwVyV8g8g7I4+rIfTEtwR1o9ewh+WkFTW/wycan3j3Y2m/XZCh3 Q==; X-CSE-ConnectionGUID: RbHd191jQweRpbsIBQuXNQ== X-CSE-MsgGUID: 24IMnCVGRb6QboyxdCbn8g== X-IronPort-AV: E=McAfee;i="6800,10657,11508"; a="56231893" X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="56231893" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:32 -0700 X-CSE-ConnectionGUID: 4+D2s0aoSYKl3xpn6jCNcw== X-CSE-MsgGUID: kK1k6PcKTSi7sFWK7Gztzw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,353,1747724400"; d="scan'208";a="163633606" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 07:58:30 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , James Morse , Mauro Carvalho Chehab , Robert Richter , Lai Yi , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] EDAC/skx_common: Remove unused *NUM*_IMC macros Date: Thu, 31 Jul 2025 22:55:34 +0800 Message-ID: <20250731145534.2759334-8-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> References: <20250731145534.2759334-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are no references to the *NUM*_IMC macros, so remove them. Signed-off-by: Qiuxu Zhuo --- drivers/edac/skx_common.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/edac/skx_common.h b/drivers/edac/skx_common.h index e7038fd45d06..73ba89786cdf 100644 --- a/drivers/edac/skx_common.h +++ b/drivers/edac/skx_common.h @@ -29,23 +29,18 @@ #define GET_BITFIELD(v, lo, hi) \ (((v) & GENMASK_ULL((hi), (lo))) >> (lo)) =20 -#define SKX_NUM_IMC 2 /* Memory controllers per socket */ #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */ #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */ =20 -#define I10NM_NUM_DDR_IMC 12 #define I10NM_NUM_DDR_CHANNELS 2 #define I10NM_NUM_DDR_DIMMS 2 =20 -#define I10NM_NUM_HBM_IMC 16 #define I10NM_NUM_HBM_CHANNELS 2 #define I10NM_NUM_HBM_DIMMS 1 =20 -#define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC) #define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANN= ELS) #define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS) =20 -#define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC) #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) #define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS) =20 --=20 2.43.0