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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:02:01 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/8] arm64: dts: s32g2: Add the Software Timer Watchdog (SWT) nodes Date: Thu, 31 Jul 2025 16:01:38 +0200 Message-ID: <20250731140146.62960-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Referred in the documentation as the Software Timer Watchdog (SWT), the s32g2 has 7 watchdogs. The number of watchdogs is designed to allow dedicating one watchdog per Cortex-M7/A53 present on the SoC. Add the SWT nodes in the device tree. Signed-off-by: Daniel Lezcano --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 56 ++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 1783edb81350..478899d4dd06 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -317,6 +317,38 @@ usdhc0-200mhz-grp4 { }; }; =20 + swt0: watchdog@40100000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40100000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt1: watchdog@40104000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40104000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt2: watchdog@40108000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40108000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x4010c000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + stm0: timer@4011c000 { compatible =3D "nxp,s32g2-stm"; reg =3D <0x4011c000 0x3000>; @@ -445,6 +477,30 @@ i2c2: i2c@401ec000 { status =3D "disabled"; }; =20 + swt4: watchdog@40200000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40200000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt5: watchdog@40204000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40204000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt6: watchdog@40208000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40208000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + stm4: timer@4021c000 { compatible =3D "nxp,s32g2-stm"; reg =3D <0x4021c000 0x3000>; --=20 2.43.0