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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:01:57 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 1/8] arm64: dts: s32g2: Add the System Timer Module nodes Date: Thu, 31 Jul 2025 16:01:34 +0200 Message-ID: <20250731140146.62960-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The s32g2 has a STM module containing 8 timers. Each timer has a dedicated interrupt and share the same clock. Add the timers STM0->STM6 nodes for the s32g2 SoC. The STM7 node is not added because it is slightly different and needs an extra property which will be added later when supported by the driver. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 63 ++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index ea1456d361a3..1783edb81350 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -317,6 +317,42 @@ usdhc0-200mhz-grp4 { }; }; =20 + stm0: timer@4011c000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x4011c000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + stm1: timer@40120000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40120000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + stm2: timer@40124000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40124000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + stm3: timer@40128000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40128000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + edma0: dma-controller@40144000 { compatible =3D "nxp,s32g2-edma"; reg =3D <0x40144000 0x24000>, @@ -409,6 +445,33 @@ i2c2: i2c@401ec000 { status =3D "disabled"; }; =20 + stm4: timer@4021c000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x4021c000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm5: timer@40220000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40220000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm6: timer@40224000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40224000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + edma1: dma-controller@40244000 { compatible =3D "nxp,s32g2-edma"; reg =3D <0x40244000 0x24000>, --=20 2.43.0