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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:01:57 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 1/8] arm64: dts: s32g2: Add the System Timer Module nodes Date: Thu, 31 Jul 2025 16:01:34 +0200 Message-ID: <20250731140146.62960-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The s32g2 has a STM module containing 8 timers. Each timer has a dedicated interrupt and share the same clock. Add the timers STM0->STM6 nodes for the s32g2 SoC. The STM7 node is not added because it is slightly different and needs an extra property which will be added later when supported by the driver. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 63 ++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index ea1456d361a3..1783edb81350 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -317,6 +317,42 @@ usdhc0-200mhz-grp4 { }; }; =20 + stm0: timer@4011c000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x4011c000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + stm1: timer@40120000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40120000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + stm2: timer@40124000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40124000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + stm3: timer@40128000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40128000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + edma0: dma-controller@40144000 { compatible =3D "nxp,s32g2-edma"; reg =3D <0x40144000 0x24000>, @@ -409,6 +445,33 @@ i2c2: i2c@401ec000 { status =3D "disabled"; }; =20 + stm4: timer@4021c000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x4021c000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm5: timer@40220000 { + compatible =3D "nxp,s32g2-stm"; + reg =3D <0x40220000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:01:58 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 2/8] arm64: dts: s32g274-rd2: Enable the STM timers Date: Thu, 31 Jul 2025 16:01:35 +0200 Message-ID: <20250731140146.62960-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the timers STM0 -> STM3 on the s32g274-rd2 The platform has 4 CPUs, and the Linux STM timer driver is instantiated per CPU. Enable 4 STM timers that can be used as replacements for the ARM architected timers. The remaining STM timers are not useful to the Linux kernel and provide no benefit, so they are left disabled. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/b= oot/dts/freescale/s32g274a-rdb2.dts index b5ba51696f43..505776d19151 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -40,6 +40,22 @@ &uart1 { status =3D "okay"; }; =20 +&stm0 { + status =3D "okay"; +}; + +&stm1 { + status =3D "okay"; +}; + +&stm2 { + status =3D "okay"; +}; + +&stm3 { + status =3D "okay"; +}; + &usdhc0 { pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; pinctrl-0 =3D <&pinctrl_usdhc0>; --=20 2.43.0 From nobody Sun Dec 14 02:01:17 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D994D2D23A5 for ; Thu, 31 Jul 2025 14:02:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753970523; cv=none; b=bGDu6Y8vU8cxtnxiE+f+9Uy6zFXSaQ4GQjZ3EmzUbM+d2ldzomTxC/2KYbXQdLOcW1I3aFmiZhlH2P9MjhqmUnC6p7ng6QleWzk7R/1RSh2gruJDNe2NvJScI8uCxvGWpwXrHbdGSgnSKjJcHBgB3SIo/Adf6BNykrSomCWCpR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753970523; c=relaxed/simple; bh=vcA02yLSNwMr2sw3WTjr/QQMCrQppMAlK1ftMTli3h8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AyQGk9y+T+iyZKcPVOnYVPHBBESqeNlIzsLlRd1YhOS9ZfaY1/SDOQOMWdMXq/MH1bnCs0CLenoy0ZOTVLI2RPT6rOKaTmllQALF+6zN2Ft7ABCi+YZfYzmUWXzlgu92GmlrdQtEUjEyWAHhuC0F4Xxpq9/bDrXW0Bl3Juwy7h0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=pvqE5oat; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pvqE5oat" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-451d3f72391so4619215e9.3 for ; Thu, 31 Jul 2025 07:02:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753970520; x=1754575320; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aB00SSfP6c+OHo+3LviFK6KTCkRiE6kjMG1sy5ThVvM=; b=pvqE5oatdDMxVpLhdugSamCoWqFPJboKanMleT8QPbmOIKbvCGGMV5AzRzFGVxPE6o WOLtuAmq5+wx2FcENC2Nw1EZ3c1Rv7Ci8fyiaUFZEaFniw8e6/uuC4/j2dw6Hr1yvcyv T0hxbtYJUS6g5/apg6uge6xnhJ9TkGtGi4iHZPhyS8490ZMFb5cxki7zwrfxcDN54yxF NR/Mb6rG7AOCKv1RZGPOCMiKYGjQrk7Ay9HJejGq4WwU01/QPuKAepRb3aSgWdRRKSrr GrpMiKQojygNHC7a8MnIRf7Uj3k11zj00ymtyh1W/uMWgDnmcdB408ugvQyUbDtLy5Da gAAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753970520; x=1754575320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aB00SSfP6c+OHo+3LviFK6KTCkRiE6kjMG1sy5ThVvM=; b=JE63+1GovfedEyFqyoxG2W2GKz0y+ShiM0S/boozg4Nzhf1njwf6UQzsxJYQ9IKHID xfDjawlIiZaclNLD/Q68Rjih3ejkPF87Auei+W93ushaVhIStUx9Z53nTGZi0D8rJ0nE w+5prNnX4KYf5CYhVaqz2fHSWyJQ2FeTYxHpWiimxL+biJHI64pCH/snLAN/3Q78Q/kW 5xJcHYBDBFmqu9AIGXxy6j9TAP2WOS1YNhDj1VNbhWy1gJWYXg7jYK2R7go7qXsxWsv2 4yNE1cmlc95ur3LOSyuTA78kz6nN3ZAEqsjSI7vJN9uo7eTg8A3UF86ukbdXvsZBcxqZ kJ7w== X-Forwarded-Encrypted: i=1; AJvYcCXntbBv+zKz0tl3ETFJcOXH9JV5IiTLcGSlhSneUlWeai1tuIzY1ljtVUxZe5JhmZpPM8i79Y+0prh1y+k=@vger.kernel.org X-Gm-Message-State: AOJu0Yw29WyTZEEFQHYyaFYZjI2SL4nTuteucGE8Pc5qYqahoiZ0QJK8 QERWv14P1kZN6wRPqYqsMy52E4j3sQk4WqqvXdE/B8NKPSrDmUCxYr0HqeGfi5ALEXdC1vrmPJE lJX9b X-Gm-Gg: ASbGncvKP6EIsr5Si6Cqc5fCsx/X4ELAgm2an7ja13aZqQnUQB/1qq8rZTwnZSNNA4Z 5KaNkO9aj67S/27n/wZrfJH95vmvFKux4El2iQY+oGn4l6mm+OY2OSPicSzMS/8QmQaXpyEvWS0 jPo2SQLMLwYw4DFw3W3SzrFXblcQaXYu6D+Y6iZ5J5yb3oyLZ43iSIp6eeLno08SMWEvqds1xhZ cHq63011IwV/5vjF2+9QI01Dqs21GMQkbc3Op3SufiXIrTjhGV0MhwUWOaVjS4FWjwyWIvDIvlk p4OlReMu1muyZ62eUZn1LeyzkWV8KaIXa+PvVovSoWcsC11fzob2PNTHamRVY30XF3uc4PAZHQq 4WYLDRaeYTMJ+YUEhvN230GDXi5rOL72YTy5/ajIq9s/Ccnr8 X-Google-Smtp-Source: AGHT+IGqwlW5ma8WPKveKqUhTUAr3VgKYFhAtuL+0U//6ALH9ryJa3alHyJCYGFqgrUVq1o4bMWuuQ== X-Received: by 2002:a05:600c:8711:b0:455:fc16:9eb3 with SMTP id 5b1f17b1804b1-45892bd7be5mr65100585e9.33.1753970519969; Thu, 31 Jul 2025 07:01:59 -0700 (PDT) Received: from mai.. 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:01:59 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 3/8] arm64: dts: s32g3: Add the System Timer Module nodes Date: Thu, 31 Jul 2025 16:01:36 +0200 Message-ID: <20250731140146.62960-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The s32g3 has a STM module containing 12 timers. Each timer has a dedicated interrupt and share the same clock. Add the STM0->STM11 nodes for the s32g3 SoC. The STM7 node is not added because it is slightly different and needs an extra property which will be added later when supported by the driver. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 99 ++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index 991dbfbfa203..c2c986f03986 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -374,6 +374,42 @@ usdhc0-200mhz-grp4 { }; }; =20 + stm0: timer@4011c000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x4011c000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm1: timer@40120000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x40120000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm2: timer@40124000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x40124000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm3: timer@40128000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x40128000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + edma0: dma-controller@40144000 { compatible =3D "nxp,s32g3-edma", "nxp,s32g2-edma"; reg =3D <0x40144000 0x24000>, @@ -471,6 +507,33 @@ i2c2: i2c@401ec000 { status =3D "disabled"; }; =20 + stm4: timer@4021c000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x4021c000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm5: timer@40220000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x40220000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm6: timer@40224000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x40224000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + edma1: dma-controller@40244000 { compatible =3D "nxp,s32g3-edma", "nxp,s32g2-edma"; reg =3D <0x40244000 0x24000>, @@ -560,6 +623,42 @@ usdhc0: mmc@402f0000 { status =3D "disabled"; }; =20 + stm8: timer@40520000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x40520000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + interrupts =3D ; + status =3D "disabled"; + }; + + stm9: timer@40524000 { + compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg =3D <0x40524000 0x3000>; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:02:00 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 4/8] arm64: dts: s32g399a-rdb3: Enable the STM timers Date: Thu, 31 Jul 2025 16:01:37 +0200 Message-ID: <20250731140146.62960-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The platform has 8 CPUs, and the Linux STM timer driver is instantiated per CPU. Enable 8 STM timers that can be used as replacements for the ARM architected timers. The remaining STM timers are not useful to the Linux kernel and provide no benefit, so they are left disabled. Enable STM0 to STM6 and STM8 on the s32g399a-rdb3 platform. STM7 is skipped, as it differs slightly from the others and requires an additional property to be properly handled by the driver. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- .../boot/dts/freescale/s32g399a-rdb3.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/b= oot/dts/freescale/s32g399a-rdb3.dts index 802f543cae4a..467e0c105c3f 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -40,6 +40,38 @@ &uart1 { status =3D "okay"; }; =20 +&stm0 { + status =3D "okay"; +}; + +&stm1 { + status =3D "okay"; +}; + +&stm2 { + status =3D "okay"; +}; + +&stm3 { + status =3D "okay"; +}; + +&stm4 { + status =3D "okay"; +}; + +&stm5 { + status =3D "okay"; +}; + +&stm6 { + status =3D "okay"; +}; + +&stm8 { + status =3D "okay"; +}; + &i2c4 { current-sensor@40 { compatible =3D "ti,ina231"; --=20 2.43.0 From nobody Sun Dec 14 02:01:17 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 531A72D373A for ; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:02:01 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/8] arm64: dts: s32g2: Add the Software Timer Watchdog (SWT) nodes Date: Thu, 31 Jul 2025 16:01:38 +0200 Message-ID: <20250731140146.62960-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Referred in the documentation as the Software Timer Watchdog (SWT), the s32g2 has 7 watchdogs. The number of watchdogs is designed to allow dedicating one watchdog per Cortex-M7/A53 present on the SoC. Add the SWT nodes in the device tree. Signed-off-by: Daniel Lezcano --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 56 ++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 1783edb81350..478899d4dd06 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -317,6 +317,38 @@ usdhc0-200mhz-grp4 { }; }; =20 + swt0: watchdog@40100000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40100000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt1: watchdog@40104000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40104000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt2: watchdog@40108000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40108000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x4010c000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + stm0: timer@4011c000 { compatible =3D "nxp,s32g2-stm"; reg =3D <0x4011c000 0x3000>; @@ -445,6 +477,30 @@ i2c2: i2c@401ec000 { status =3D "disabled"; }; =20 + swt4: watchdog@40200000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40200000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt5: watchdog@40204000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40204000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt6: watchdog@40208000 { + compatible =3D "nxp,s32g2-swt"; + reg =3D <0x40208000 0x1000>; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:02:03 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 6/8] arm64: dts: s32g274-rd2: Enable the SWT watchdog Date: Thu, 31 Jul 2025 16:01:39 +0200 Message-ID: <20250731140146.62960-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SWT0 is directly connected to the reset line and only one instance is useful for its purpose. Let's enable it for the s32g274-rd2. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/b= oot/dts/freescale/s32g274a-rdb2.dts index 505776d19151..4f58be68c818 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -56,6 +56,10 @@ &stm3 { status =3D "okay"; }; =20 +&swt0 { + status =3D "okay"; +}; + &usdhc0 { pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; pinctrl-0 =3D <&pinctrl_usdhc0>; --=20 2.43.0 From nobody Sun Dec 14 02:01:17 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BCC32D3EFA for ; Thu, 31 Jul 2025 14:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753970529; cv=none; b=Wg5vDG1D/WZI74vadDcIiQJY1+G1ss3f8Rs+0ZBJeFOyQWtalyuhl0WCKvtIjx3bz+NilYErxulFXBY1x32/Dv96bZt4IhDSwZYEYw9h4X59yNrGFmC92EM2U6YSI3eRTdTx2Ro+2v+/ieDkTCYj2yIj7viFrOetKPkeWpxugVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753970529; c=relaxed/simple; bh=b/zd24rk+o9OlSLaMVLq9Pw8EaD6LUwOrTp1/I6fhs8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dyfFbQFHDiTrZMP6zk6YbQ1wNS9WUgtWA61NTv16Zx3QxV6xogZAhLYDCdK4x6i/LUeUTzWwRAdJHFmdvO6VLzEmRafVtyI3KHr737qXMhebHQXVDcWYTOoiB0Da1NhUYfjgHMAngMrql6i1Hd6V8qEKrA87KfZjvcj99dDPfmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=uJknp74r; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uJknp74r" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-45619d70c72so15755155e9.0 for ; Thu, 31 Jul 2025 07:02:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753970525; x=1754575325; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z64nEAaTCVKG57zoeUfRDIzBYeQhTygoaGUdQv/8uC4=; b=uJknp74rs/X1QihoWCiZnwMJDkH8pC44ehKDi4oP3WbIky72QVPdibeydMMxWOdheh wWctli8nGgzqR2XSnn7hz+S9wkv5PBlBtNU7IKxYQ3gqG03znn/xRGMkZ54qPlZ6/qeh i9d6Ts57iTObidoMEvHFZFRKGSy74ACtklUWRf/+MOdsXHlXZx9Ju/iU+1lRaKdi2bjl VNnarGLhj4BKYD6VUrlPDZZ+suAa8t/K9fKDSnWMuLRqFAqcdADVYinljzl59BT/sFq7 /W5j93Pu+saeGUGKBWz0kWhr4T5qJSPCNIbYYBLTFovj5yWuF/THixtu2PBAM3ZAqPxv a9qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753970525; x=1754575325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z64nEAaTCVKG57zoeUfRDIzBYeQhTygoaGUdQv/8uC4=; b=Sy1JkY/FD3FgFa0DSGd2ipau3tRjM3rYGU7dbV8IXOK4Gw440LDMXLMXFFb8dEUWfy rnaydxSpKjFSUCYlogNhTHBzW4TaLzykwvj7RLi3EDic9DalF8ibUgibWqAzsnDkzQkb f0TFDouDy74uLXGt7oLKJsOHFDdKP2yVnMlrk/9agRAiJz20jY5oI/l2QwCgePLF+A4/ o/sMx7Axyu2BKVwdbyOQTZL9y4mz1KOiSAiDoEVWa3CXPCIMOHFBe5XgVG5kTd98hFt4 J3dlx7OY8pAelhxcvK0LTwGbNjHZFDAfdjFB1l76KhEGDGVJv32kC4QMSUlq4FT9joyP +hJw== X-Forwarded-Encrypted: i=1; AJvYcCVbJScK4MWihL7/+pbZVObKaOpF1EHfN9/HLvF8D3mNMkvVIcUj5xSlXl1t0WRYwQZrUKBk2pczz7a/j0g=@vger.kernel.org X-Gm-Message-State: AOJu0YzibGsiKbKHF9cIdZOzcnakMg85laPs23vEN5JpjhvO78xoeDii vKv9K0jrOAfAwbl8JhoYwxd2wUZ39TFY6h/fqiyxkCRBzGfdrtMrEr2QmvvCZBrSnNA= X-Gm-Gg: ASbGncubvJ/loKN7pRx7SMs9cENLydi6Aswz7pGfLhTsZeqtWaKhts9pzB6TCoiw212 XYDuNTlmhQ62dje9FKLZE4K3WfqVyxbbpCYvE+9BItOork2NrLWmWgqB4lbs8zW3FGH5S8guP3c Gjz4R0Q4bF5PzHjHtMU48Y8APEXdW2KjiVl9vmDcjE9vhn/Lb4L8gt79hLbGoi2oIYhK/SoU0/g K0xezY/5fiEtkbIgDiCCWhUXhgQzEM2mCuWfZAW0eGk2ha/oVLruYHwfEavYsbSuha2LaTaARbJ ievLbLc0hNnQOvfX/C3BhehBp5JTrxrnvGFm0Td3mMe5+Lim/SWwFAiTMw144HzJ7b8cgKplV4/ 4vHkRIrAGPbm092EdRyF9dz3lAmONVHrQrm+Qx39kIw7+o73w X-Google-Smtp-Source: AGHT+IG0Fg0obv6QNkBb8H8gLrRktxs7boJ84AHt095fewSVZFjevx0sKm5v6FUBwWIQGMfsDR/Uww== X-Received: by 2002:a5d:64ec:0:b0:3b7:8cf0:4b2a with SMTP id ffacd0b85a97d-3b79d4e3623mr1743875f8f.16.1753970524846; Thu, 31 Jul 2025 07:02:04 -0700 (PDT) Received: from mai.. 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:02:04 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 7/8] arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes Date: Thu, 31 Jul 2025 16:01:40 +0200 Message-ID: <20250731140146.62960-8-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Referred in the documentation as the Software Timer Watchdog (SWT), the s32g3 has 12 watchdogs. The number of watchdogs is designed to allow dedicating one watchdog per Cortex-M7/A53 present on the SoC. Add the SWT nodes in the device tree. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 96 ++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index c2c986f03986..0ceb0807537a 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -374,6 +374,38 @@ usdhc0-200mhz-grp4 { }; }; =20 + swt0: watchdog@40100000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x40100000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt1: watchdog@40104000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x40104000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt2: watchdog@40108000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x40108000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x4010c000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + stm0: timer@4011c000 { compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; reg =3D <0x4011c000 0x3000>; @@ -507,6 +539,38 @@ i2c2: i2c@401ec000 { status =3D "disabled"; }; =20 + swt4: watchdog@40200000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x40200000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt5: watchdog@40204000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x40204000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt6: watchdog@40208000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x40208000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt7: watchdog@4020C000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <0x4020C000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + stm4: timer@4021c000 { compatible =3D "nxp,s32g3-stm", "nxp,s32g2-stm"; reg =3D <0x4021c000 0x3000>; @@ -623,6 +687,38 @@ usdhc0: mmc@402f0000 { status =3D "disabled"; }; =20 + swt8: watchdog@40500000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg =3D <40500000 0x1000>; + clocks =3D <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names =3D "counter", "module", "register"; + status =3D "disabled"; + }; + + swt9: watchdog@40504000 { + compatible =3D "nxp,s32g3-swt", "nxp,s32g2-swt"; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:02:05 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati Subject: [PATCH v2 8/8] arm64: dts: s32g399a-rdb3: Enable the SWT watchdog Date: Thu, 31 Jul 2025 16:01:41 +0200 Message-ID: <20250731140146.62960-9-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org> References: <20250731140146.62960-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SWT0 is directly connected to the reset line and only one instance is useful for its purpose. Let's enable it on the s32g399a-rdb3. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati --- arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/b= oot/dts/freescale/s32g399a-rdb3.dts index 467e0c105c3f..e94f70ad82d9 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -72,6 +72,10 @@ &stm8 { status =3D "okay"; }; =20 +&swt0 { + status =3D "okay"; +}; + &i2c4 { current-sensor@40 { compatible =3D "ti,ina231"; --=20 2.43.0