From nobody Sun Oct 5 16:21:04 2025 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 404E3A94A; Thu, 31 Jul 2025 13:19:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753967964; cv=none; b=Je+jZemOqKqqhGy1xv/3hWVoatWdw/7/ZYbViYdHFJ9Nv1z1HD1/nupTMG1bscyZfluDuvqdKmCtebkyem8Cacm6/zDA2RU0H1McZTAsgWbe97Zv9H/tSR0+pOxjrJTNORJbX64R57uwGVKBU/iqTOrN/vCytmuVgW+VDf0TIDA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753967964; c=relaxed/simple; bh=8r3Fv+M4yTGdiz6h5pXNqXQwzpNc8g8rNb0PDyVc9B0=; h=From:To:Cc:Date:Message-Id:MIME-Version:Subject; b=hmLj7MLISinw0BXnS6v7X71iL2VGfhsM8Dw7n+E2xyfVbkiuORN5dhSLSiqvy3XXDMpwOSXUgHGGikvb433wDsjWtqc8/XJXlI8yHvCbta7hVljm22vGnzo/XGPW51vA9bVEftTlNTSlzKFmISQ93iDNP7zGOtFmpeolhQrzOxs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=A5cf+gf/; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="A5cf+gf/" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Cc:To :From:subject:date:message-id:reply-to; bh=u6pOakssCsfcxux6WyYCgTIITzfS/oiDlxNCjWk9jPU=; b=A5cf+gf/wJZm1cMoZxuX8lktwK C+JUEEfXjvMmrduGv9hJ7/D7JhrnrSly5ci6pG/PEfsSSL9YqWPd+GpSMPAQzFrHDSP/ShnfLjilr q9iAssrVq07RRtkYddrRkW1TVRyJWw+pZacP2l9N2sV6m1ByjZL7ve0wNhke/Tf1zeCw=; Received: from modemcable061.19-161-184.mc.videotron.ca ([184.161.19.61]:49772 helo=localhost.localdomain) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1uhSea-0006PE-Vz; Thu, 31 Jul 2025 08:45:01 -0400 From: Hugo Villeneuve To: Greg Kroah-Hartman , Jiri Slaby , Jon Ringle Cc: hugo@hugovil.com, Hugo Villeneuve , stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Date: Thu, 31 Jul 2025 08:44:50 -0400 Message-Id: <20250731124451.1108864-1-hugo@hugovil.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 184.161.19.61 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP Subject: [PATCH] serial: sc16is7xx: fix bug in flow control levels init X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve When trying to set MCR[2], XON1 is incorrectly accessed instead. And when writing to the TCR register to configure flow control levels, we are incorrectly writing to the MSR register. The default value of $00 is then used for TCR, which means that selectable trigger levels in FCR are used in place of TCR. TCR/TLR access requires EFR[4] (enable enhanced functions) and MCR[2] to be set. EFR[4] is already set in probe(). MCR access requires LCR[7] to be zero. Since LCR is set to $BF when trying to set MCR[2], XON1 is incorrectly accessed instead because MCR shares the same address space as XON1. Since MCR[2] is unmodified and still zero, when writing to TCR we are in fact writing to MSR because TCR/TLR registers share the same address space as MSR/SPR. Fix by first removing useless reconfiguration of EFR[4] (enable enhanced functions), as it is already enabled in sc16is7xx_probe() since commit 43c51bb573aa ("sc16is7xx: make sure device is in suspend once probed"). Now LCR is $00, which means that MCR access is enabled. Also remove regcache_cache_bypass() calls since we no longer access the enhanced registers set, and TCR is already declared as volatile (in fact by declaring MSR as volatile, which shares the same address). Finally disable access to TCR/TLR registers after modifying them by clearing MCR[2]. Note: the comment about "... and internal clock div" is wrong and can be ignored/removed as access to internal clock div registers (DLL/DLH) is permitted only when LCR[7] is logic 1, not when enhanced features is enabled. And DLL/DLH access is not needed in sc16is7xx_startup(). Fixes: dfeae619d781 ("serial: sc16is7xx") Cc: stable@vger.kernel.org Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 5ea8aadb6e69c..9056cb82456f1 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1177,17 +1177,6 @@ static int sc16is7xx_startup(struct uart_port *port) sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, SC16IS7XX_FCR_FIFO_BIT); =20 - /* Enable EFR */ - sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, - SC16IS7XX_LCR_CONF_MODE_B); - - regcache_cache_bypass(one->regmap, true); - - /* Enable write access to enhanced features and internal clock div */ - sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, - SC16IS7XX_EFR_ENABLE_BIT, - SC16IS7XX_EFR_ENABLE_BIT); - /* Enable TCR/TLR */ sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, SC16IS7XX_MCR_TCRTLR_BIT, @@ -1199,7 +1188,8 @@ static int sc16is7xx_startup(struct uart_port *port) SC16IS7XX_TCR_RX_RESUME(24) | SC16IS7XX_TCR_RX_HALT(48)); =20 - regcache_cache_bypass(one->regmap, false); + /* Disable TCR/TLR access */ + sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, SC16IS7XX_MCR_TCRTLR_BIT, = 0); =20 /* Now, initialize the UART */ sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); base-commit: 260f6f4fda93c8485c8037865c941b42b9cba5d2 --=20 2.39.5