From nobody Sun Oct 5 20:12:49 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E99232367C5; Thu, 31 Jul 2025 11:57:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753963046; cv=none; b=pO3k+pWulP2L6V+CxafHhMiCEeTGMVOeGURbOSYZJPXpABu21jMPLi0NTuIyW9ioU/rhxXW1Y+WDpRjun+uNtpFlBAN7ruzbE5nNWA4yi/72YWyzTLqX18vAwzm0LjRY2Kw7ykOIzASefXP9fTxvBn2ZU0RqmyoeMnrW7mlLgjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753963046; c=relaxed/simple; bh=63Kt0YS0GCOV2374eT2S7Ilwhv+fN878acMzagNPu9I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hE4qH7gvlrtSIju1yNdJG2oiCrGeVXidktWG710JzUZoxaW7/6YA+PyWIaX/0IqC+bccDn1RVPGq+UmB18Y1vWlLZ7raH3Vuzjh/UywQ6+lRpBqeI/9HFHqtje9T5VbAjbpmR1wkUpNHpaShD9z1W2OsU3RTlSnbg7wsm2L+BQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xqTUJKta; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xqTUJKta" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 56VBvFGv3481496; Thu, 31 Jul 2025 06:57:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1753963035; bh=z6sZ+TNX9IcKpnhypEPKDNU8G9miBOODLIjgJJ1A5pg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xqTUJKta4gqiJHOtYcJh6lpgL9WJHb2/Q2dXreTfbZ+V419PNQzwXAc2+t59T8K/I RIAywB5SdW/wb2ZbVw9T+eOF7KfH9SJSZlY9ALAAdgL3iPNgDBpV5lxVFamVEprea/ PVC8Ok7zohWY5COCDGjyOwoZ6Wh15xtegDwNbNFA= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 56VBvFxZ2686468 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 31 Jul 2025 06:57:15 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 31 Jul 2025 06:57:14 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 31 Jul 2025 06:57:14 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 56VBudQP2861468; Thu, 31 Jul 2025 06:57:11 -0500 From: Akashdeep Kaur To: , , , , , , , , , , CC: , Subject: [PATCH 1/3] arm64: dts: ti: k3-am62p5-sk: Remove the unused config from USB1_DRVVBUS Date: Thu, 31 Jul 2025 17:26:29 +0530 Message-ID: <20250731115631.3263798-2-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250731115631.3263798-1-a-kaur@ti.com> References: <20250731115631.3263798-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the Deep Sleep mode. For that, either deep Sleep pullup can be selected or the pin can have the same configuration that it had when SoC was in active mode. In order for deep sleep configuration to take effect, the deep sleep control bit has to be enabled. Remove the deep sleep state configuration from USB1_DRVBUS pin as it is anyways not taking effect (deep sleep control bit is not set). This reverts commit 115290c112952db27009668aa7ae2f29920704f0. Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 899da7896563..e8f0ac2c55e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -360,7 +360,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACL= KR.UART1_TXD */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1