From nobody Sun Oct 5 18:21:50 2025 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9BEE28030E for ; Thu, 31 Jul 2025 23:19:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754003969; cv=none; b=oWiTQ+KovgPCxD7A6LwQKJKHmM1TGqZNPOmRTX5YNQ09o6a5KGQ+xV4xExDctIaff139AXSKaUFmu/7STkQa2JO2bcwWhBH3UKspOuGzIuE2myD33U2T5+tODPR1WQH3FVlQ4A220/WAxmFo8EDUEEmQnq0rlrK4wN8cJy0SXyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754003969; c=relaxed/simple; bh=7li879NG60DMvoItDtTrx3PfjzLR4bOnwC03MvXTnvw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N/B22xsZZIKuz10AzFqnMUgotJ7pf2nldTbAf9gH2Abka+/+PyMTLVINs8vQK68bgXzczvhXjsizur5K3IffMp98jzqQR7I7hF6d0nEFIubWEN+obyNz6piEcjhBvkZwL2nO0mzgH/aevu5mwtz69JxnmjHgRLpRmCVXrl3Hw78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=v0Pozl2b; arc=none smtp.client-ip=209.85.210.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="v0Pozl2b" Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-76bdea88e12so10366b3a.0 for ; Thu, 31 Jul 2025 16:19:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1754003967; x=1754608767; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=R/zH7pR/lYDXTCsVz0jr8PjmlJlgvFu5fq+fqB2fhJ8=; b=v0Pozl2bi5KvMT4Yn8/7sLgvcQM96NT0NXz/2ri71B6545qi2LbDhCU/5JFzVmoaWi oHUhQb76ozVZ40bukOBDi7rdWToQ8RR60wp0DO9HH+ZmyIAEXm8GjBP3xb72kzXtKs+F 1a65Y3fYnWOHMs5xMvCkMjlULc5g4ciLUGMalk0NbxrISh9phUlOOylLQmwswBvX2fcG S3Csa+DzQ9acJ3HB0eoH1OJ6DBg857rr0Ao6F8RtvshaCOhxrvbJ5AVEGVz8yzst23xF m1Uq+d7aJEliJFbGyUIIwNja4CkzYNXkVeNRPOTMwAsBtMR0iuogGy3HSZXeGB05WSfM 8kCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754003967; x=1754608767; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R/zH7pR/lYDXTCsVz0jr8PjmlJlgvFu5fq+fqB2fhJ8=; b=fRWjzvmApEq29Bw57+5X07k6m/Z0yQWNP63AdOnhRguMFvO4bWQJ2BgSYVqcrst7GY ApxL/1hqNXQg055NlzQn+66W3OVuLnCU56BcYnDKODQkIHFRI0XnF9jjGcPEGkD5COqG +WJ0dF1wx8InJPqJV3tETR0DWv+Hp4ngjc606qRO8nbnWf15HLraq+8ltgmeeAVsx1mb JB9gxZ2ZMppOujPGSNnIrLB/sDeOx6eOfU5KKqzr2HWQtj1LCvbjzvxLbD/LE93cQkRi TR0JO6r1R85jCANqTs666+UoyxS3M8r5OO1MgRAMsW30uW55HfVRKo+qMoJqUuTUwLt+ w87Q== X-Gm-Message-State: AOJu0YxUv3lIWnuWXOhh9txCMH3vvR9Ti1SpBT3Fw4yJ6SCjmOENe6/x NJBbiupzL+jto/QaYNur7EA/nXTLB7rg1azUkirBVb5Hw+44yqh5auSk7rek/0Zr8BQ= X-Gm-Gg: ASbGncudq79SVVnBl2xHQRAOHwcPSFfpX5D5+hMSzZEqeag0P7OKeDZ/fdeQ0mwEpw0 wpXLkFO3AUKGP36asoSOqp7QKq+19IXHMxc8EBIHRD45ljFHVCaZ2grE1Z2We3B6aDoA7FAkCpd h9np8qBvyfXzmwLQXiYYDMRi+kkm4pLhR8KelnUUEP4j9oFmAXn9ggw36pQ86EII2kBBw6ptc7f Nt1wqHGtiPErJxONiJpM8f1754UuqdbRNfVA11pWFgKqyjk2RxujDhlowBLfsrG6dtfaLfF6HXW TPZWWZUBNyu03xstgvPmkPcr+veX5YEskBt++gUoqz8APvRUrq0pBBe9UItQQ1xe9gPIjBUI3dU uvne5J3VY7ALZByECdHYj07O9/zTwPAd5IR88RzI6OOo= X-Google-Smtp-Source: AGHT+IGYtHbkIIYCjaK0pApil9XPoWC3HM910LxxJmFY6X3GTvEXVCJzuEQBTa4Y+eDTOHWGTwIO1w== X-Received: by 2002:a17:902:ce05:b0:240:7753:3c22 with SMTP id d9443c01a7336-24096ae530dmr117950085ad.33.1754003967144; Thu, 31 Jul 2025 16:19:27 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31f63da8fcfsm5773085a91.7.2025.07.31.16.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 16:19:26 -0700 (PDT) From: Deepak Gupta Date: Thu, 31 Jul 2025 16:19:13 -0700 Subject: [PATCH v19 03/27] riscv: zicfiss / zicfilp enumeration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-v5_user_cfi_series-v19-3-09b468d7beab@rivosinc.com> References: <20250731-v5_user_cfi_series-v19-0-09b468d7beab@rivosinc.com> In-Reply-To: <20250731-v5_user_cfi_series-v19-0-09b468d7beab@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Benno Lossin Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp stands for unprivleged integer spec extension for shadow stack and branch tracking on indirect branches, respectively. This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights up bit in cpu feature bitmap. Furthermore this patch adds detection utility functions to return whether shadow stack or landing pads are supported by cpu. Reviewed-by: Zong Li Reviewed-by: Alexandre Ghiti Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/cpufeature.h | 12 ++++++++++++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 22 ++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 9430dc198caa..c5c01efba3e7 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -156,4 +156,16 @@ static __always_inline bool riscv_cpu_has_extension_un= likely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } =20 +static inline bool cpu_supports_shadow_stack(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFISS)); +} + +static inline bool cpu_supports_indirect_br_lp_instr(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFILP)); +} + #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index affd63e11b0a..7c4619a6d70d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -106,6 +106,8 @@ #define RISCV_ISA_EXT_ZAAMO 97 #define RISCV_ISA_EXT_ZALRSC 98 #define RISCV_ISA_EXT_ZICBOP 99 +#define RISCV_ISA_EXT_ZICFILP 100 +#define RISCV_ISA_EXT_ZICFISS 101 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 743d53415572..d38136672650 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -274,6 +274,24 @@ static int riscv_ext_svadu_validate(const struct riscv= _isa_ext_data *data, return 0; } =20 +static int riscv_cfilp_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) + return -EINVAL; + + return 0; +} + +static int riscv_cfiss_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) + return -EINVAL; + + return 0; +} + static const unsigned int riscv_a_exts[] =3D { RISCV_ISA_EXT_ZAAMO, RISCV_ISA_EXT_ZALRSC, @@ -461,6 +479,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zic= bop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_x= linuxenvcfg_exts, + riscv_cfilp_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_x= linuxenvcfg_exts, + riscv_cfiss_validate), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), --=20 2.43.0