From nobody Sun Oct 5 18:19:56 2025 Received: from srv01.abscue.de (abscue.de [89.58.28.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBF921714C6; Thu, 31 Jul 2025 15:53:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.28.240 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753977188; cv=none; b=GVs41/KNqGIgTvlbnL7qqB7Q3V6RvDilzU8NRagyiRjdqMHOh4CInzh1fPDXugZCAD1eNskkdqDKXC5+RHfRTVXWSd+P0M1hc6eXgdje57/TW5iowOKqKAx1YppzEEj6sWvLWNBvEUH3VLB6pcNFpmvTKoQYm7t4m1hHridEUeM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753977188; c=relaxed/simple; bh=g0G7XYNv76Ui/n2QbdZ3v+0NlnsKXvm8GwhIBAxnAB4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mVNMDZw17fDPX3jmUL+VXsgGCnSlGJSlhvQ5UgW//BoO+jd4oARDh/gCqTxohxUZ6IQWQQBuxVUYaXPaw/l+Fo6Yt+fDhI4sVN8c1iGjS1qJKMx6Kms0Ovbfvjx+7XkKd9JB0ICsLXkVWxKEasYjzkPCv5XytsvTQS789LDu2ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de; spf=pass smtp.mailfrom=abscue.de; arc=none smtp.client-ip=89.58.28.240 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=abscue.de Received: from srv01.abscue.de (localhost [127.0.0.1]) by spamfilter.srv.local (Postfix) with ESMTP id 45CB71C26E9; Thu, 31 Jul 2025 17:52:57 +0200 (CEST) X-Spam-Level: Received: from fluffy-mammal.metal.fwg-cag.de (unknown [IPv6:2001:9e8:cdc9:0:1347:874c:9851:58c6]) by srv01.abscue.de (Postfix) with ESMTPSA id 93AB61C2712; Thu, 31 Jul 2025 17:52:56 +0200 (CEST) From: =?utf-8?q?Otto_Pfl=C3=BCger?= Date: Thu, 31 Jul 2025 17:51:22 +0200 Subject: [PATCH v3 09/16] drm: sprd: fix DSI rate and PLL setup code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-ums9230-drm-v3-9-06d4f57c4b08@abscue.de> References: <20250731-ums9230-drm-v3-0-06d4f57c4b08@abscue.de> In-Reply-To: <20250731-ums9230-drm-v3-0-06d4f57c4b08@abscue.de> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Kevin Tang , Liviu Dudau , Russell King , Eric Anholt , Kevin Tang Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 Correct the initialization code to treat the hs_rate and lp_rate values as hertz instead of kilohertz. While at it, fix a bit operation bug in the PLL initialization code which caused a PLL register to be set to zero instead of the desired value. Fixes: 1c66496b1391 ("drm/sprd: add Unisoc's drm mipi dsi&dphy driver") Signed-off-by: Otto Pfl=C3=BCger --- drivers/gpu/drm/sprd/megacores_pll.c | 7 +++---- drivers/gpu/drm/sprd/sprd_dsi.c | 7 +++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/sprd/megacores_pll.c b/drivers/gpu/drm/sprd/me= gacores_pll.c index e5a18599678ab6e3771cd732dcca409ab2d59f72..f214f906b58fb006c4305de9b8b= 86b4a934f2074 100644 --- a/drivers/gpu/drm/sprd/megacores_pll.c +++ b/drivers/gpu/drm/sprd/megacores_pll.c @@ -23,13 +23,12 @@ =20 static int dphy_calc_pll_param(struct dphy_pll *pll) { - const u32 khz =3D 1000; const u32 mhz =3D 1000000; const unsigned long long factor =3D 100; unsigned long long tmp; int i; =20 - pll->potential_fvco =3D pll->freq / khz; + pll->potential_fvco =3D pll->freq / mhz; =20 for (i =3D 0; i < 4; ++i) { if (pll->potential_fvco >=3D pll->platform->band_low && @@ -89,7 +88,7 @@ static void dphy_set_pll_reg(struct dphy_pll *pll, struct= regmap *regmap) reg_val[3] =3D pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2); reg_val[4] =3D pll->kint >> 12; reg_val[5] =3D pll->kint >> 4; - reg_val[6] =3D pll->out_sel | ((pll->kint << 4) & 0xf); + reg_val[6] =3D pll->out_sel | ((pll->kint & 0xf) << 4); reg_val[7] =3D 1 << 4; reg_val[8] =3D pll->det_delay; =20 @@ -218,7 +217,7 @@ void dphy_timing_config(struct dsi_context *ctx) u32 tmp =3D 0; =20 /* t_ui: 1 ui, byteck: 8 ui, half byteck: 4 ui */ - t_ui =3D 1000 * scale / (pll->freq / 1000); + t_ui =3D 1000 * scale / (pll->freq / 1000000); t_byteck =3D t_ui << 3; t_half_byteck =3D t_ui << 2; constant =3D t_ui << 1; diff --git a/drivers/gpu/drm/sprd/sprd_dsi.c b/drivers/gpu/drm/sprd/sprd_ds= i.c index 106a0e7dac5cb89e6a96cc33a1698ec48c9f2745..071313b605447525326f6b869bc= 09991d4fcd691 100644 --- a/drivers/gpu/drm/sprd/sprd_dsi.c +++ b/drivers/gpu/drm/sprd/sprd_dsi.c @@ -390,7 +390,7 @@ static u32 fmt_to_coding(u32 fmt) static void sprd_dsi_init(struct dsi_context *ctx) { struct sprd_dsi *dsi =3D container_of(ctx, struct sprd_dsi, ctx); - u32 byte_clk =3D dsi->slave->hs_rate / 8; + u32 byte_clk =3D dsi->slave->hs_rate / 8000; u16 data_hs2lp, data_lp2hs, clk_hs2lp, clk_lp2hs; u16 max_rd_time; int div; @@ -407,7 +407,7 @@ static void sprd_dsi_init(struct dsi_context *ctx) dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, VIDEO_PKT_VCID, 0); dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, GEN_RX_VCID, 0); =20 - div =3D DIV_ROUND_UP(byte_clk, dsi->slave->lp_rate); + div =3D DIV_ROUND_UP(byte_clk, dsi->slave->lp_rate / 1000); writel(div, ctx->base + TX_ESC_CLK_CONFIG); =20 max_rd_time =3D ns_to_cycle(ctx->max_rd_time, byte_clk); @@ -449,7 +449,6 @@ static int sprd_dsi_dpi_video(struct dsi_context *ctx) { struct sprd_dsi *dsi =3D container_of(ctx, struct sprd_dsi, ctx); struct videomode *vm =3D &ctx->vm; - u32 byte_clk =3D dsi->slave->hs_rate / 8; u16 bpp_x100; u16 video_size; u32 ratio_x1000; @@ -471,7 +470,7 @@ static int sprd_dsi_dpi_video(struct dsi_context *ctx) video_size =3D round_video_size(coding, vm->hactive); bpp_x100 =3D calc_bytes_per_pixel_x100(coding); video_size_step =3D calc_video_size_step(coding); - ratio_x1000 =3D byte_clk * 1000 / (vm->pixelclock / 1000); + ratio_x1000 =3D dsi->slave->hs_rate / 8 / (vm->pixelclock / 1000); hline =3D vm->hactive + vm->hsync_len + vm->hfront_porch + vm->hback_porch; =20 --=20 2.50.0