From nobody Sun Oct 5 18:19:56 2025 Received: from srv01.abscue.de (abscue.de [89.58.28.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96FDF1DF991; Thu, 31 Jul 2025 15:53:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.28.240 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753977188; cv=none; b=XLuRJF1q+jKU+SZhQ6zrBFfZou6PCkIuSw76pyffadjnLPWJoIXOiymeRQz7ydB5qLc9KiVa6pbi66zhREwH06vCPQCwe9DbxIegL41s1YSpnVMHqpMFNAqzZofV17vKn6adXnZfSlIvAk1kiO4EwBb5PjTLVD6+V0sJ+sTTbYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753977188; c=relaxed/simple; bh=K8BHA+iA1iydveDUvp/YesIVTsMaDiSb18vKNRsmk48=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e4pyn4H+y2FF/3VJjpG3lZB/gqx/5wlCy0muYuDUiEAAp+/YVgtap24n7yWNJOYyYgRakLcjyJkRWYHDVDzEAYK/xmT6Fv/Xh4itDewNpbvwdcfnUUZj5KQAsCUz/Lmu1X7VLjYbVgiIfIQFEkUTolnAmq07xpDuY2FXNt9GEX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de; spf=pass smtp.mailfrom=abscue.de; arc=none smtp.client-ip=89.58.28.240 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=abscue.de Received: from srv01.abscue.de (localhost [127.0.0.1]) by spamfilter.srv.local (Postfix) with ESMTP id 0F55C1C271E; Thu, 31 Jul 2025 17:52:59 +0200 (CEST) X-Spam-Level: Received: from fluffy-mammal.metal.fwg-cag.de (unknown [IPv6:2001:9e8:cdc9:0:1347:874c:9851:58c6]) by srv01.abscue.de (Postfix) with ESMTPSA id CA3B71C270C; Thu, 31 Jul 2025 17:52:55 +0200 (CEST) From: =?utf-8?q?Otto_Pfl=C3=BCger?= Date: Thu, 31 Jul 2025 17:51:21 +0200 Subject: [PATCH v3 08/16] drm: sprd: add support for UMS9230 DSI PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-ums9230-drm-v3-8-06d4f57c4b08@abscue.de> References: <20250731-ums9230-drm-v3-0-06d4f57c4b08@abscue.de> In-Reply-To: <20250731-ums9230-drm-v3-0-06d4f57c4b08@abscue.de> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Kevin Tang , Liviu Dudau , Russell King , Eric Anholt , Kevin Tang Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 Move platform-specific PLL parameters to the device tree match data and add the parameters for UMS9230. Signed-off-by: Otto Pfl=C3=BCger --- drivers/gpu/drm/sprd/megacores_pll.c | 21 ++++++++------------- drivers/gpu/drm/sprd/sprd_dsi.c | 21 ++++++++++++++++++++- drivers/gpu/drm/sprd/sprd_dsi.h | 9 ++++++++- 3 files changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/sprd/megacores_pll.c b/drivers/gpu/drm/sprd/me= gacores_pll.c index 3091dfdc11e3b547a05a9edaa4047a1e367c1596..e5a18599678ab6e3771cd732dcc= a409ab2d59f72 100644 --- a/drivers/gpu/drm/sprd/megacores_pll.c +++ b/drivers/gpu/drm/sprd/megacores_pll.c @@ -21,12 +21,6 @@ =20 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2) =20 -/* sharkle */ -#define VCO_BAND_LOW 750 -#define VCO_BAND_MID 1100 -#define VCO_BAND_HIGH 1500 -#define PHY_REF_CLK 26000 - static int dphy_calc_pll_param(struct dphy_pll *pll) { const u32 khz =3D 1000; @@ -36,11 +30,10 @@ static int dphy_calc_pll_param(struct dphy_pll *pll) int i; =20 pll->potential_fvco =3D pll->freq / khz; - pll->ref_clk =3D PHY_REF_CLK / khz; =20 for (i =3D 0; i < 4; ++i) { - if (pll->potential_fvco >=3D VCO_BAND_LOW && - pll->potential_fvco <=3D VCO_BAND_HIGH) { + if (pll->potential_fvco >=3D pll->platform->band_low && + pll->potential_fvco <=3D pll->platform->band_high) { pll->fvco =3D pll->potential_fvco; pll->out_sel =3D BIT(i); break; @@ -50,21 +43,23 @@ static int dphy_calc_pll_param(struct dphy_pll *pll) if (pll->fvco =3D=3D 0) return -EINVAL; =20 - if (pll->fvco >=3D VCO_BAND_LOW && pll->fvco <=3D VCO_BAND_MID) { + if (pll->fvco >=3D pll->platform->band_low && + pll->fvco <=3D pll->platform->band_mid) { /* vco band control */ pll->vco_band =3D 0x0; /* low pass filter control */ pll->lpf_sel =3D 1; - } else if (pll->fvco > VCO_BAND_MID && pll->fvco <=3D VCO_BAND_HIGH) { + } else if (pll->fvco > pll->platform->band_mid && + pll->fvco <=3D pll->platform->band_high) { pll->vco_band =3D 0x1; pll->lpf_sel =3D 0; } else { return -EINVAL; } =20 - pll->nint =3D pll->fvco / pll->ref_clk; + pll->nint =3D pll->fvco / pll->platform->ref_clk; tmp =3D pll->fvco * factor * mhz; - do_div(tmp, pll->ref_clk); + do_div(tmp, pll->platform->ref_clk); tmp =3D tmp - pll->nint * factor * mhz; tmp *=3D BIT(20); do_div(tmp, 100000000); diff --git a/drivers/gpu/drm/sprd/sprd_dsi.c b/drivers/gpu/drm/sprd/sprd_ds= i.c index 22f300654a1903ecb7002c1e643361c6c51623d4..106a0e7dac5cb89e6a96cc33a16= 98ec48c9f2745 100644 --- a/drivers/gpu/drm/sprd/sprd_dsi.c +++ b/drivers/gpu/drm/sprd/sprd_dsi.c @@ -1071,8 +1071,23 @@ static const struct mipi_dsi_host_ops sprd_dsi_host_= ops =3D { .transfer =3D sprd_dsi_host_transfer, }; =20 +static const struct dphy_pll_platform dphy_pll_sharkl3 =3D { + .band_low =3D 750, + .band_mid =3D 1100, + .band_high =3D 1500, + .ref_clk =3D 26, +}; + +static const struct dphy_pll_platform dphy_pll_ums9230 =3D { + .band_low =3D 1250, + .band_mid =3D 1800, + .band_high =3D 2500, + .ref_clk =3D 26, +}; + static const struct of_device_id dsi_match_table[] =3D { - { .compatible =3D "sprd,sharkl3-dsi-host" }, + { .compatible =3D "sprd,sharkl3-dsi-host", .data =3D &dphy_pll_sharkl3 }, + { .compatible =3D "sprd,ums9230-dsi-host", .data =3D &dphy_pll_ums9230 }, { /* sentinel */ }, }; =20 @@ -1091,6 +1106,10 @@ static int sprd_dsi_probe(struct platform_device *pd= ev) dsi->host.ops =3D &sprd_dsi_host_ops; dsi->host.dev =3D dev; =20 + dsi->ctx.pll.platform =3D of_device_get_match_data(dev); + if (!dsi->ctx.pll.platform) + return -EINVAL; + return mipi_dsi_host_register(&dsi->host); } =20 diff --git a/drivers/gpu/drm/sprd/sprd_dsi.h b/drivers/gpu/drm/sprd/sprd_ds= i.h index d15b8bfd61f2e69f877aa727fbbbe4b61e9cb0fe..1aa609b1da33601217941390673= 553552f2923b1 100644 --- a/drivers/gpu/drm/sprd/sprd_dsi.h +++ b/drivers/gpu/drm/sprd/sprd_dsi.h @@ -64,6 +64,13 @@ enum pll_timing { TA_WAIT, }; =20 +struct dphy_pll_platform { + u32 band_low; + u32 band_mid; + u32 band_high; + u32 ref_clk; /* dphy reference clock, unit: MHz */ +}; + struct dphy_pll { u8 refin; /* Pre-divider control signal */ u8 cp_s; /* 00: SDM_EN=3D1, 10: SDM_EN=3D0 */ @@ -71,7 +78,6 @@ struct dphy_pll { u8 sdm_en; u8 div; u8 int_n; /* integer N PLL */ - u32 ref_clk; /* dphy reference clock, unit: MHz */ u32 freq; /* panel config, unit: KHz */ u32 fvco; u32 potential_fvco; @@ -81,6 +87,7 @@ struct dphy_pll { u8 out_sel; /* post divider control */ u8 vco_band; /* vco range */ u8 det_delay; + const struct dphy_pll_platform *platform; }; =20 struct dsi_context { --=20 2.50.0