From nobody Sun Oct 5 18:19:55 2025 Received: from srv01.abscue.de (abscue.de [89.58.28.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3539C1E32D7; Thu, 31 Jul 2025 15:53:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.28.240 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753977189; cv=none; b=FlpS60Bpp134F5GFSWZAgd3lgm83jIr9yK1XQQGYRYyaCUoDIyTgrOV12RuXELgZX6c3fKCXssPda/FJPESqYx6r5gHNX9swhFnH56l1PYvSXApg+FLjbFgPpp727S35DmpWnUgJEbZg3Ohnjz+msnCgwYSuB+qBSuEA+ECysks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753977189; c=relaxed/simple; bh=4bxQLOtRkyl6SeRQbTil/FKNSHg0sfy6UDXeqn90ijA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LRmDmHYxBwRft+P5dUS+wh7t+hcSxWBqxNfzJvPh9V5IORhcGfufJfx1lBawnpTa0x/p6aEWo62M7SS8XKYpy29LQ1W1V8+XmHuxQG/HubP/YZ4Yqhtw1WKFxmHpJpU7ISvGyb2H2RuSdtHP+BDjHrI6AU9hITCM95qv/HOlRao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de; spf=pass smtp.mailfrom=abscue.de; arc=none smtp.client-ip=89.58.28.240 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=abscue.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=abscue.de Received: from srv01.abscue.de (localhost [127.0.0.1]) by spamfilter.srv.local (Postfix) with ESMTP id 710FD1C2727; Thu, 31 Jul 2025 17:52:59 +0200 (CEST) X-Spam-Level: Received: from fluffy-mammal.metal.fwg-cag.de (unknown [IPv6:2001:9e8:cdc9:0:1347:874c:9851:58c6]) by srv01.abscue.de (Postfix) with ESMTPSA id BFFE11C2715; Thu, 31 Jul 2025 17:52:58 +0200 (CEST) From: =?utf-8?q?Otto_Pfl=C3=BCger?= Date: Thu, 31 Jul 2025 17:51:25 +0200 Subject: [PATCH v3 12/16] drm: sprd: add support for newer DPU versions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-ums9230-drm-v3-12-06d4f57c4b08@abscue.de> References: <20250731-ums9230-drm-v3-0-06d4f57c4b08@abscue.de> In-Reply-To: <20250731-ums9230-drm-v3-0-06d4f57c4b08@abscue.de> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Kevin Tang , Liviu Dudau , Russell King , Eric Anholt , Kevin Tang Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 Newer DPU revisions with the same register layout, such as the one used in UMS9230 (version 5), require different defaults for the display interface configuration but otherwise remain compatible with the version this driver was originally written for. Check the DPU version register to account for these configuration differences. Signed-off-by: Otto Pfl=C3=BCger --- drivers/gpu/drm/sprd/sprd_dpu.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dp= u.c index 9d274600e6a80bdfc435f6c6eff77c9dd71cb38c..978d4947e1bc5cd5b13b1f25719= 268fa08b77297 100644 --- a/drivers/gpu/drm/sprd/sprd_dpu.c +++ b/drivers/gpu/drm/sprd/sprd_dpu.c @@ -27,6 +27,7 @@ #include "sprd_dsi.h" =20 /* Global control registers */ +#define REG_DPU_VERSION 0x00 #define REG_DPU_CTRL 0x04 #define REG_DPU_CFG0 0x08 #define REG_PANEL_SIZE 0x20 @@ -406,6 +407,7 @@ static void sprd_dpu_init(struct sprd_dpu *dpu) { struct dpu_context *ctx =3D &dpu->ctx; u32 int_mask =3D 0; + u32 dpu_version =3D readl(ctx->base + REG_DPU_VERSION); =20 writel(0x00, ctx->base + REG_BG_COLOR); writel(0x00, ctx->base + REG_MMU_EN); @@ -418,10 +420,16 @@ static void sprd_dpu_init(struct sprd_dpu *dpu) if (ctx->if_type =3D=3D SPRD_DPU_IF_DPI) { /* use dpi as interface */ dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI); - /* disable Halt function for SPRD DSI */ - dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN); - /* select te from external pad */ - dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD); + + if (dpu_version < 0x300) { + /* disable Halt function for SPRD DSI */ + dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN); + /* select te from external pad */ + dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD); + } else { + /* enable Halt function for SPRD DSI */ + dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN); + } =20 /* enable dpu update done INT */ int_mask |=3D BIT_DPU_INT_UPDATE_DONE; --=20 2.50.0