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Thu, 31 Jul 2025 00:16:05 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 31 Jul 2025 09:15:54 +0200 Subject: [PATCH v2 3/3] dt-bindings: ufs: qcom: Split SM8650 and similar Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-dt-bindings-ufs-qcom-v2-3-53bb634bf95a@linaro.org> References: <20250731-dt-bindings-ufs-qcom-v2-0-53bb634bf95a@linaro.org> In-Reply-To: <20250731-dt-bindings-ufs-qcom-v2-0-53bb634bf95a@linaro.org> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Kumar Dwivedi , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8603; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=m4Q58xqf9/x4E0jlUz4rpnXUwO4kR+noNYCXUYqKHk0=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoixgvSf90OB3oyLSCdRTgI1O1KtbPcZh2rWUMe uiBfXwVx46JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaIsYLwAKCRDBN2bmhouD 16xjD/9hofBF29vglaxv/+fCMf1vugvzZliqr08i1pEj8x1+VTFwn/QEQWNiPDQO2+TxTMr0uOJ xMAsZExfNQtyABjS3jGytOBAAT7M6CTfhdb73dn8cMLV4pr/64208LFlveU+00imNXkXKiYapMn YmaC6RA5gfy3bWkkNNkz3Ytzq/hNjBaOcvHR+RNjebdjOT7oZLa6qOsHAgCTzIHIp6vrLTCmTYA hGqlIGyHGqUe+ExLf2oYUCs/lYespdCI5S1dKCNfaDW2mYujqlLnxiETcRuFXH8OxQ96KT+4d8e OvAPSiQdLLKjx83rMU7Klv4b9mpvCDrJmdX+Y2liug2OlrxI3hIr1UhXCTOmcc946CJsYXAzwTs kcWUSyp2c/8DpUTzZhm7qHDOo3G64nz673r8NudR27oWryrbzYnyA1ox7B46+73HvAu9AFRGP+v fcla15kkOjt3BvTwe2koSN7ndTWPOKVFFmLxpFANvcqQXiAr7oieKH7Tcexz05LF+hjlcWTSDpm d/pjwWN9UPasnuzGq0vRiVJx7wwM767IHrgCEn0OxJtRE82JbDTQA7OSz7LniCtYqI/BWrarwzU rjGQkdsUwSO+vjxcWcLbVmRRa64pwz9Il868JHCcs3+2fFI+SxssOoX6XKVSZz+5EidDgWzK3CM VdMAXh2tLjtRdsw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The binding for Qualcomm SoC UFS controllers grew and it will grow further. Split SM8650 and SM8750 UFS controllers which: 1. Do not reference ICE as IO address space, but as phandle, 2. Have same order of clocks. 3. Have MCQ IO address space. Document that MCQ address space as optional to maintain backwards compatibility and because Linux drivers can operate perfectly fine without it (thus without MCQ feature). Linux driver already uses "mcq" as possible name for "reg-names" property. The split allows easier review and maintenance of the binding. Signed-off-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 +++++++++++++++++= ++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 32 ---- 2 files changed, 178 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml b= /Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..aaa0bbb5bfe1673e3e0d25812c2= 829350b137abb --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 and Other SoCs UFS Controllers + +maintainers: + - Bjorn Andersson + +# Select only our matches, not all jedec,ufs-2.0 +select: + properties: + compatible: + contains: + enum: + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + - const: qcom,ufshc + - const: jedec,ufs-2.0 + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: std + - const: mcq + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: rx_lane1_sync_clk + + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Inline Crypto Engine node + +required: + - compatible + - reg + +allOf: + - $ref: qcom,ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + ufshc@1d84000 { + compatible =3D "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2= .0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALW= AYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIV= E_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_AC= TIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + operating-points-v2 =3D <&ufs_opp_table>; + + iommus =3D <&apps_smmu 0x60 0>; + + lanes-per-direction =3D <2>; + qcom,ice =3D <&ice>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + vcc-supply =3D <&vreg_l7b_2p5>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l9b_1p2>; + vccq-max-microamp =3D <1200000>; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz =3D /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index 191b88120d139a47632e3dce3d3f3a37d7a55c72..1dd41f6d5258014d59c8c8005bc= 54f7994351a52 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -24,8 +24,6 @@ select: - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc required: - compatible =20 @@ -41,8 +39,6 @@ properties: - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 =20 @@ -66,34 +62,6 @@ required: allOf: - $ref: qcom,ufs-common.yaml =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: core_clk - - const: bus_aggr_clk - - const: iface_clk - - const: core_clk_unipro - - const: ref_clk - - const: tx_lane0_sync_clk - - const: rx_lane0_sync_clk - - const: rx_lane1_sync_clk - reg: - minItems: 1 - maxItems: 1 - reg-names: - maxItems: 1 - - if: properties: compatible: --=20 2.48.1