From nobody Sun Oct 5 16:18:16 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6194328DB73 for ; Thu, 31 Jul 2025 13:50:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969828; cv=none; b=C7RAZz4Fr3HNuDzmtL3tkc9ZABUw9IUND0uz7J/6y9KcL3YF+T1fN1yc2OeE2Q9wFD32jdWLh8lFgjhwemOQU6eQXktmAGDYnlvyQQgx35d/sb8yTy4Tk286SyltD9mfs8Bc8WhdoAQGfEK4YdeXFK+UaEU3DBZY59hxAumqosM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969828; c=relaxed/simple; bh=naB5TXIloBsYYk0fC6SVqC5HEO6bji2jghzaTdAJF8g=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=A3Pt/xwJLF1XWvwCXCksTupyyRLxZQ1b3swn31ofMuJLKiBCz2JAxsTSv0adCQKGCfDBDjmA2acNjdLj/7eYS1791vcU6X87I2FnGhoVDCmk6ihcaPCcgcod/9uOGCfaaXnyfcuXe7C99OnV9nDYldiVYDVkBth4cx3dpqquZHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=SKlCLIlg; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="SKlCLIlg" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250731135019euoutp024bd49240c8d42efb7e362d3c4d0dbf04~XWkHzGKAC1416114161euoutp02O for ; Thu, 31 Jul 2025 13:50:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250731135019euoutp024bd49240c8d42efb7e362d3c4d0dbf04~XWkHzGKAC1416114161euoutp02O DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1753969819; bh=13CbFbRowhmFlbOcL4SBnR0PIDJYNoScTnm59i8nQ4I=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=SKlCLIlgRVkmk9/grS+bIVse7FK00P3q2INYOHepAYt91csDPaMJIuwEy3Sdw65JP RzvQ2LCqmxHc797w7xsO2hyEvUqsug+HKOMlhynf9bCFeVzFAlq5pM5eG3Un1AUvfr m8rN2KwCdLT83pIm0oAI0srFW0yC1Hzt8se6QBNE= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250731135018eucas1p173c5f4a902409cfc3058bc400c4d2b10~XWkG3RUio2363423634eucas1p1L; Thu, 31 Jul 2025 13:50:18 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250731135017eusmtip23f89456c7d0a35fecc1695a12ec06719~XWkF0t0QU2218122181eusmtip2W; Thu, 31 Jul 2025 13:50:17 +0000 (GMT) From: Michal Wilczynski Date: Thu, 31 Jul 2025 15:50:11 +0200 Subject: [PATCH v9 1/5] drm/imagination: Use pwrseq for TH1520 GPU power management Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-apr_14_for_sending-v9-1-c242dc1ffc14@samsung.com> In-Reply-To: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250731135018eucas1p173c5f4a902409cfc3058bc400c4d2b10 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250731135018eucas1p173c5f4a902409cfc3058bc400c4d2b10 X-EPHeader: CA X-CMS-RootMailID: 20250731135018eucas1p173c5f4a902409cfc3058bc400c4d2b10 References: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> Update the Imagination PVR DRM driver to leverage the pwrseq framework for managing the complex power sequence of the GPU on the T-HEAD TH1520 SoC. To cleanly separate platform-specific logic from the generic driver, this patch introduces an `init` callback to the `pwr_power_sequence_ops` struct. This allows for different power management strategies to be selected at probe time based on the device's compatible string. A `pvr_device_data` struct, associated with each compatible in the of_device_id table, points to the appropriate ops table (manual or pwrseq). At probe time, the driver now calls the `->init()` op. For pwrseq-based platforms, this callback calls `devm_pwrseq_get("gpu-power")`, deferring probe if the sequencer is not yet available. For other platforms, it falls back to the existing manual clock and reset handling. The runtime PM callbacks continue to call the appropriate functions via the ops table. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/pvr_device.c | 22 +--- drivers/gpu/drm/imagination/pvr_device.h | 22 ++++ drivers/gpu/drm/imagination/pvr_drv.c | 27 ++++- drivers/gpu/drm/imagination/pvr_power.c | 174 ++++++++++++++++++++++++---= ---- drivers/gpu/drm/imagination/pvr_power.h | 19 +++- 5 files changed, 203 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 8b9ba4983c4cb5bc40342fcafc4259078bc70547..294b6019b4155bb7fdb7de73ccf= 7fa8ad867811f 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -121,21 +122,6 @@ static int pvr_device_clk_init(struct pvr_device *pvr_= dev) return 0; } =20 -static int pvr_device_reset_init(struct pvr_device *pvr_dev) -{ - struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); - struct reset_control *reset; - - reset =3D devm_reset_control_get_optional_exclusive(drm_dev->dev, NULL); - if (IS_ERR(reset)) - return dev_err_probe(drm_dev->dev, PTR_ERR(reset), - "failed to get gpu reset line\n"); - - pvr_dev->reset =3D reset; - - return 0; -} - /** * pvr_device_process_active_queues() - Process all queue related events. * @pvr_dev: PowerVR device to check @@ -618,6 +604,9 @@ pvr_device_init(struct pvr_device *pvr_dev) struct device *dev =3D drm_dev->dev; int err; =20 + /* Get the platform-specific data based on the compatible string. */ + pvr_dev->device_data =3D of_device_get_match_data(dev); + /* * Setup device parameters. We do this first in case other steps * depend on them. @@ -631,8 +620,7 @@ pvr_device_init(struct pvr_device *pvr_dev) if (err) return err; =20 - /* Get the reset line for the GPU */ - err =3D pvr_device_reset_init(pvr_dev); + err =3D pvr_dev->device_data->pwr_ops->init(pvr_dev); if (err) return err; =20 diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 7cb01c38d2a9c3fc71effe789d4dfe54eddd93ee..0c970255f90805a569d7d19e35e= c5f4ca7f02f7a 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -37,6 +37,9 @@ struct clk; /* Forward declaration from . */ struct firmware; =20 +/* Forward declaration from */ +struct pwrseq_desc; + /** * struct pvr_gpu_id - Hardware GPU ID information for a PowerVR device * @b: Branch ID. @@ -57,6 +60,14 @@ struct pvr_fw_version { u16 major, minor; }; =20 +/** + * struct pvr_device_data - Platform specific data associated with a compa= tible string. + * @pwr_ops: Pointer to a structure with platform-specific power functions. + */ +struct pvr_device_data { + const struct pvr_power_sequence_ops *pwr_ops; +}; + /** * struct pvr_device - powervr-specific wrapper for &struct drm_device */ @@ -98,6 +109,9 @@ struct pvr_device { /** @fw_version: Firmware version detected at runtime. */ struct pvr_fw_version fw_version; =20 + /** @device_data: Pointer to platform-specific data. */ + const struct pvr_device_data *device_data; + /** @regs_resource: Resource representing device control registers. */ struct resource *regs_resource; =20 @@ -148,6 +162,14 @@ struct pvr_device { */ struct reset_control *reset; =20 + /** + * @pwrseq: Pointer to a power sequencer, if one is used. + * + * Note: This member should only be accessed when + * IS_ENABLED(CONFIG_POWER_SEQUENCING) is true. + */ + struct pwrseq_desc *pwrseq; + /** @irq: IRQ number. */ int irq; =20 diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index b058ec183bb30ab5c3db17ebaadf2754520a2a1f..af830e565646daf19555197df49= 2438ef48d5e44 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1480,15 +1480,37 @@ static void pvr_remove(struct platform_device *plat= _dev) pvr_power_domains_fini(pvr_dev); } =20 +static const struct pvr_device_data pvr_device_data_manual =3D { + .pwr_ops =3D &pvr_power_sequence_ops_manual, +}; + +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) +static const struct pvr_device_data pvr_device_data_pwrseq =3D { + .pwr_ops =3D &pvr_power_sequence_ops_pwrseq, +}; +#endif + static const struct of_device_id dt_match[] =3D { - { .compatible =3D "img,img-rogue", .data =3D NULL }, +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) + { + .compatible =3D "thead,th1520-gpu", + .data =3D &pvr_device_data_pwrseq, + }, +#endif + { + .compatible =3D "img,img-rogue", + .data =3D &pvr_device_data_manual, + }, =20 /* * This legacy compatible string was introduced early on before the more = generic * "img,img-rogue" was added. Keep it around here for compatibility, but = never use * "img,img-axe" in new devicetrees. */ - { .compatible =3D "img,img-axe", .data =3D NULL }, + { + .compatible =3D "img,img-axe", + .data =3D &pvr_device_data_manual, + }, {} }; MODULE_DEVICE_TABLE(of, dt_match); @@ -1513,4 +1535,5 @@ MODULE_DESCRIPTION(PVR_DRIVER_DESC); MODULE_LICENSE("Dual MIT/GPL"); MODULE_IMPORT_NS("DMA_BUF"); MODULE_FIRMWARE("powervr/rogue_33.15.11.3_v1.fw"); +MODULE_FIRMWARE("powervr/rogue_36.52.104.182_v1.fw"); MODULE_FIRMWARE("powervr/rogue_36.53.104.796_v1.fw"); diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index 187a07e0bd9adb2f0713ac2c8e091229f4027354..58e0e812894de19c834e1dfca42= 7208b343eaa1c 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -18,6 +18,9 @@ #include #include #include +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) +#include +#endif #include #include #include @@ -234,6 +237,132 @@ pvr_watchdog_init(struct pvr_device *pvr_dev) return 0; } =20 +static int pvr_power_init_manual(struct pvr_device *pvr_dev) +{ + struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); + struct reset_control *reset; + + reset =3D devm_reset_control_get_optional_exclusive(drm_dev->dev, NULL); + if (IS_ERR(reset)) + return dev_err_probe(drm_dev->dev, PTR_ERR(reset), + "failed to get gpu reset line\n"); + + pvr_dev->reset =3D reset; + + return 0; +} + +static int pvr_power_on_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err =3D clk_prepare_enable(pvr_dev->core_clk); + if (err) + return err; + + err =3D clk_prepare_enable(pvr_dev->sys_clk); + if (err) + goto err_core_clk_disable; + + err =3D clk_prepare_enable(pvr_dev->mem_clk); + if (err) + goto err_sys_clk_disable; + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + err =3D reset_control_deassert(pvr_dev->reset); + if (err) + goto err_mem_clk_disable; + + return 0; + +err_mem_clk_disable: + clk_disable_unprepare(pvr_dev->mem_clk); + +err_sys_clk_disable: + clk_disable_unprepare(pvr_dev->sys_clk); + +err_core_clk_disable: + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + +static int pvr_power_off_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err =3D reset_control_assert(pvr_dev->reset); + + clk_disable_unprepare(pvr_dev->mem_clk); + clk_disable_unprepare(pvr_dev->sys_clk); + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + +const struct pvr_power_sequence_ops pvr_power_sequence_ops_manual =3D { + .init =3D pvr_power_init_manual, + .power_on =3D pvr_power_on_sequence_manual, + .power_off =3D pvr_power_off_sequence_manual, +}; + +#if IS_ENABLED(CONFIG_POWER_SEQUENCING) +static int pvr_power_init_pwrseq(struct pvr_device *pvr_dev) +{ + struct device *dev =3D from_pvr_device(pvr_dev)->dev; + + pvr_dev->pwrseq =3D devm_pwrseq_get(dev, "gpu-power"); + if (IS_ERR(pvr_dev->pwrseq)) { + /* + * This platform requires a sequencer. If we can't get it, we + * must return the error (including -EPROBE_DEFER to wait for + * the provider to appear) + */ + return dev_err_probe(dev, PTR_ERR(pvr_dev->pwrseq), + "Failed to get required power sequencer\n"); + } + + return 0; +} + +static int pvr_power_on_sequence_pwrseq(struct pvr_device *pvr_dev) +{ + return pwrseq_power_on(pvr_dev->pwrseq); +} + +static int pvr_power_off_sequence_pwrseq(struct pvr_device *pvr_dev) +{ + return pwrseq_power_off(pvr_dev->pwrseq); +} + +const struct pvr_power_sequence_ops pvr_power_sequence_ops_pwrseq =3D { + .init =3D pvr_power_init_pwrseq, + .power_on =3D pvr_power_on_sequence_pwrseq, + .power_off =3D pvr_power_off_sequence_pwrseq, +}; +#else /* IS_ENABLED(CONFIG_POWER_SEQUENCING) */ +static int pvr_power_sequence_stub(struct pvr_device *pvr_dev) +{ + WARN_ONCE(1, "pwrseq support not enabled in kernel config\n"); + return -EOPNOTSUPP; +} + +const struct pvr_power_sequence_ops pvr_power_sequence_ops_pwrseq =3D { + .init =3D pvr_power_sequence_stub, + .power_on =3D pvr_power_sequence_stub, + .power_off =3D pvr_power_sequence_stub, +}; +#endif /* IS_ENABLED(CONFIG_POWER_SEQUENCING) */ + int pvr_power_device_suspend(struct device *dev) { @@ -252,11 +381,7 @@ pvr_power_device_suspend(struct device *dev) goto err_drm_dev_exit; } =20 - clk_disable_unprepare(pvr_dev->mem_clk); - clk_disable_unprepare(pvr_dev->sys_clk); - clk_disable_unprepare(pvr_dev->core_clk); - - err =3D reset_control_assert(pvr_dev->reset); + err =3D pvr_dev->device_data->pwr_ops->power_off(pvr_dev); =20 err_drm_dev_exit: drm_dev_exit(idx); @@ -276,53 +401,22 @@ pvr_power_device_resume(struct device *dev) if (!drm_dev_enter(drm_dev, &idx)) return -EIO; =20 - err =3D clk_prepare_enable(pvr_dev->core_clk); + err =3D pvr_dev->device_data->pwr_ops->power_on(pvr_dev); if (err) goto err_drm_dev_exit; =20 - err =3D clk_prepare_enable(pvr_dev->sys_clk); - if (err) - goto err_core_clk_disable; - - err =3D clk_prepare_enable(pvr_dev->mem_clk); - if (err) - goto err_sys_clk_disable; - - /* - * According to the hardware manual, a delay of at least 32 clock - * cycles is required between de-asserting the clkgen reset and - * de-asserting the GPU reset. Assuming a worst-case scenario with - * a very high GPU clock frequency, a delay of 1 microsecond is - * sufficient to ensure this requirement is met across all - * feasible GPU clock speeds. - */ - udelay(1); - - err =3D reset_control_deassert(pvr_dev->reset); - if (err) - goto err_mem_clk_disable; - if (pvr_dev->fw_dev.booted) { err =3D pvr_power_fw_enable(pvr_dev); if (err) - goto err_reset_assert; + goto err_power_off; } =20 drm_dev_exit(idx); =20 return 0; =20 -err_reset_assert: - reset_control_assert(pvr_dev->reset); - -err_mem_clk_disable: - clk_disable_unprepare(pvr_dev->mem_clk); - -err_sys_clk_disable: - clk_disable_unprepare(pvr_dev->sys_clk); - -err_core_clk_disable: - clk_disable_unprepare(pvr_dev->core_clk); +err_power_off: + pvr_dev->device_data->pwr_ops->power_off(pvr_dev); =20 err_drm_dev_exit: drm_dev_exit(idx); diff --git a/drivers/gpu/drm/imagination/pvr_power.h b/drivers/gpu/drm/imag= ination/pvr_power.h index ada85674a7ca762dcf92df40424230e1c3910342..f7848f106fb97111a82a6727bb2= c860deb64fc56 100644 --- a/drivers/gpu/drm/imagination/pvr_power.h +++ b/drivers/gpu/drm/imagination/pvr_power.h @@ -4,11 +4,11 @@ #ifndef PVR_POWER_H #define PVR_POWER_H =20 -#include "pvr_device.h" - #include #include =20 +struct pvr_device; + int pvr_watchdog_init(struct pvr_device *pvr_dev); void pvr_watchdog_fini(struct pvr_device *pvr_dev); =20 @@ -41,4 +41,19 @@ pvr_power_put(struct pvr_device *pvr_dev) int pvr_power_domains_init(struct pvr_device *pvr_dev); void pvr_power_domains_fini(struct pvr_device *pvr_dev); =20 +/** + * struct pvr_power_sequence_ops - Platform specific power sequence operat= ions. + * @init: Pointer to the platform-specific initialization function. + * @power_on: Pointer to the platform-specific power on function. + * @power_off: Pointer to the platform-specific power off function. + */ +struct pvr_power_sequence_ops { + int (*init)(struct pvr_device *pvr_dev); + int (*power_on)(struct pvr_device *pvr_dev); + int (*power_off)(struct pvr_device *pvr_dev); +}; + +extern const struct pvr_power_sequence_ops pvr_power_sequence_ops_manual; +extern const struct pvr_power_sequence_ops pvr_power_sequence_ops_pwrseq; + #endif /* PVR_POWER_H */ --=20 2.34.1 From nobody Sun Oct 5 16:18:16 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87C6C239E84 for ; Thu, 31 Jul 2025 13:50:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969823; cv=none; b=dIRmyzahw8+UJaymr/qpOm/n7JwoOKOzNxYoSdBvIF8e0T/eWGcZkIrjSZHvAOVi2ttlH76VPWcvxfL6LmLV22XHKUawieyWIWHbEAbM1ym6SsShfc6E6/f8wIzL6HRPA9y2aZhLL3betuzHTavrn2UpcvkE6ZHoHUPzDjWAhLY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969823; c=relaxed/simple; bh=nt9WXl70jNXZ92RmyXR9xdR0VxISjP6PVLPZGJzG8+o=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=L/Vkc0LuNUjpZ2KY7+YFPN8vMcdKEprQBiiodIgGrXe0a8SyhMOx85toO6YCPi8c849mMJvDk+scb5dbz3Tc1zB8xxxGK6lNxHkFOiDn9ti1rewjaPZJXekZvIPXQU2VoWimQTJeGRZ7hbsY3lwCZR/9agskqUa/YDEQksPD8qE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=CQT61DjK; arc=none smtp.client-ip=210.118.77.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="CQT61DjK" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20250731135019euoutp01c150375710e93d55803068373e4037d0~XWkIXol0x0157501575euoutp01d for ; Thu, 31 Jul 2025 13:50:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20250731135019euoutp01c150375710e93d55803068373e4037d0~XWkIXol0x0157501575euoutp01d DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1753969819; bh=GqjP+sqWnHbA9FEjGQX5W1M8XprOwuwRbOKks19Q5zo=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=CQT61DjKDH9WRSh8myB97dE1/g8DAVsU9D9+ai5yjHRtsAdr/rb+D+ifmps7fwzuy h2Sms18vutJSLZU4zTZaibzZonCKchHN9fa647kzAaPoR4DJhLhXBbXEib6jvhX5k9 f5YnfLF96qpbX3Fx9OiHw1bE1IDe0ikXMrCzT6DE= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250731135019eucas1p1239902cf5a5a8fa40ea35722e6feb965~XWkH4ziN20233102331eucas1p1O; Thu, 31 Jul 2025 13:50:19 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250731135018eusmtip23c074c65c850d0ecb3aa1102bd2a0903~XWkG7Qs0A2644626446eusmtip2L; Thu, 31 Jul 2025 13:50:18 +0000 (GMT) From: Michal Wilczynski Date: Thu, 31 Jul 2025 15:50:12 +0200 Subject: [PATCH v9 2/5] dt-bindings: gpu: img,powervr-rogue: Define power domains per variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-apr_14_for_sending-v9-2-c242dc1ffc14@samsung.com> In-Reply-To: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250731135019eucas1p1239902cf5a5a8fa40ea35722e6feb965 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250731135019eucas1p1239902cf5a5a8fa40ea35722e6feb965 X-EPHeader: CA X-CMS-RootMailID: 20250731135019eucas1p1239902cf5a5a8fa40ea35722e6feb965 References: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> Rework the PowerVR Rogue GPU binding to use an explicit, per variant style for defining power domain properties. The generic `if` block for `img,img-rogue`, is removed. It is replaced with self-contained `if/then` blocks for each existing GPU variant. Each block now explicitly defines power domain properties and requirements for that specific variant, making the rules easier to read and maintain. This addresses feedback from the maintainer to explicitly list items for each variant [1]. Link: https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@lina= ro.org/ [1] Signed-off-by: Michal Wilczynski --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 36 ++++++++++--------= ---- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..24ce46ba0b7015fca799f045ee2= ccdd258088068 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -57,10 +57,8 @@ properties: maxItems: 2 =20 power-domain-names: - items: - - const: a - - const: b minItems: 1 + maxItems: 2 =20 dma-coherent: true =20 @@ -77,18 +75,6 @@ required: additionalProperties: false =20 allOf: - # Constraints added alongside the new compatible strings that would othe= rwise - # create an ABI break. - - if: - properties: - compatible: - contains: - const: img,img-rogue - then: - required: - - power-domains - - power-domain-names - - if: properties: compatible: @@ -97,9 +83,14 @@ allOf: then: properties: power-domains: - maxItems: 1 + items: + - description: Power domain A power-domain-names: - maxItems: 1 + items: + - const: a + required: + - power-domains + - power-domain-names =20 - if: properties: @@ -109,9 +100,16 @@ allOf: then: properties: power-domains: - minItems: 2 + items: + - description: Power domain A + - description: Power domain B power-domain-names: - minItems: 2 + items: + - const: a + - const: b + required: + - power-domains + - power-domain-names =20 - if: properties: --=20 2.34.1 From nobody Sun Oct 5 16:18:16 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC0E92D23A3 for ; Thu, 31 Jul 2025 13:50:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969831; cv=none; b=YJMW/s1KTOF4LELXgxPkr4uu41hfEeLESpXot++H7MQ52O6jJ+taTc3vu+ndauvBsUF7Km2UMGBczmeu5GeL/xBGLOnjOd1d7iqkXc9KcM1+LBiDw//lhKTuxpJZ46229sQcP3UESsdSf5SRoWba31MEEliE9uneOmTVh7zeFVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969831; c=relaxed/simple; bh=FJK7jcoW2OTvZWNfJpQX7PrdJmC/ePNdaJ5PJROYE+Y=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=mDcH4Hl5UyYF3PF8tPspJ6UuZwv91+sO0eI9/WMvoXuqpgmNzmiR7+8sMOLtxDHOdlSyR97Ps6YeHlXZnrXtBvp1MUOdUMu2HXKdYhA7PNFLudg44rKluHy+blA1TK1OnxXWW6qbCbzUsYn+wwV2K/ifDXmBms7hM+jleSpjq1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=PlcXZZgb; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="PlcXZZgb" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250731135021euoutp020f6e50903f32ecee7e8bba85f81f5fb5~XWkJpTvzE1417014170euoutp02O for ; Thu, 31 Jul 2025 13:50:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250731135021euoutp020f6e50903f32ecee7e8bba85f81f5fb5~XWkJpTvzE1417014170euoutp02O DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1753969821; bh=6W87Q1x1CQJtR6NEM1xR9BS/avezudE94uTfUvbF1vw=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=PlcXZZgbl9fevamWWHBq2+To55Ns+nxcG+AFIi5AIo9OeUsQECPbYUzyG1uM1lRC1 27ezTwycyDDVo35Rq/wb6OYQ0/Eok92SlkHfUdlJxVkD5MOtG1W0rlSrf34Ur3+7zb E+VpTV24obp9ZAIhq/d034mwkbg4+VJIDW+qfOkc= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250731135020eucas1p1e8f286222a03ec9b63a7409ff66c3238~XWkI6kFKx1671816718eucas1p1R; Thu, 31 Jul 2025 13:50:20 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250731135019eusmtip2d9c31dd3d47bb7debe5fd189ea191589~XWkH8uhaX3049130491eusmtip2R; Thu, 31 Jul 2025 13:50:19 +0000 (GMT) From: Michal Wilczynski Date: Thu, 31 Jul 2025 15:50:13 +0200 Subject: [PATCH v9 3/5] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-apr_14_for_sending-v9-3-c242dc1ffc14@samsung.com> In-Reply-To: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250731135020eucas1p1e8f286222a03ec9b63a7409ff66c3238 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250731135020eucas1p1e8f286222a03ec9b63a7409ff66c3238 X-EPHeader: CA X-CMS-RootMailID: 20250731135020eucas1p1e8f286222a03ec9b63a7409ff66c3238 References: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's specific GPU compatible string. The thead,th1520-gpu compatible, along with its full chain img,img-bxm-4-64, and img,img-rogue, is added to the list of recognized GPU types. While the BXM-4-64 GPU IP is designed with two distinct power domains, the TH1520 SoC integrates it with only a single, unified power gate that is controllable by the kernel. The binding enforces this with a specific if block for the thead,th1520-gpu compatible that requires a single power-domains entry and disallows power-domain-names. The B-series GPU rule is also updated to include img,img-bxm-4-64 and to explicitly exclude the TH1520. Signed-off-by: Michal Wilczynski --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 29 ++++++++++++++++++= +++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 24ce46ba0b7015fca799f045ee2ccdd258088068..e47e0f3d1b5078b3050e26f6c1a= c175edec528ec 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -21,6 +21,11 @@ properties: # work with newer dts. - const: img,img-axe - const: img,img-rogue + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue - items: - enum: - ti,j721s2-gpu @@ -96,7 +101,29 @@ allOf: properties: compatible: contains: - const: img,img-bxs-4-64 + const: thead,th1520-gpu + then: + properties: + power-domains: + items: + - description: The single, unified power domain for the GPU on= the + TH1520 SoC, integrating all internal IP power domains. + power-domain-names: false + required: + - power-domains + + - if: + properties: + compatible: + contains: + enum: + - img,img-bxm-4-64 + - img,img-bxs-4-64 + not: + properties: + compatible: + contains: + const: thead,th1520-gpu then: properties: power-domains: --=20 2.34.1 From nobody Sun Oct 5 16:18:16 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC1A42D23A5 for ; Thu, 31 Jul 2025 13:50:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969830; cv=none; b=Md+VCrAN6l4hCMtp+45u8ComYIwC1ML6fqbEOz1gSEofNYEIX7Y9Sz1vYOEHmPPBfQUNZmqnO6DBTHEN6OSiOrRWEX/QPm2cAKO8Y1uOfCa3TXE8e+oY/nmyKV1C5+c/zvC2B97eG6Pv1elf8Wk+DFhWOJdxnDterUI46Q/KVbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969830; c=relaxed/simple; bh=P7It3FMf29uKY5DKZnUmXnhqoBhVLO35ws15wFY52ZM=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=ggF3MJK6mIT0XxxrKAS+Zb4vBmK6da6synTrP7+XEHeWeJ+ZHqJnafvNLIe3ya1GM/k32pONPRMdabzDJyIyhwHSut9Wg9tWqvbSrKN4uMHdSmswgMszUGugOP7Tkhf5msOSJB98AIaLC9YryRhqpLUyt/p1vsSAxtyg72r02zU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=OXdujAG0; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="OXdujAG0" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250731135022euoutp02be4bf8a953e0d6095b9895fcae60c268~XWkKdRMfR1416414164euoutp02O for ; Thu, 31 Jul 2025 13:50:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250731135022euoutp02be4bf8a953e0d6095b9895fcae60c268~XWkKdRMfR1416414164euoutp02O DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1753969822; bh=VfsQJvjq5c9ev8IN+DYZ8WbeMJC6AfqTnoMPHMtlcaY=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=OXdujAG0rszUmzoNdWNVeBKiT7iavVKyRxNEgjzg/1MeqvpWaC3KoXSvTpAQxjP4/ z8ttJZ5kSw6LOViSf+aTpNX1+Aw7TcJEYygfFuZUC/VjQS+RD4HpIfFj9ou3mCUhgF nGkBAnEPLWUaU61OFQPFnVblldnWHVqlf+H6Fj+s= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250731135021eucas1p22c5267e560c135038e4175fc18d135aa~XWkJ93JQs2783527835eucas1p2L; Thu, 31 Jul 2025 13:50:21 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250731135020eusmtip28dbe050b38a266a945600abb6d911d01~XWkI_fC9w2644126441eusmtip2-; Thu, 31 Jul 2025 13:50:20 +0000 (GMT) From: Michal Wilczynski Date: Thu, 31 Jul 2025 15:50:14 +0200 Subject: [PATCH v9 4/5] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-apr_14_for_sending-v9-4-c242dc1ffc14@samsung.com> In-Reply-To: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250731135021eucas1p22c5267e560c135038e4175fc18d135aa X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250731135021eucas1p22c5267e560c135038e4175fc18d135aa X-EPHeader: CA X-CMS-RootMailID: 20250731135021eucas1p22c5267e560c135038e4175fc18d135aa References: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be controlled programatically. Reviewed-by: Ulf Hansson Reviewed-by: Drew Fustini Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 42724bf7e90e08fac326c464d0f080e3bd2cd59b..6ae5c632205ba63248c0a119c03= bdfc084aac7a0 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 { #clock-cells =3D <0>; }; =20 + gpu_mem_clk: mem-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + clock-output-names =3D "gpu_mem_clk"; + #clock-cells =3D <0>; + }; + stmmac_axi_config: stmmac-axi-config { snps,wr_osr_lmt =3D <15>; snps,rd_osr_lmt =3D <15>; @@ -500,6 +507,20 @@ clk: clock-controller@ffef010000 { #clock-cells =3D <1>; }; =20 + gpu: gpu@ffef400000 { + compatible =3D "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; + reg =3D <0xff 0xef400000 0x0 0x100000>; + interrupt-parent =3D <&plic>; + interrupts =3D <102 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_GPU_CORE>, + <&gpu_mem_clk>, + <&clk_vo CLK_GPU_CFG_ACLK>; + clock-names =3D "core", "mem", "sys"; + power-domains =3D <&aon TH1520_GPU_PD>; + resets =3D <&rst TH1520_RESET_ID_GPU>; + }; + rst: reset-controller@ffef528000 { compatible =3D "thead,th1520-reset"; reg =3D <0xff 0xef528000 0x0 0x4f>; --=20 2.34.1 From nobody Sun Oct 5 16:18:16 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 113012D23A9 for ; Thu, 31 Jul 2025 13:50:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969830; cv=none; b=p4CkAMXqk1pGbRZx5erEFuPHKRYJyVJzPNCA39OATuXLG4andCDgJ+u/+5MrbpgWRYAAmPSChCB+7h4DN4aPhAeKjZao09zzBV2rTPm3CUh1ZOmivIe8f/MJxOB2wBwc/DBnhKigNVt1FWuLUTPTI4mAbSWxzNl2Tjp7SCTn0QY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753969830; c=relaxed/simple; bh=Eqahkamg13uwXjpD2HqVe8PGEmKJKZBW1G6dF/3Hy5o=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=vF2CsSjI/tn1C/Fukz/PzO77/vuzUf7c6yQKDSpvuOX3eOmoitEjVqyuSThXGvPNtnPA7xF+zhB0UL5Fxpx2lC8wLSvjPqE3XicDUJ9+jd+mQ3V417k7+I13yEHh1wF28pU6ODQ/yXekapxXj6/qzx5pSligMWyzN04dv1k3RmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=Es8c2Yq5; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="Es8c2Yq5" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250731135023euoutp024fce1f1b5d33b187fd572a73860e0d0f~XWkLxip_M1416714167euoutp02F for ; Thu, 31 Jul 2025 13:50:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250731135023euoutp024fce1f1b5d33b187fd572a73860e0d0f~XWkLxip_M1416714167euoutp02F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1753969823; bh=o9pup7lxdlJYj1WCugUFlZF6W3E8/CCvLfzm1q+9rG4=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=Es8c2Yq5qhXWnh/0jOSHEfENH34QtVdjTK6zOwwr7JeShukwtnWhRcZIzpddg6o8c LaMHg5suhHtsPW8u9ABHWFVay6v99hvJCQyd1HydwARUYO1Remj7fxaQ6H6HMnSJTp qHgPYXT9sFvjahYKSkhSRKZm6Pd/WrsMSRwwuvnM= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250731135022eucas1p25e396efeb6096c7359a029a775d0f21f~XWkLCUHpl0703007030eucas1p2m; Thu, 31 Jul 2025 13:50:22 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250731135021eusmtip2a53c34b00c11d99c50154d27f553bfe5~XWkKBtDkV3049030490eusmtip2Z; Thu, 31 Jul 2025 13:50:21 +0000 (GMT) From: Michal Wilczynski Date: Thu, 31 Jul 2025 15:50:15 +0200 Subject: [PATCH v9 5/5] drm/imagination: Enable PowerVR driver for RISC-V Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250731-apr_14_for_sending-v9-5-c242dc1ffc14@samsung.com> In-Reply-To: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> To: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250731135022eucas1p25e396efeb6096c7359a029a775d0f21f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250731135022eucas1p25e396efeb6096c7359a029a775d0f21f X-EPHeader: CA X-CMS-RootMailID: 20250731135022eucas1p25e396efeb6096c7359a029a775d0f21f References: <20250731-apr_14_for_sending-v9-0-c242dc1ffc14@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. The RISC-V support is restricted to 64-bit systems (RISCV && 64BIT) as the driver currently has an implicit dependency on a 64-bit platform. Add a dependency on MMU to fix a build warning on RISC-V configurations without an MMU. Reviewed-by: Ulf Hansson Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imaginat= ion/Kconfig index 3bfa2ac212dccb73c53bdc2bc259bcba636e7cfc..682dd2633d0c012df18d0f7144d= 029b67a14d241 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,8 +3,9 @@ =20 config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Gra= phics" - depends on ARM64 + depends on (ARM64 || RISCV && 64BIT) depends on DRM + depends on MMU depends on PM select DRM_EXEC select DRM_GEM_SHMEM_HELPER --=20 2.34.1