From nobody Sun Oct 5 20:01:14 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4867E2E337E; Wed, 30 Jul 2025 16:08:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753891710; cv=none; b=cYvxT9KTLE1Z90CHRVclpPGeZHRhSU7Ex0gVsCWhvqB1MXviARvzpxGKY1kSe4XRVUZ0zQUxp86onHg7YNTXxMqKZ5GMiVp1QBSbblWWS6ZRXUIAlzqm6aMtNez4j6nO0loueLPNrxHw7rILopX+8N4p1x2nMz8HS1MXEOOqzcE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753891710; c=relaxed/simple; bh=jURueI/QgGrZ6um0yH99F1lStbRfGYLvaLrbClFpun0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lv/7B6ekRJBIWEX+ECh74r26cvRZWQ7L0lk3SHcDkWjItiI5ez4N7kJk57yztbTKCd0yrNnTJ+Bzt6l41pnp1LL/u7RyWhW/EuKsmPr+T/cwjHZdjhZgh9EKgcWWO1CpRIM4KPyztMtnwjJqvykTP0iumtJ4htUeQpbt8xs1FE4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q2vPn/qa; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q2vPn/qa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753891709; x=1785427709; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jURueI/QgGrZ6um0yH99F1lStbRfGYLvaLrbClFpun0=; b=Q2vPn/qaPen1KqbZDumNeA6sBBd9uOhgJzZ53ZAKDPHwCZ67Ohvc6Wtd EEO5u7R8i7qBSreH0pNZws5oe459SkKU52zIvgVBAebfO+sGzGqm8laIx mgYVxxcxMq2UvAuL75vP4VeZvzH+awHOuHdAAsBjKya+kho7RKN8L9ECI hSOAJ7136NdFO60zNNJUB3TZ/USg+oMfDuz/M2xHLsu4qnFYkG0eCb9tc AHu9CVHcmgCoXVbjRXJz8dF3GvkBKq5mPniHxolLFulIA3cF/FXlKEjsc 58YMWJ7N0ROdSQh4g+W9dYRNLFOikryLDkNM0Jk6xnntURopPpa6Qt+zk w==; X-CSE-ConnectionGUID: YXRTWFOsQxO+VhQZw7rz3w== X-CSE-MsgGUID: FfcmKh6qR76V8MzWBLwpDw== X-IronPort-AV: E=McAfee;i="6800,10657,11507"; a="67278887" X-IronPort-AV: E=Sophos;i="6.16,350,1744095600"; d="scan'208";a="67278887" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2025 09:08:29 -0700 X-CSE-ConnectionGUID: K4R7QIh3SealjWAvN2yBMw== X-CSE-MsgGUID: dtq0yOO9Q4KLR47Eb1dY+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,350,1744095600"; d="scan'208";a="163812986" Received: from newjersey.igk.intel.com ([10.102.20.203]) by fmviesa010.fm.intel.com with ESMTP; 30 Jul 2025 09:08:25 -0700 From: Alexander Lobakin To: intel-wired-lan@lists.osuosl.org Cc: Alexander Lobakin , Michal Kubiak , Maciej Fijalkowski , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexei Starovoitov , Daniel Borkmann , Simon Horman , nxne.cnse.osdt.itp.upstreaming@intel.com, bpf@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH iwl-next v3 10/18] idpf: add 4-byte completion descriptor definition Date: Wed, 30 Jul 2025 18:07:09 +0200 Message-ID: <20250730160717.28976-11-aleksander.lobakin@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250730160717.28976-1-aleksander.lobakin@intel.com> References: <20250730160717.28976-1-aleksander.lobakin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Michal Kubiak In the queue-based scheduling mode, Tx completion descriptor is 4 bytes comparing to 8 bytes in flow-based. Add definition for it and allocate the corresponding amount of memory for the descriptors during the completion queue creation. This does not include handling 4-byte completions during Tx polling, as for now, the only user of QB will be XDP, which has its own routines. Signed-off-by: Michal Kubiak Signed-off-by: Alexander Lobakin --- .../net/ethernet/intel/idpf/idpf_lan_txrx.h | 6 +++- drivers/net/ethernet/intel/idpf/idpf_txrx.h | 11 ++++-- drivers/net/ethernet/intel/idpf/idpf_txrx.c | 34 +++++++++++-------- 3 files changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h b/drivers/net/= ethernet/intel/idpf/idpf_lan_txrx.h index 7492d1713243..20d5af64e750 100644 --- a/drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h +++ b/drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h @@ -186,13 +186,17 @@ struct idpf_base_tx_desc { __le64 qw1; /* type_cmd_offset_bsz_l2tag1 */ }; /* read used with buffer queues */ =20 -struct idpf_splitq_tx_compl_desc { +struct idpf_splitq_4b_tx_compl_desc { /* qid=3D[10:0] comptype=3D[13:11] rsvd=3D[14] gen=3D[15] */ __le16 qid_comptype_gen; union { __le16 q_head; /* Queue head */ __le16 compl_tag; /* Completion tag */ } q_head_compl_tag; +}; /* writeback used with completion queues */ + +struct idpf_splitq_tx_compl_desc { + struct idpf_splitq_4b_tx_compl_desc common; u8 ts[3]; u8 rsvd; /* Reserved */ }; /* writeback used with completion queues */ diff --git a/drivers/net/ethernet/intel/idpf/idpf_txrx.h b/drivers/net/ethe= rnet/intel/idpf/idpf_txrx.h index 52753dff381c..11a318fd48d4 100644 --- a/drivers/net/ethernet/intel/idpf/idpf_txrx.h +++ b/drivers/net/ethernet/intel/idpf/idpf_txrx.h @@ -728,7 +728,9 @@ libeth_cacheline_set_assert(struct idpf_buf_queue, 64, = 24, 32); =20 /** * struct idpf_compl_queue - software structure representing a completion = queue - * @comp: completion descriptor array + * @comp: 8-byte completion descriptor array + * @comp_4b: 4-byte completion descriptor array + * @desc_ring: virtual descriptor ring address * @txq_grp: See struct idpf_txq_group * @flags: See enum idpf_queue_flags_t * @desc_count: Number of descriptors @@ -748,7 +750,12 @@ libeth_cacheline_set_assert(struct idpf_buf_queue, 64,= 24, 32); */ struct idpf_compl_queue { __cacheline_group_begin_aligned(read_mostly); - struct idpf_splitq_tx_compl_desc *comp; + union { + struct idpf_splitq_tx_compl_desc *comp; + struct idpf_splitq_4b_tx_compl_desc *comp_4b; + + void *desc_ring; + }; struct idpf_txq_group *txq_grp; =20 DECLARE_BITMAP(flags, __IDPF_Q_FLAGS_NBITS); diff --git a/drivers/net/ethernet/intel/idpf/idpf_txrx.c b/drivers/net/ethe= rnet/intel/idpf/idpf_txrx.c index 34dc12cf5b21..8a7b58ae05d4 100644 --- a/drivers/net/ethernet/intel/idpf/idpf_txrx.c +++ b/drivers/net/ethernet/intel/idpf/idpf_txrx.c @@ -95,8 +95,8 @@ static void idpf_compl_desc_rel(struct idpf_compl_queue *= complq) return; =20 dma_free_coherent(complq->netdev->dev.parent, complq->size, - complq->comp, complq->dma); - complq->comp =3D NULL; + complq->desc_ring, complq->dma); + complq->desc_ring =3D NULL; complq->next_to_use =3D 0; complq->next_to_clean =3D 0; } @@ -225,12 +225,16 @@ static int idpf_tx_desc_alloc(const struct idpf_vport= *vport, static int idpf_compl_desc_alloc(const struct idpf_vport *vport, struct idpf_compl_queue *complq) { - complq->size =3D array_size(complq->desc_count, sizeof(*complq->comp)); + u32 desc_size; =20 - complq->comp =3D dma_alloc_coherent(complq->netdev->dev.parent, - complq->size, &complq->dma, - GFP_KERNEL); - if (!complq->comp) + desc_size =3D idpf_queue_has(FLOW_SCH_EN, complq) ? + sizeof(*complq->comp) : sizeof(*complq->comp_4b); + complq->size =3D array_size(complq->desc_count, desc_size); + + complq->desc_ring =3D dma_alloc_coherent(complq->netdev->dev.parent, + complq->size, &complq->dma, + GFP_KERNEL); + if (!complq->desc_ring) return -ENOMEM; =20 complq->next_to_use =3D 0; @@ -1738,7 +1742,7 @@ static void idpf_tx_handle_rs_completion(struct idpf_= tx_queue *txq, /* RS completion contains queue head for queue based scheduling or * completion tag for flow based scheduling. */ - u16 rs_compl_val =3D le16_to_cpu(desc->q_head_compl_tag.q_head); + u16 rs_compl_val =3D le16_to_cpu(desc->common.q_head_compl_tag.q_head); =20 if (!idpf_queue_has(FLOW_SCH_EN, txq)) { idpf_tx_splitq_clean(txq, rs_compl_val, budget, cleaned, false); @@ -1773,19 +1777,19 @@ static bool idpf_tx_clean_complq(struct idpf_compl_= queue *complq, int budget, do { struct libeth_sq_napi_stats cleaned_stats =3D { }; struct idpf_tx_queue *tx_q; + __le16 hw_head; int rel_tx_qid; - u16 hw_head; u8 ctype; /* completion type */ u16 gen; =20 /* if the descriptor isn't done, no work yet to do */ - gen =3D le16_get_bits(tx_desc->qid_comptype_gen, + gen =3D le16_get_bits(tx_desc->common.qid_comptype_gen, IDPF_TXD_COMPLQ_GEN_M); if (idpf_queue_has(GEN_CHK, complq) !=3D gen) break; =20 /* Find necessary info of TX queue to clean buffers */ - rel_tx_qid =3D le16_get_bits(tx_desc->qid_comptype_gen, + rel_tx_qid =3D le16_get_bits(tx_desc->common.qid_comptype_gen, IDPF_TXD_COMPLQ_QID_M); if (rel_tx_qid >=3D complq->txq_grp->num_txq || !complq->txq_grp->txqs[rel_tx_qid]) { @@ -1795,14 +1799,14 @@ static bool idpf_tx_clean_complq(struct idpf_compl_= queue *complq, int budget, tx_q =3D complq->txq_grp->txqs[rel_tx_qid]; =20 /* Determine completion type */ - ctype =3D le16_get_bits(tx_desc->qid_comptype_gen, + ctype =3D le16_get_bits(tx_desc->common.qid_comptype_gen, IDPF_TXD_COMPLQ_COMPL_TYPE_M); switch (ctype) { case IDPF_TXD_COMPLT_RE: - hw_head =3D le16_to_cpu(tx_desc->q_head_compl_tag.q_head); + hw_head =3D tx_desc->common.q_head_compl_tag.q_head; =20 - idpf_tx_splitq_clean(tx_q, hw_head, budget, - &cleaned_stats, true); + idpf_tx_splitq_clean(tx_q, le16_to_cpu(hw_head), + budget, &cleaned_stats, true); break; case IDPF_TXD_COMPLT_RS: idpf_tx_handle_rs_completion(tx_q, tx_desc, --=20 2.50.1