From nobody Sat Feb 7 07:24:25 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D80A42951BD; Wed, 30 Jul 2025 10:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753873099; cv=none; b=W9bM0LbXiE8UcRlPiPE8ODpfRKUAWsTcAwrX6vHybYupML0x+HL1rZngldtOGhamVQs8xU4lW1ZzwdpnkAM285sMIZf+ryS6S61qXlRxUwslV6DT59HK7xEZCMlRTZYpAsVWNcT8GK3bQ5VLeUXk0E3D2bgBKd18Oofy4xCzGCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753873099; c=relaxed/simple; bh=Gb7IZwUlriHpo5vbmDTNk57nLTln98iuALB5y5tpq5c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=iRPhS2tvawwx/rlgWtCGoY6sj1cWGSxfKyEKEHAp87RFzS3CJyu+fsAJfK8SA0fG0yyN+qu1CfH2VEa23DcxnKd3MvzJRIOq+sygw3S8Ow2EWGGrKbtEGmXtcU4cFxoaWn2gB7HaHOcY1boFHfGyFkA+xqy/EfbW/hb/JU1c9yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=oaE+5Hee; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="oaE+5Hee" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753873095; bh=Gb7IZwUlriHpo5vbmDTNk57nLTln98iuALB5y5tpq5c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oaE+5HeehbZPse4DdKtVVwL597hkExSABPuT0iHyr3wVpSZcy+FPUnHVXSLNwm4Nr VTagTeUfnr8NHbogeeWhVv/pMDjUb5KS33v6UxwrV0EmgGRndEBO0JuiwTkfZdnN63 HFummwPM/l5lvD9hGT8KGUvj2W8u2OHmkVfWjoFh9yRQnxRziFTZ67vEGrcsiD60iV In3T25rj93l5s6F2itXWBEl9Sygq3z+SCwSTbKNcWI0uAxjfndBZG341nyqK6BeGj2 pd3kSobjpjN09JrAsxvnxyVixrMPh/QX1ayhvukJB5HxkBtAhtZauCLcLaXlbZGFFd bdO50fZjTnqpQ== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:4db2:e926:c82d:3276]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7183017E15D4; Wed, 30 Jul 2025 12:58:13 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH v3 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Date: Wed, 30 Jul 2025 12:56:32 +0200 Message-Id: <20250730105653.64910-7-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250730105653.64910-1-laura.nao@collabora.com> References: <20250730105653.64910-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MT8196 uses a HW voter for gate enable/disable control, with set/clr/sta registers located in a separate regmap. Refactor mtk_clk_register_gate() to take a struct mtk_gate instead of individual parameters, avoiding the need to add three extra arguments to support HW voter register offsets. Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao --- drivers/clk/mediatek/clk-gate.c | 35 ++++++++++++--------------------- 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gat= e.c index 67d9e741c5e7..0375ccad4be3 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -152,12 +152,9 @@ const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = =3D { }; EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); =20 -static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char= *name, - const char *parent_name, - struct regmap *regmap, int set_ofs, - int clr_ofs, int sta_ofs, u8 bit, - const struct clk_ops *ops, - unsigned long flags) +static struct clk_hw *mtk_clk_register_gate(struct device *dev, + const struct mtk_gate *gate, + struct regmap *regmap) { struct mtk_clk_gate *cg; int ret; @@ -167,17 +164,17 @@ static struct clk_hw *mtk_clk_register_gate(struct de= vice *dev, const char *name if (!cg) return ERR_PTR(-ENOMEM); =20 - init.name =3D name; - init.flags =3D flags | CLK_SET_RATE_PARENT; - init.parent_names =3D parent_name ? &parent_name : NULL; - init.num_parents =3D parent_name ? 1 : 0; - init.ops =3D ops; + init.name =3D gate->name; + init.flags =3D gate->flags | CLK_SET_RATE_PARENT; + init.parent_names =3D gate->parent_name ? &gate->parent_name : NULL; + init.num_parents =3D gate->parent_name ? 1 : 0; + init.ops =3D gate->ops; =20 cg->regmap =3D regmap; - cg->set_ofs =3D set_ofs; - cg->clr_ofs =3D clr_ofs; - cg->sta_ofs =3D sta_ofs; - cg->bit =3D bit; + cg->set_ofs =3D gate->regs->set_ofs; + cg->clr_ofs =3D gate->regs->clr_ofs; + cg->sta_ofs =3D gate->regs->sta_ofs; + cg->bit =3D gate->shift; =20 cg->hw.init =3D &init; =20 @@ -228,13 +225,7 @@ int mtk_clk_register_gates(struct device *dev, struct = device_node *node, continue; } =20 - hw =3D mtk_clk_register_gate(dev, gate->name, gate->parent_name, - regmap, - gate->regs->set_ofs, - gate->regs->clr_ofs, - gate->regs->sta_ofs, - gate->shift, gate->ops, - gate->flags); + hw =3D mtk_clk_register_gate(dev, gate, regmap); =20 if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", gate->name, --=20 2.39.5