From nobody Sun Oct 5 21:45:55 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60F5A1F4E4F; Wed, 30 Jul 2025 10:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753873096; cv=none; b=ndbV/GYctY9WHaSYgVIg4UKhXMz+KUZpKI6sKcl+zaGh8MbY7XT3RtSOe34c3quUJRSxlGcohb+4SNC/7bE3ohN5/JFDYe0kC/hLVyPf/G6y59d9a3KHeBtkgivHAaLaAhsaDiagG/5BDgcfmsWPjdDroy6CjGOJY5c0EhjoA0k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753873096; c=relaxed/simple; bh=RlcE9Jg2j9ECUaIkGmgoYUjHnr3YRO309JaqfhngUog=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=VGQ7kBQov47U07KYXfZ6RFnIx/do27oaC2M2iah1g6H0BoeV0r3oHZD7qapNfl7kXreFxEHFE8HVVOPlh3hN9zycwKYY2J3Ji2SZ3hQ8begvb06mYk0R5jC1LqrxEy/RL0zMoFdRe/ORLI+q47OUcWCafbWtQ7WbPoowA+/p2ak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Iby7kDm2; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Iby7kDm2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753873087; bh=RlcE9Jg2j9ECUaIkGmgoYUjHnr3YRO309JaqfhngUog=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Iby7kDm267sngdflxp4GxNYqOAJ0Y4X+cr/Bl8keQnW2trn06SMBVZb+u5nLcNM6q 6E1y5xuKGqU5kfSsGOLuUJPldWy+rM18VQeF5LOL5FcOA7iYLQ7+mOfV5/G8mUVz4w 6RRh6ZmrfOnkAjtssWyg2hEZqwS9IH1paYMy8Orv7ERafaUfICVeHzbBgwanL33VA/ 23sO3zW3yFAtHg5L3XF26zmgGc1A/TDqWzkpbT4cjRNnTlHXNIPNa5p/9u32/Vp1p6 XYHVWrGUxOt7npFGaTZOYzGTZzlNNxCSQMqXwKnyWDWyJL+y0KLA+Yw8b1PjorTqh4 qggaEMd6/qNTQ== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:4db2:e926:c82d:3276]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 45F3217E1319; Wed, 30 Jul 2025 12:58:06 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH v3 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Date: Wed, 30 Jul 2025 12:56:27 +0200 Message-Id: <20250730105653.64910-2-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250730105653.64910-1-laura.nao@collabora.com> References: <20250730105653.64910-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On MT8196, there are set/clr registers to control a shared PLL enable register. These are intended to prevent different masters from manipulating the PLLs independently. Add the corresponding en_set_reg and en_clr_reg fields to the mtk_pll_data structure. Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao --- drivers/clk/mediatek/clk-pll.c | 4 ++++ drivers/clk/mediatek/clk-pll.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index ce453e1718e5..49ca25dd5418 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -308,6 +308,10 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk= _pll *pll, pll->en_addr =3D base + data->en_reg; else pll->en_addr =3D pll->base_addr + REG_CON0; + if (data->en_set_reg) + pll->en_set_addr =3D base + data->en_set_reg; + if (data->en_clr_reg) + pll->en_clr_addr =3D base + data->en_clr_reg; pll->hw.init =3D &init; pll->data =3D data; =20 diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index 285c8db958b3..c4d06bb11516 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -47,6 +47,8 @@ struct mtk_pll_data { const struct mtk_pll_div_table *div_table; const char *parent_name; u32 en_reg; + u32 en_set_reg; + u32 en_clr_reg; u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ u8 pcw_chg_bit; }; @@ -68,6 +70,8 @@ struct mtk_clk_pll { void __iomem *pcw_addr; void __iomem *pcw_chg_addr; void __iomem *en_addr; + void __iomem *en_set_addr; + void __iomem *en_clr_addr; const struct mtk_pll_data *data; }; =20 --=20 2.39.5