From nobody Sun Oct 5 21:48:08 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F50429E115; Wed, 30 Jul 2025 10:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753873111; cv=none; b=r6q14yItFq+wbd+2MiIUowduLsw6i12reOipJZgF9/XKgqMJQiiN6YyCudi2wdV7zXi74lkKMyRE9WlGp4JEtfBPjK2xXeCozEviDZZ20Dg/K37+MHGXgM5z1s5aM1jbRjZqvOkeXnOt+RpnsmkOJZawS/7tRBiabfQ+ng+IFS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753873111; c=relaxed/simple; bh=V10M5KrcGqdwBWP5pRAuvn9wiUQebMYaxvUagELScFU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=rjW/JkqxOAWXAW25izZm1Fbr6A6C6UMun/QvajWq3vfECkWIjEtYybHZBVxI8Z9xjLbZf88zeG1THxT1EMkzpenQj6kqb+fDPr6MC6fM/KPQWWNUH/pkNh7U4t/vvu4Tke2BaXLq1jYHq+CpGfqAHVyR6TQkx9vuffh5MuFapo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=HrmR5P8M; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="HrmR5P8M" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753873107; bh=V10M5KrcGqdwBWP5pRAuvn9wiUQebMYaxvUagELScFU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HrmR5P8MItnujaaH+YTayGPP3AG4K1LuoZPCrridRHqhQ3425+plriNHmAbmFGn8k /PoFS8wZcrNQ+SPlN7VmdGt+sprO4b6anUqb+G9ma7I47VVzbDOrFDo62vksmm25jb yPlBrwiuCg7XcJ2/mG202/LL6GSU3p6GXa/P0tHIclQd9mT3Lzi7V69xnveYiwTg+7 r3yAOjFsSnQ21JYamTGGZOI7unEO10h1bjDmCzOTYMJJeep3BewVrm4jBJ8BPWw63P MM01cxhEfAVk0+fZ/P7zT1Xwp1OHR8JQholQBDWuen6qTKGmkr2FJsHuJvia4VUte6 yYFO3GHLbNtDg== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:4db2:e926:c82d:3276]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 36F6B17E130E; Wed, 30 Jul 2025 12:58:26 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH v3 15/27] clk: mediatek: Add MT8196 ufssys clock support Date: Wed, 30 Jul 2025 12:56:41 +0200 Message-Id: <20250730105653.64910-16-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250730105653.64910-1-laura.nao@collabora.com> References: <20250730105653.64910-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for the MT8196 ufssys clock controller, which provides clock gate control for UFS. Reviewed-by: N=C3=ADcolas F. R. A. Prado Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 109 +++++++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index c55a7c8bdcc5..848624792a23 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -1068,6 +1068,13 @@ config COMMON_CLK_MT8196 help This driver supports MediaTek MT8196 basic clocks. =20 +config COMMON_CLK_MT8196_UFSSYS + tristate "Clock driver for MediaTek MT8196 ufssys" + depends on COMMON_CLK_MT8196 + default COMMON_CLK_MT8196 + help + This driver supports MediaTek MT8196 ufssys clocks. + config COMMON_CLK_MT8365 tristate "Clock driver for MediaTek MT8365" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index fc941b5baf04..ee6a1bb5ce38 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -163,6 +163,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) +=3D clk-mt8195-= wpe.o obj-$(CONFIG_COMMON_CLK_MT8196) +=3D clk-mt8196-apmixedsys.o clk-mt8196-to= pckgen.o \ clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \ clk-mt8196-peri_ao.o +obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) +=3D clk-mt8196-ufs_ao.o obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365-apmixedsys.o clk-mt8365.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) +=3D clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) +=3D clk-mt8365-cam.o diff --git a/drivers/clk/mediatek/clk-mt8196-ufs_ao.c b/drivers/clk/mediate= k/clk-mt8196-ufs_ao.c new file mode 100644 index 000000000000..858706b3ba6f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8196-ufs_ao.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao + */ +#include +#include +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#define MT8196_UFSAO_RST0_SET_OFFSET 0x48 +#define MT8196_UFSAO_RST1_SET_OFFSET 0x148 + +static const struct mtk_gate_regs ufsao0_cg_regs =3D { + .set_ofs =3D 0x108, + .clr_ofs =3D 0x10c, + .sta_ofs =3D 0x104, +}; + +static const struct mtk_gate_regs ufsao1_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0xc, + .sta_ofs =3D 0x4, +}; + +#define GATE_UFSAO0(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &ufsao0_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_OPS_PARENT_ENABLE, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_UFSAO1(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &ufsao1_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_OPS_PARENT_ENABLE, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate ufsao_clks[] =3D { + /* UFSAO0 */ + GATE_UFSAO0(CLK_UFSAO_UFSHCI_UFS, "ufsao_ufshci_ufs", "ufs", 0), + GATE_UFSAO0(CLK_UFSAO_UFSHCI_AES, "ufsao_ufshci_aes", "aes_ufsfde", 1), + /* UFSAO1 */ + GATE_UFSAO1(CLK_UFSAO_UNIPRO_TX_SYM, "ufsao_unipro_tx_sym", "clk26m", 0), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM0, "ufsao_unipro_rx_sym0", "clk26m", 1= ), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM1, "ufsao_unipro_rx_sym1", "clk26m", 2= ), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_SYS, "ufsao_unipro_sys", "ufs", 3), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_SAP, "ufsao_unipro_sap", "clk26m", 4), + GATE_UFSAO1(CLK_UFSAO_PHY_SAP, "ufsao_phy_sap", "clk26m", 8), +}; + +static u16 ufsao_rst_ofs[] =3D { + MT8196_UFSAO_RST0_SET_OFFSET, + MT8196_UFSAO_RST1_SET_OFFSET +}; + +static u16 ufsao_rst_idx_map[] =3D { + [MT8196_UFSAO_RST0_UFS_MPHY] =3D 8, + [MT8196_UFSAO_RST1_UFS_UNIPRO] =3D 1 * RST_NR_PER_BANK + 0, + [MT8196_UFSAO_RST1_UFS_CRYPTO] =3D 1 * RST_NR_PER_BANK + 1, + [MT8196_UFSAO_RST1_UFSHCI] =3D 1 * RST_NR_PER_BANK + 2, +}; + +static const struct mtk_clk_rst_desc ufsao_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D ufsao_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(ufsao_rst_ofs), + .rst_idx_map =3D ufsao_rst_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(ufsao_rst_idx_map), +}; + +static const struct mtk_clk_desc ufsao_mcd =3D { + .clks =3D ufsao_clks, + .num_clks =3D ARRAY_SIZE(ufsao_clks), + .rst_desc =3D &ufsao_rst_desc, +}; + +static const struct of_device_id of_match_clk_mt8196_ufs_ao[] =3D { + { .compatible =3D "mediatek,mt8196-ufscfg-ao", .data =3D &ufsao_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ufs_ao); + +static struct platform_driver clk_mt8196_ufs_ao_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8196-ufs-ao", + .of_match_table =3D of_match_clk_mt8196_ufs_ao, + }, +}; + +module_platform_driver(clk_mt8196_ufs_ao_drv); +MODULE_DESCRIPTION("MediaTek MT8196 ufs_ao clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5