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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:18 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com, Arnd Bergmann Subject: [PATCH v2 01/20] clocksource/drivers/vf-pit: Replace raw_readl/writel to reald/writel Date: Wed, 30 Jul 2025 10:27:03 +0200 Message-ID: <20250730082725.183133-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver uses the raw_readl() and raw_writel() functions. Those are not for MMIO devices. Replace them with readl() and writel() Signed-off-by: Daniel Lezcano Cc: Arnd Bergmann --- drivers/clocksource/timer-vf-pit.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 911c92146eca..8041a8f62d1f 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -35,30 +35,30 @@ static unsigned long cycle_per_jiffy; =20 static inline void pit_timer_enable(void) { - __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); + writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); } =20 static inline void pit_timer_disable(void) { - __raw_writel(0, clkevt_base + PITTCTRL); + writel(0, clkevt_base + PITTCTRL); } =20 static inline void pit_irq_acknowledge(void) { - __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); + writel(PITTFLG_TIF, clkevt_base + PITTFLG); } =20 static u64 notrace pit_read_sched_clock(void) { - return ~__raw_readl(clksrc_base + PITCVAL); + return ~readl(clksrc_base + PITCVAL); } =20 static int __init pit_clocksource_init(unsigned long rate) { /* set the max load value and start the clock source counter */ - __raw_writel(0, clksrc_base + PITTCTRL); - __raw_writel(~0UL, clksrc_base + PITLDVAL); - __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); + writel(0, clksrc_base + PITTCTRL); + writel(~0UL, clksrc_base + PITLDVAL); + writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); =20 sched_clock_register(pit_read_sched_clock, 32, rate); return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, @@ -76,7 +76,7 @@ static int pit_set_next_event(unsigned long delta, * hardware requirement. */ pit_timer_disable(); - __raw_writel(delta - 1, clkevt_base + PITLDVAL); + writel(delta - 1, clkevt_base + PITLDVAL); pit_timer_enable(); =20 return 0; @@ -125,8 +125,8 @@ static struct clock_event_device clockevent_pit =3D { =20 static int __init pit_clockevent_init(unsigned long rate, int irq) { - __raw_writel(0, clkevt_base + PITTCTRL); - __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); + writel(0, clkevt_base + PITTCTRL); + writel(PITTFLG_TIF, clkevt_base + PITTFLG); =20 BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "VF pit timer", &clockevent_pit)); @@ -183,7 +183,7 @@ static int __init pit_timer_init(struct device_node *np) cycle_per_jiffy =3D clk_rate / (HZ); =20 /* enable the pit module */ - __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); + writel(~PITMCR_MDIS, timer_base + PITMCR); =20 ret =3D pit_clocksource_init(clk_rate); if (ret) --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E74B25A34F for ; Wed, 30 Jul 2025 08:28:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; 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(146725694.box.freepro.com. [130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:19 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 02/20] clocksource/drivers/vf-pit: Add COMPILE_TEST option Date: Wed, 30 Jul 2025 10:27:04 +0200 Message-ID: <20250730082725.183133-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The VF PIT driver is a silent koption. In order to allow a better compilation test coverage, let's add the COMPILE_TEST option so it can be selected on other platforms than the Vybrid Family. Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 645f517a1ac2..6f7d371904df 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -475,7 +475,7 @@ config FSL_FTM_TIMER Support for Freescale FlexTimer Module (FTM) timer. =20 config VF_PIT_TIMER - bool + bool "Vybrid Family Programmable timer" if COMPILE_TEST select CLKSRC_MMIO help Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs. --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 578DE266B67 for ; Wed, 30 Jul 2025 08:28:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753864105; cv=none; b=RPGYXHrWU4PjzDU5dPrZ9Cw9G2ibNNhtzvHrd/L3MMZiz7xAKPn54kpqVXuQ55YzHBSPSt8lv8sP0K8aoIxB5g8ttHnmTbsAoMxqVlMEfLwr7MZw9ZsL3iYD4zSpt/Abx0qZLMOTlGsuU8iN0F1npN3omCc+Ro2UyVfFuFO4NSI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753864105; c=relaxed/simple; bh=lB1+NV5iSNlFSlhTC8Xxt8kaeBogF43m8ZXjdWSORVM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=U0UIOyvrVDZcxiSbNfKQu+s9K5QrJVxJPqZlPniFszwKO6H+OYpKf3GrX3T5en9U9lialxhKLglbdE0XQuw146M7hHHDeJ/WIRV44EH+8kRiAsV9ADpuR0CIyKtudeWwoA7zGh28ME2zCeG/NcgN9Xh6K5go4/dP2qW9iHY+D9k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=XEqGCTuE; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XEqGCTuE" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4560cdf235cso31166175e9.1 for ; Wed, 30 Jul 2025 01:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753864102; x=1754468902; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oF76aiNEz7qF+G8H8HzTyPMCcCc+/sIEb5cmvblT5b4=; b=XEqGCTuEbv867mdeR8S7cvqvdOfMVXwrcjA1z0W6zO/C2zAuxVoRAVTW1Pp6aSFrpE p5ttx5epdbKUQJUGJUdCW5k3PSrGlGPPOGKJoZoEdGbTmXYCK0CS51ci2Uzu8T+mHaAz 6EzMyUL/kjrOf69ycWfDhqUdUI3A5uUSPQq6LxJgaEqsWftNTEhcWoazQmmFmF7nAF9E kbu5+e2k+KdBs0iVNIt12/YIodmeC34Pv9MHX3nU/g/h1BZEd5lthT3cLkS2Yv594siI Ob81T/9+6H8hxdlAGs/k6200HpSHb/TOE0q1x4Z43W/PXFtbbsL2lttALR8Bvb2n8NOT QaGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753864102; x=1754468902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oF76aiNEz7qF+G8H8HzTyPMCcCc+/sIEb5cmvblT5b4=; b=mNzVIxPalDjgUMR5js5kSjHxE4LHNR4K88FT2Adpi02Z9CqGFyYEiXboav9h6bxB/+ j9R40vyPJJks5hDNrrDBWAFsRPn54RZzmaoOsopv0+kYrkOY7AAvyc8+aPRaKpd2f9ZP TS5cf2RSqFuWWnZIWXmRqtCk687HrF6VY5199prOyFaKhRcqEl/fDjnZPJ3Utq1nJyrX AW54tPiZt0V6xAzzD8dAafXwEu87AaNMRHqdsQT8I9FHK24//3jpMhvvVBtYw6lHD7pF lMddYm1wfP8IaNTeYuut2vxyZ53SgzCN1dhv7NJUocIDjUO4VitVwfcOavDrCkoED61j rdaw== X-Forwarded-Encrypted: i=1; AJvYcCXqmMGPHr/aM9e/lAiXAFmQnvtKkMHQhLSPXzhAOwf8eL+SsJcglMr4EtG14C3UYqK+J9YW/PYKX9B04/Y=@vger.kernel.org X-Gm-Message-State: AOJu0YzuYbnnTqlJd8GW3L1SJdYzuQvqkv6UQWxQlYKUydnbvHK8kuSB yJmpDHJgN7ft+U/3Dfm7Ufp3cnN3Fhz4AajGNxGuWMnTq6rcZ9v2w4QtWp9O5plVdXc= X-Gm-Gg: ASbGncs73U/veUoJ4X2aaeK9Yje+GS1fTgsM82YKwF7Tnulgcdmeu/CW4yU9u3T231a hRtcw2mUm895N8oLeozyvQ8UZm+eLC/fTH4zfguZIeSvu0dcKzT4J2IZHpCwqEj6fQd9zNwQcrM odvIGSP6lLEfR0WMT+LegV7w0OQl8M6mc8f7GxunvqZR2wKCn3orvkfCwOsUDshbR90Luukjmur yA+Cl++S7UbTq53Rk3OnrGn/MvSOL8TtRt07xnjvIK5YfQeexTykpIuSFlGzd3yR4G/TRqU1Tsg fKVx4fn03KYWxiavimsDhUoJtPwpFV90LJrZrJM7o/6Rq0P2kNj9RYw6PS/AO1DlnDiXIaGKlCU /O6q1azljVjhNPekJXb7DTe7UxwYM8BR2CauTPQXGkO4evDHpVNIaJ9cUPYc= X-Google-Smtp-Source: AGHT+IEUEqNsNVOLPSa6ckRwv9gWPeqsiwcVdgR6NOXeFT0B/IM+wnnZ+dAhRaGYk9Hr6PLDMJAEKA== X-Received: by 2002:a05:600c:1f92:b0:43c:f0ae:da7 with SMTP id 5b1f17b1804b1-45892b95237mr19550945e9.7.1753864101550; Wed, 30 Jul 2025 01:28:21 -0700 (PDT) Received: from mai.. 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:21 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 03/20] clocksource/drivers/vf-pit: Set the scene for multiple timers Date: Wed, 30 Jul 2025 10:27:05 +0200 Message-ID: <20250730082725.183133-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver is implemented as using a single timer and a single clocksource. In order to take advantage of the multiple timers supported in the PIT hardware and introduce different setup for a new platform, let's encapsulate the data into a structure and pass this structure around in the function parameter. The structure will be a per timer instansiation in the next changes. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 121 +++++++++++++++++------------ 1 file changed, 72 insertions(+), 49 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 8041a8f62d1f..e4a8b32fff75 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -15,7 +15,7 @@ */ #define PITMCR 0x00 #define PIT0_OFFSET 0x100 -#define PITn_OFFSET(n) (PIT0_OFFSET + 0x10 * (n)) +#define PIT_CH(n) (PIT0_OFFSET + 0x10 * (n)) #define PITLDVAL 0x00 #define PITCVAL 0x04 #define PITTCTRL 0x08 @@ -29,23 +29,36 @@ =20 #define PITTFLG_TIF 0x1 =20 +struct pit_timer { + void __iomem *clksrc_base; + void __iomem *clkevt_base; + unsigned long cycle_per_jiffy; + struct clock_event_device ced; + struct clocksource cs; +}; + +static struct pit_timer pit_timer; + static void __iomem *clksrc_base; -static void __iomem *clkevt_base; -static unsigned long cycle_per_jiffy; =20 -static inline void pit_timer_enable(void) +static inline struct pit_timer *ced_to_pit(struct clock_event_device *ced) { - writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); + return container_of(ced, struct pit_timer, ced); } =20 -static inline void pit_timer_disable(void) +static inline void pit_timer_enable(struct pit_timer *pit) { - writel(0, clkevt_base + PITTCTRL); + writel(PITTCTRL_TEN | PITTCTRL_TIE, pit->clkevt_base + PITTCTRL); } =20 -static inline void pit_irq_acknowledge(void) +static inline void pit_timer_disable(struct pit_timer *pit) { - writel(PITTFLG_TIF, clkevt_base + PITTFLG); + writel(0, pit->clkevt_base + PITTCTRL); +} + +static inline void pit_irq_acknowledge(struct pit_timer *pit) +{ + writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG); } =20 static u64 notrace pit_read_sched_clock(void) @@ -53,21 +66,24 @@ static u64 notrace pit_read_sched_clock(void) return ~readl(clksrc_base + PITCVAL); } =20 -static int __init pit_clocksource_init(unsigned long rate) +static int __init pit_clocksource_init(struct pit_timer *pit, unsigned lon= g rate) { /* set the max load value and start the clock source counter */ - writel(0, clksrc_base + PITTCTRL); - writel(~0UL, clksrc_base + PITLDVAL); - writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); + writel(0, pit->clksrc_base + PITTCTRL); + writel(~0, pit->clksrc_base + PITLDVAL); + writel(PITTCTRL_TEN, pit->clksrc_base + PITTCTRL); + + clksrc_base =3D pit->clksrc_base; =20 sched_clock_register(pit_read_sched_clock, 32, rate); - return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, + return clocksource_mmio_init(pit->clksrc_base + PITCVAL, "vf-pit", rate, 300, 32, clocksource_mmio_readl_down); } =20 -static int pit_set_next_event(unsigned long delta, - struct clock_event_device *unused) +static int pit_set_next_event(unsigned long delta, struct clock_event_devi= ce *ced) { + struct pit_timer *pit =3D ced_to_pit(ced); + /* * set a new value to PITLDVAL register will not restart the timer, * to abort the current cycle and start a timer period with the new @@ -75,30 +91,37 @@ static int pit_set_next_event(unsigned long delta, * and the PITLAVAL should be set to delta minus one according to pit * hardware requirement. */ - pit_timer_disable(); - writel(delta - 1, clkevt_base + PITLDVAL); - pit_timer_enable(); + pit_timer_disable(pit); + writel(delta - 1, pit->clkevt_base + PITLDVAL); + pit_timer_enable(pit); =20 return 0; } =20 -static int pit_shutdown(struct clock_event_device *evt) +static int pit_shutdown(struct clock_event_device *ced) { - pit_timer_disable(); + struct pit_timer *pit =3D ced_to_pit(ced); + + pit_timer_disable(pit); + return 0; } =20 -static int pit_set_periodic(struct clock_event_device *evt) +static int pit_set_periodic(struct clock_event_device *ced) { - pit_set_next_event(cycle_per_jiffy, evt); + struct pit_timer *pit =3D ced_to_pit(ced); + + pit_set_next_event(pit->cycle_per_jiffy, ced); + return 0; } =20 static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt =3D dev_id; + struct clock_event_device *ced =3D dev_id; + struct pit_timer *pit =3D ced_to_pit(ced); =20 - pit_irq_acknowledge(); + pit_irq_acknowledge(pit); =20 /* * pit hardware doesn't support oneshot, it will generate an interrupt @@ -106,33 +129,33 @@ static irqreturn_t pit_timer_interrupt(int irq, void = *dev_id) * and start the counter again. So software need to disable the timer * to stop the counter loop in ONESHOT mode. */ - if (likely(clockevent_state_oneshot(evt))) - pit_timer_disable(); + if (likely(clockevent_state_oneshot(ced))) + pit_timer_disable(pit); =20 - evt->event_handler(evt); + ced->event_handler(ced); =20 return IRQ_HANDLED; } =20 -static struct clock_event_device clockevent_pit =3D { - .name =3D "VF pit timer", - .features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown =3D pit_shutdown, - .set_state_periodic =3D pit_set_periodic, - .set_next_event =3D pit_set_next_event, - .rating =3D 300, -}; - -static int __init pit_clockevent_init(unsigned long rate, int irq) +static int __init pit_clockevent_init(struct pit_timer *pit, unsigned long= rate, int irq) { - writel(0, clkevt_base + PITTCTRL); - writel(PITTFLG_TIF, clkevt_base + PITTFLG); + writel(0, pit->clkevt_base + PITTCTRL); + + writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG); =20 BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "VF pit timer", &clockevent_pit)); + "VF pit timer", &pit->ced)); + + pit->ced.cpumask =3D cpumask_of(0); + pit->ced.irq =3D irq; + + pit->ced.name =3D "VF pit timer"; + pit->ced.features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + pit->ced.set_state_shutdown =3D pit_shutdown; + pit->ced.set_state_periodic =3D pit_set_periodic; + pit->ced.set_next_event =3D pit_set_next_event; + pit->ced.rating =3D 300; =20 - clockevent_pit.cpumask =3D cpumask_of(0); - clockevent_pit.irq =3D irq; /* * The value for the LDVAL register trigger is calculated as: * LDVAL trigger =3D (period / clock period) - 1 @@ -141,7 +164,7 @@ static int __init pit_clockevent_init(unsigned long rat= e, int irq) * LDVAL trigger value is 1. And then the min_delta is * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit. */ - clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff); + clockevents_config_and_register(&pit->ced, rate, 2, 0xffffffff); =20 return 0; } @@ -164,8 +187,8 @@ static int __init pit_timer_init(struct device_node *np) * so choose PIT2 as clocksource, PIT3 as clockevent device, * and leave PIT0 and PIT1 unused for anyone else who needs them. */ - clksrc_base =3D timer_base + PITn_OFFSET(2); - clkevt_base =3D timer_base + PITn_OFFSET(3); + pit_timer.clksrc_base =3D timer_base + PIT_CH(2); + pit_timer.clkevt_base =3D timer_base + PIT_CH(3); =20 irq =3D irq_of_parse_and_map(np, 0); if (irq <=3D 0) @@ -180,15 +203,15 @@ static int __init pit_timer_init(struct device_node *= np) return ret; =20 clk_rate =3D clk_get_rate(pit_clk); - cycle_per_jiffy =3D clk_rate / (HZ); + pit_timer.cycle_per_jiffy =3D clk_rate / (HZ); =20 /* enable the pit module */ writel(~PITMCR_MDIS, timer_base + PITMCR); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:22 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 04/20] clocksource/drivers/vf-pit: Rework the base address usage Date: Wed, 30 Jul 2025 10:27:06 +0200 Message-ID: <20250730082725.183133-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This change passes the base address to the clockevent and clocksource initialization functions in order to use different base address in the next changes. No functional changes intended. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 35 +++++++++++++++++++----------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index e4a8b32fff75..6a5f940ad0bc 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -66,8 +66,16 @@ static u64 notrace pit_read_sched_clock(void) return ~readl(clksrc_base + PITCVAL); } =20 -static int __init pit_clocksource_init(struct pit_timer *pit, unsigned lon= g rate) +static int __init pit_clocksource_init(struct pit_timer *pit, void __iomem= *base, + unsigned long rate) { + /* + * The channels 0 and 1 can be chained to build a 64-bit + * timer. Let's use the channel 2 as a clocksource and leave + * the channels 0 and 1 unused for anyone else who needs them + */ + pit->clksrc_base =3D base + PIT_CH(2); + /* set the max load value and start the clock source counter */ writel(0, pit->clksrc_base + PITTCTRL); writel(~0, pit->clksrc_base + PITLDVAL); @@ -76,8 +84,9 @@ static int __init pit_clocksource_init(struct pit_timer *= pit, unsigned long rate clksrc_base =3D pit->clksrc_base; =20 sched_clock_register(pit_read_sched_clock, 32, rate); + return clocksource_mmio_init(pit->clksrc_base + PITCVAL, "vf-pit", rate, - 300, 32, clocksource_mmio_readl_down); + 300, 32, clocksource_mmio_readl_down); } =20 static int pit_set_next_event(unsigned long delta, struct clock_event_devi= ce *ced) @@ -137,8 +146,16 @@ static irqreturn_t pit_timer_interrupt(int irq, void *= dev_id) return IRQ_HANDLED; } =20 -static int __init pit_clockevent_init(struct pit_timer *pit, unsigned long= rate, int irq) +static int __init pit_clockevent_init(struct pit_timer *pit, void __iomem = *base, + unsigned long rate, int irq) { + /* + * The channels 0 and 1 can be chained to build a 64-bit + * timer. Let's use the channel 3 as a clockevent and leave + * the channels 0 and 1 unused for anyone else who needs them + */ + pit->clkevt_base =3D base + PIT_CH(3); + writel(0, pit->clkevt_base + PITTCTRL); =20 writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG); @@ -182,14 +199,6 @@ static int __init pit_timer_init(struct device_node *n= p) return -ENXIO; } =20 - /* - * PIT0 and PIT1 can be chained to build a 64-bit timer, - * so choose PIT2 as clocksource, PIT3 as clockevent device, - * and leave PIT0 and PIT1 unused for anyone else who needs them. - */ - pit_timer.clksrc_base =3D timer_base + PIT_CH(2); - pit_timer.clkevt_base =3D timer_base + PIT_CH(3); - irq =3D irq_of_parse_and_map(np, 0); if (irq <=3D 0) return -EINVAL; @@ -208,10 +217,10 @@ static int __init pit_timer_init(struct device_node *= np) /* enable the pit module */ writel(~PITMCR_MDIS, timer_base + PITMCR); =20 - ret =3D pit_clocksource_init(&pit_timer, clk_rate); + ret =3D pit_clocksource_init(&pit_timer, timer_base, clk_rate); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:23 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 05/20] clocksource/drivers/vf-pit: Pass the cpu number as parameter Date: Wed, 30 Jul 2025 10:27:07 +0200 Message-ID: <20250730082725.183133-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to initialize the timer with a cpumask tied to a cpu, let's pass it as a parameter instead of hardwiring it in the init function. No functional changes intended. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 6a5f940ad0bc..9f3b72be987a 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -147,7 +147,7 @@ static irqreturn_t pit_timer_interrupt(int irq, void *d= ev_id) } =20 static int __init pit_clockevent_init(struct pit_timer *pit, void __iomem = *base, - unsigned long rate, int irq) + unsigned long rate, int irq, unsigned int cpu) { /* * The channels 0 and 1 can be chained to build a 64-bit @@ -163,7 +163,7 @@ static int __init pit_clockevent_init(struct pit_timer = *pit, void __iomem *base, BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "VF pit timer", &pit->ced)); =20 - pit->ced.cpumask =3D cpumask_of(0); + pit->ced.cpumask =3D cpumask_of(cpu); pit->ced.irq =3D irq; =20 pit->ced.name =3D "VF pit timer"; @@ -221,6 +221,6 @@ static int __init pit_timer_init(struct device_node *np) if (ret) return ret; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:24 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 06/20] clocksource/drivers/vf-pit: Encapsulate the initialization of the cycles_per_jiffy Date: Wed, 30 Jul 2025 10:27:08 +0200 Message-ID: <20250730082725.183133-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the cycles_per_jiffy initialization to the same place where the other pit timer fields are initialized. No functional changes intended. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 9f3b72be987a..a11e6a63c79f 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -155,6 +155,7 @@ static int __init pit_clockevent_init(struct pit_timer = *pit, void __iomem *base, * the channels 0 and 1 unused for anyone else who needs them */ pit->clkevt_base =3D base + PIT_CH(3); + pit->cycle_per_jiffy =3D rate / (HZ); =20 writel(0, pit->clkevt_base + PITTCTRL); =20 @@ -212,7 +213,6 @@ static int __init pit_timer_init(struct device_node *np) return ret; =20 clk_rate =3D clk_get_rate(pit_clk); - pit_timer.cycle_per_jiffy =3D clk_rate / (HZ); =20 /* enable the pit module */ writel(~PITMCR_MDIS, timer_base + PITMCR); --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB008262FC5 for ; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:24 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 07/20] clocksource/drivers/vf-pit: Allocate the struct timer at init time Date: Wed, 30 Jul 2025 10:27:09 +0200 Message-ID: <20250730082725.183133-8-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of having a static global structure for a timer, let's allocate it dynamically so we can create multiple instances in the future to support multiple timers. At the same time, add the rollbacking code in case of error. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 48 +++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index a11e6a63c79f..d408dcddb4e9 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -37,8 +37,6 @@ struct pit_timer { struct clocksource cs; }; =20 -static struct pit_timer pit_timer; - static void __iomem *clksrc_base; =20 static inline struct pit_timer *ced_to_pit(struct clock_event_device *ced) @@ -189,38 +187,66 @@ static int __init pit_clockevent_init(struct pit_time= r *pit, void __iomem *base, =20 static int __init pit_timer_init(struct device_node *np) { + struct pit_timer *pit; struct clk *pit_clk; void __iomem *timer_base; unsigned long clk_rate; int irq, ret; =20 + pit =3D kzalloc(sizeof(*pit), GFP_KERNEL); + if (!pit) + return -ENOMEM; + + ret =3D -ENXIO; timer_base =3D of_iomap(np, 0); if (!timer_base) { pr_err("Failed to iomap\n"); - return -ENXIO; + goto out_kfree; } =20 + ret =3D -EINVAL; irq =3D irq_of_parse_and_map(np, 0); - if (irq <=3D 0) - return -EINVAL; + if (irq <=3D 0) { + pr_err("Failed to irq_of_parse_and_map\n"); + goto out_iounmap; + } =20 pit_clk =3D of_clk_get(np, 0); - if (IS_ERR(pit_clk)) - return PTR_ERR(pit_clk); + if (IS_ERR(pit_clk)) { + ret =3D PTR_ERR(pit_clk); + goto out_iounmap; + } =20 ret =3D clk_prepare_enable(pit_clk); if (ret) - return ret; + goto out_clk_put; =20 clk_rate =3D clk_get_rate(pit_clk); =20 /* enable the pit module */ writel(~PITMCR_MDIS, timer_base + PITMCR); =20 - ret =3D pit_clocksource_init(&pit_timer, timer_base, clk_rate); + ret =3D pit_clocksource_init(pit, timer_base, clk_rate); if (ret) - return ret; + goto out_disable_unprepare; + + ret =3D pit_clockevent_init(pit, timer_base, clk_rate, irq, 0); + if (ret) + goto out_pit_clocksource_unregister; + + return 0; =20 - return pit_clockevent_init(&pit_timer, timer_base, clk_rate, irq, 0); +out_pit_clocksource_unregister: + clocksource_unregister(&pit->cs); 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No functional change intended. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index d408dcddb4e9..d1aec6aaeb02 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -21,11 +21,11 @@ #define PITTCTRL 0x08 #define PITTFLG 0x0c =20 -#define PITMCR_MDIS (0x1 << 1) +#define PITMCR_MDIS BIT(1) =20 -#define PITTCTRL_TEN (0x1 << 0) -#define PITTCTRL_TIE (0x1 << 1) -#define PITCTRL_CHN (0x1 << 2) +#define PITTCTRL_TEN BIT(0) +#define PITTCTRL_TIE BIT(1) +#define PITCTRL_CHN BIT(2) =20 #define PITTFLG_TIF 0x1 =20 --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03658293C45 for ; Wed, 30 Jul 2025 08:28:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753864110; cv=none; b=Rrw96CgjAOcJuEcMcdn9t3nqVti6jCjSoklQH/4tP+vAL3eFJDAHvgiunkrULp+gP9EBjSox/I/j7Mt6Mz02LYlwOd3I0G1hxGMsXbYUK1VayI5w+ntJ5xNF66wpimsZ+Cqto9qRASmr/06ML1Xs1LtHwmo48H6j5gfo0+OrEX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753864110; c=relaxed/simple; bh=GfQzwNUl/+3omCCkQkujjBdEzx8xgVxwbwy3bH02h/E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i6WwJznz9WQf0RMZGrd6R/HFYgLWu9cCzoh9GYlYhz45LcwCPo1PfQVlJAbR+8kKJIl1pju03YNh1s+qbTJ0UifkVOSsPi78WrtSrzsu3kI5IT277G6aElWIVu+0/0ps/G+RJTT0Ec/LvHHSV5BHcoxgzkOxJQKnJ/mVFjq1yS8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=wqEIliuW; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wqEIliuW" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-3b783d851e6so3424794f8f.0 for ; Wed, 30 Jul 2025 01:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753864107; x=1754468907; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8Kg1N7IKrT0Nex/PfaqDl7XqOb3/89XK53bW16WuXbM=; b=wqEIliuWzNSeU+r4jzEJqsqDFF6cHta1sBN9yc5G2PJn8tGTnH1+rQOLTV3ldaPiZt Hg27kqJJ06tjJLD5j/VfQL4srSDeLa5dMWHq38URMjIExC+IwBHC2G5Q2O+qn5mhklgp do7oGXSifk2EYKygpphpTB2JC5BDUKCezPzN9d/Z1oCbz+YxRHG1ERktnJj0QJ9bduiT q0U4xpPHNxX7phYpj6G6Y7c4e8Q3Tz+pEpewfw9FVdgEYiI6KKEkuf3zm5X15dm1Wez2 uPOGS0bQJuZsgqbR7mI+KKK+IvNRHQmQ75m72e9UgJyz17DmJrEjPdQDXG++jzonWOdt xBGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753864107; x=1754468907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Kg1N7IKrT0Nex/PfaqDl7XqOb3/89XK53bW16WuXbM=; b=k8MK/02GrkI46ySgQsx9Sfiws+fWm0Yh35gP2D06ej/DFQsxF+ATYytodD3ZGWdY9P M+8ZBx5s2M8GzocWTfn4H/kB2FNRcxvdI4FSfsWV/phFgZKgf1VniY1jqsEwv+QnbaNi HrPekQHyxzhw4g4da1GvEOdellPNe68ix0/0wpPn95psE9SKeM7QQH4xK90pro95uiRe paEgLGzzRBl9oskzI3vgg8nDoyMuEA1RCYXrYRc/VKHPFKSYB0nLurLIl0hHZOUQUJCL 0cEPJJqc/kxFDDgSxdsh35cV4ogYJDqmGR//2SFOkWCdvoJDRfBoWB7nSuAAhg0mdWu8 qdzQ== X-Forwarded-Encrypted: i=1; AJvYcCUmCp7LuAaETceqH7fV/UL+V8rbgtawJ6xkAE9mr9/VlGOs0XDrjT6hxmjBylso4CXVgZyVB+KITRcqCns=@vger.kernel.org X-Gm-Message-State: AOJu0YyWqCo6mE7iPH3gYCEHxZQYhif38WTZmX6B/iS1lrVHh+mnrwXz q16bhuea24bi1ovOIi155L22XDGouukGr3bSdY3wXYxj8IUiKK63ELNxOozotUmIhsw= X-Gm-Gg: ASbGncugwFDeGK0gae/5d4W18kvXx9szffnTm25eGO+77SpaD8de60ekf4ckR+X72rK NBChJxcRlTuPZPKZkuhseEQVFwwP3Gjmf/8ZnwZDwMgkHMB0xOdh6YH+ohzw2M7KlcGwpkUCQG1 63yXBuPkjCRc90rAZ1dl/ba3d0e/8rw5Mvk/rgHhPOZuIiN4gpSe6Oh0xe0AOsXEpqOncXObYLV SQkP3semtuqhO20FMQ4fBNIO9INVkb3b7wGGMhCxPWKDbgLAq11eAsVIIGaj22/d59Max19Wo10 ffqzVH8sK6vX+S1Kt4S/gTfYdbBXiEioLs0ffS5YlzSRMOHg9pSDh6gg+6M93vWu2GcRR18B2yC zY/1CZxMzAnwsxME74tztIxJZ0RPIeVaUBSeDKYpfMdLlqsod X-Google-Smtp-Source: AGHT+IGfrV1oS65LoHrjnQuwVg/JWvOsiypKJwdoZ5rsfC7kAm0dtOTzXRqOWgsRdhfqwug+YacotA== X-Received: by 2002:a05:6000:238a:b0:3a4:e480:b5df with SMTP id ffacd0b85a97d-3b79500efd4mr2117066f8f.44.1753864107412; Wed, 30 Jul 2025 01:28:27 -0700 (PDT) Received: from mai.. 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:26 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 09/20] clocksource/drivers/vf-pit: Register the clocksource from the driver Date: Wed, 30 Jul 2025 10:27:11 +0200 Message-ID: <20250730082725.183133-10-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The function clocksource_mmio_init() uses its own global static clocksource variable making no possible to have several instances of a clocksource using this function. In order to support that, let's add the clocksource structure to the pit structure and use the clocksource_register_hz() function instead. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index d1aec6aaeb02..6a4043801eeb 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -44,6 +44,11 @@ static inline struct pit_timer *ced_to_pit(struct clock_= event_device *ced) return container_of(ced, struct pit_timer, ced); } =20 +static inline struct pit_timer *cs_to_pit(struct clocksource *cs) +{ + return container_of(cs, struct pit_timer, cs); +} + static inline void pit_timer_enable(struct pit_timer *pit) { writel(PITTCTRL_TEN | PITTCTRL_TIE, pit->clkevt_base + PITTCTRL); @@ -64,6 +69,13 @@ static u64 notrace pit_read_sched_clock(void) return ~readl(clksrc_base + PITCVAL); } =20 +static u64 pit_timer_clocksource_read(struct clocksource *cs) +{ + struct pit_timer *pit =3D cs_to_pit(cs); + + return (u64)~readl(pit->clksrc_base + PITCVAL); +} + static int __init pit_clocksource_init(struct pit_timer *pit, void __iomem= *base, unsigned long rate) { @@ -73,6 +85,11 @@ static int __init pit_clocksource_init(struct pit_timer = *pit, void __iomem *base * the channels 0 and 1 unused for anyone else who needs them */ pit->clksrc_base =3D base + PIT_CH(2); + pit->cs.name =3D "vf-pit"; + pit->cs.rating =3D 300; + pit->cs.read =3D pit_timer_clocksource_read; + pit->cs.mask =3D CLOCKSOURCE_MASK(32); + pit->cs.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; =20 /* set the max load value and start the clock source counter */ writel(0, pit->clksrc_base + PITTCTRL); @@ -83,8 +100,7 @@ static int __init pit_clocksource_init(struct pit_timer = *pit, void __iomem *base =20 sched_clock_register(pit_read_sched_clock, 32, rate); =20 - return clocksource_mmio_init(pit->clksrc_base + PITCVAL, "vf-pit", rate, - 300, 32, clocksource_mmio_readl_down); + return clocksource_register_hz(&pit->cs, rate); } =20 static int pit_set_next_event(unsigned long delta, struct clock_event_devi= ce *ced) --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449E2294A10 for ; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:27 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 10/20] clocksource/drivers/vf-pit: Encapsulate the macros Date: Wed, 30 Jul 2025 10:27:12 +0200 Message-ID: <20250730082725.183133-11-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pass the base address to the macro, so we can use the macro with multiple instances of the timer because we deal with different base address. At the same time, change writes to the register to the existing corresponding functions. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 35 ++++++++++++++++-------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 6a4043801eeb..8f0e26c0512d 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -16,18 +16,21 @@ #define PITMCR 0x00 #define PIT0_OFFSET 0x100 #define PIT_CH(n) (PIT0_OFFSET + 0x10 * (n)) -#define PITLDVAL 0x00 + #define PITCVAL 0x04 -#define PITTCTRL 0x08 -#define PITTFLG 0x0c =20 #define PITMCR_MDIS BIT(1) =20 -#define PITTCTRL_TEN BIT(0) -#define PITTCTRL_TIE BIT(1) -#define PITCTRL_CHN BIT(2) +#define PITLDVAL(__base) (__base) +#define PITTCTRL(__base) ((__base) + 0x08) + + +#define PITTCTRL_TEN BIT(0) +#define PITTCTRL_TIE BIT(1) + +#define PITTFLG(__base) ((__base) + 0x0c) =20 -#define PITTFLG_TIF 0x1 +#define PITTFLG_TIF BIT(0) =20 struct pit_timer { void __iomem *clksrc_base; @@ -51,17 +54,17 @@ static inline struct pit_timer *cs_to_pit(struct clocks= ource *cs) =20 static inline void pit_timer_enable(struct pit_timer *pit) { - writel(PITTCTRL_TEN | PITTCTRL_TIE, pit->clkevt_base + PITTCTRL); + writel(PITTCTRL_TEN | PITTCTRL_TIE, PITTCTRL(pit->clkevt_base)); } =20 static inline void pit_timer_disable(struct pit_timer *pit) { - writel(0, pit->clkevt_base + PITTCTRL); + writel(0, PITTCTRL(pit->clkevt_base)); } =20 static inline void pit_irq_acknowledge(struct pit_timer *pit) { - writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG); + writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base)); } =20 static u64 notrace pit_read_sched_clock(void) @@ -92,9 +95,9 @@ static int __init pit_clocksource_init(struct pit_timer *= pit, void __iomem *base pit->cs.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; =20 /* set the max load value and start the clock source counter */ - writel(0, pit->clksrc_base + PITTCTRL); - writel(~0, pit->clksrc_base + PITLDVAL); - writel(PITTCTRL_TEN, pit->clksrc_base + PITTCTRL); + pit_timer_disable(pit); + writel(~0, PITLDVAL(pit->clksrc_base)); + writel(PITTCTRL_TEN, PITTCTRL(pit->clksrc_base)); =20 clksrc_base =3D pit->clksrc_base; =20 @@ -115,7 +118,7 @@ static int pit_set_next_event(unsigned long delta, stru= ct clock_event_device *ce * hardware requirement. */ pit_timer_disable(pit); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:29 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 11/20] clocksource/drivers/vf-pit: Encapsulate the PTLCVAL macro Date: Wed, 30 Jul 2025 10:27:13 +0200 Message-ID: <20250730082725.183133-12-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pass the channel and the base address to the PITLCVAL macro so it is possible to use multiple instances of the timer with the macro. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 8f0e26c0512d..4f1b85ba5de3 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -17,13 +17,13 @@ #define PIT0_OFFSET 0x100 #define PIT_CH(n) (PIT0_OFFSET + 0x10 * (n)) =20 -#define PITCVAL 0x04 - #define PITMCR_MDIS BIT(1) =20 #define PITLDVAL(__base) (__base) #define PITTCTRL(__base) ((__base) + 0x08) =20 +#define PITCVAL_OFFSET 0x04 +#define PITCVAL(__base) ((__base) + 0x04) =20 #define PITTCTRL_TEN BIT(0) #define PITTCTRL_TIE BIT(1) @@ -40,7 +40,7 @@ struct pit_timer { struct clocksource cs; }; =20 -static void __iomem *clksrc_base; +static void __iomem *sched_clock_base; =20 static inline struct pit_timer *ced_to_pit(struct clock_event_device *ced) { @@ -69,14 +69,14 @@ static inline void pit_irq_acknowledge(struct pit_timer= *pit) =20 static u64 notrace pit_read_sched_clock(void) { - return ~readl(clksrc_base + PITCVAL); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:30 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 12/20] clocksource/drivers/vf-pit: Use the node name for the interrupt and timer names Date: Wed, 30 Jul 2025 10:27:14 +0200 Message-ID: <20250730082725.183133-13-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to differentiate from userspace the pit timer given the device tree, let's use the node name for the interrupt and the timer names. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 4f1b85ba5de3..2a255b45561d 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -79,8 +79,8 @@ static u64 pit_timer_clocksource_read(struct clocksource = *cs) return (u64)~readl(PITCVAL(pit->clksrc_base)); } =20 -static int __init pit_clocksource_init(struct pit_timer *pit, void __iomem= *base, - unsigned long rate) +static int __init pit_clocksource_init(struct pit_timer *pit, const char *= name, + void __iomem *base, unsigned long rate) { /* * The channels 0 and 1 can be chained to build a 64-bit @@ -88,7 +88,7 @@ static int __init pit_clocksource_init(struct pit_timer *= pit, void __iomem *base * the channels 0 and 1 unused for anyone else who needs them */ pit->clksrc_base =3D base + PIT_CH(2); - pit->cs.name =3D "vf-pit"; + pit->cs.name =3D name; pit->cs.rating =3D 300; pit->cs.read =3D pit_timer_clocksource_read; pit->cs.mask =3D CLOCKSOURCE_MASK(32); @@ -162,8 +162,9 @@ static irqreturn_t pit_timer_interrupt(int irq, void *d= ev_id) return IRQ_HANDLED; } =20 -static int __init pit_clockevent_init(struct pit_timer *pit, void __iomem = *base, - unsigned long rate, int irq, unsigned int cpu) +static int __init pit_clockevent_init(struct pit_timer *pit, const char *n= ame, + void __iomem *base, unsigned long rate, + int irq, unsigned int cpu) { /* * The channels 0 and 1 can be chained to build a 64-bit @@ -178,12 +179,12 @@ static int __init pit_clockevent_init(struct pit_time= r *pit, void __iomem *base, pit_irq_acknowledge(pit); =20 BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "VF pit timer", &pit->ced)); + name, &pit->ced)); =20 pit->ced.cpumask =3D cpumask_of(cpu); pit->ced.irq =3D irq; =20 - pit->ced.name =3D "VF pit timer"; + pit->ced.name =3D name; pit->ced.features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; pit->ced.set_state_shutdown =3D pit_shutdown; pit->ced.set_state_periodic =3D pit_set_periodic; @@ -208,6 +209,7 @@ static int __init pit_timer_init(struct device_node *np) struct pit_timer *pit; struct clk *pit_clk; void __iomem *timer_base; + const char *name =3D of_node_full_name(np); unsigned long clk_rate; int irq, ret; =20 @@ -244,11 +246,11 @@ static int __init pit_timer_init(struct device_node *= np) /* enable the pit module */ writel(~PITMCR_MDIS, timer_base + PITMCR); =20 - ret =3D pit_clocksource_init(pit, timer_base, clk_rate); + ret =3D pit_clocksource_init(pit, name, timer_base, clk_rate); if (ret) goto out_disable_unprepare; =20 - ret =3D pit_clockevent_init(pit, timer_base, clk_rate, irq, 0); + ret =3D pit_clockevent_init(pit, name, timer_base, clk_rate, irq, 0); if (ret) goto out_pit_clocksource_unregister; =20 --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31F0529614F for ; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:31 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 13/20] clocksource/drivers/vf-pit: Encapsulate clocksource enable / disable Date: Wed, 30 Jul 2025 10:27:15 +0200 Message-ID: <20250730082725.183133-14-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the sake of lisibility, let's encapsulate the writel calls to enable and disable the timer into a function with a self-explainatory name. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 2a255b45561d..96377088a048 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -62,6 +62,16 @@ static inline void pit_timer_disable(struct pit_timer *p= it) writel(0, PITTCTRL(pit->clkevt_base)); } =20 +static inline void pit_clocksource_enable(struct pit_timer *pit) +{ + writel(PITTCTRL_TEN, PITTCTRL(pit->clksrc_base)); +} + +static inline void pit_clocksource_disable(struct pit_timer *pit) +{ + pit_timer_disable(pit); +} + static inline void pit_irq_acknowledge(struct pit_timer *pit) { writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base)); @@ -95,9 +105,9 @@ static int __init pit_clocksource_init(struct pit_timer = *pit, const char *name, pit->cs.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; =20 /* set the max load value and start the clock source counter */ - pit_timer_disable(pit); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:32 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 14/20] clocksource/drivers/vf-pit: Enable and disable module on error Date: Wed, 30 Jul 2025 10:27:16 +0200 Message-ID: <20250730082725.183133-15-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Encapsulate the calls to writel to enable and disable the PIT module and make use of them. Add the missing module disablement in case of error. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 96377088a048..609a4d9deb64 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -13,10 +13,12 @@ /* * Each pit takes 0x10 Bytes register space */ -#define PITMCR 0x00 #define PIT0_OFFSET 0x100 #define PIT_CH(n) (PIT0_OFFSET + 0x10 * (n)) =20 +#define PITMCR(__base) (__base) + +#define PITMCR_FRZ BIT(0) #define PITMCR_MDIS BIT(1) =20 #define PITLDVAL(__base) (__base) @@ -52,6 +54,16 @@ static inline struct pit_timer *cs_to_pit(struct clockso= urce *cs) return container_of(cs, struct pit_timer, cs); } =20 +static inline void pit_module_enable(void __iomem *base) +{ + writel(0, PITMCR(base)); +} + +static inline void pit_module_disable(void __iomem *base) +{ + writel(PITMCR_MDIS, PITMCR(base)); +} + static inline void pit_timer_enable(struct pit_timer *pit) { writel(PITTCTRL_TEN | PITTCTRL_TIE, PITTCTRL(pit->clkevt_base)); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:33 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 15/20] clocksource/drivers/vf-pit: Encapsulate set counter function Date: Wed, 30 Jul 2025 10:27:17 +0200 Message-ID: <20250730082725.183133-16-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Encapsulate the writel() calls to set the counter into a self-explainatory function. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 609a4d9deb64..5551b61483f8 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -74,6 +74,11 @@ static inline void pit_timer_disable(struct pit_timer *p= it) writel(0, PITTCTRL(pit->clkevt_base)); } =20 +static inline void pit_timer_set_counter(void __iomem *base, unsigned int = cnt) +{ + writel(cnt, PITLDVAL(base)); +} + static inline void pit_clocksource_enable(struct pit_timer *pit) { writel(PITTCTRL_TEN, PITTCTRL(pit->clksrc_base)); @@ -118,7 +123,7 @@ static int __init pit_clocksource_init(struct pit_timer= *pit, const char *name, =20 /* set the max load value and start the clock source counter */ pit_clocksource_disable(pit); - writel(~0, PITLDVAL(pit->clksrc_base)); + pit_timer_set_counter(pit->clksrc_base, ~0); pit_clocksource_enable(pit); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:34 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 16/20] clocksource/drivers/vf-pit: Consolidate calls to pit_*_disable/enable Date: Wed, 30 Jul 2025 10:27:18 +0200 Message-ID: <20250730082725.183133-17-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The difference between the pit_clocksource_enable() and pit_clocksource_disable() is only setting the TIF flag for the clockevent. Let's group them and pass the TIF flag parameter to the function so we save some lines of code. But as the base address is different regarding if it is a clocksource or a clockevent, we pass the base address in parameter instead of the struct pit_timer. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 34 ++++++++++++------------------ 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 5551b61483f8..3825159a0ca7 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -64,14 +64,16 @@ static inline void pit_module_disable(void __iomem *bas= e) writel(PITMCR_MDIS, PITMCR(base)); } =20 -static inline void pit_timer_enable(struct pit_timer *pit) +static inline void pit_timer_enable(void __iomem *base, bool tie) { - writel(PITTCTRL_TEN | PITTCTRL_TIE, PITTCTRL(pit->clkevt_base)); + u32 val =3D PITTCTRL_TEN | (tie ? PITTCTRL_TIE : 0); + + writel(val, PITTCTRL(base)); } =20 -static inline void pit_timer_disable(struct pit_timer *pit) +static inline void pit_timer_disable(void __iomem *base) { - writel(0, PITTCTRL(pit->clkevt_base)); + writel(0, PITTCTRL(base)); } =20 static inline void pit_timer_set_counter(void __iomem *base, unsigned int = cnt) @@ -79,16 +81,6 @@ static inline void pit_timer_set_counter(void __iomem *b= ase, unsigned int cnt) writel(cnt, PITLDVAL(base)); } =20 -static inline void pit_clocksource_enable(struct pit_timer *pit) -{ - writel(PITTCTRL_TEN, PITTCTRL(pit->clksrc_base)); -} - -static inline void pit_clocksource_disable(struct pit_timer *pit) -{ - pit_timer_disable(pit); -} - static inline void pit_irq_acknowledge(struct pit_timer *pit) { writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base)); @@ -122,9 +114,9 @@ static int __init pit_clocksource_init(struct pit_timer= *pit, const char *name, pit->cs.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; =20 /* set the max load value and start the clock source counter */ - pit_clocksource_disable(pit); + pit_timer_disable(pit->clksrc_base); pit_timer_set_counter(pit->clksrc_base, ~0); - pit_clocksource_enable(pit); + pit_timer_enable(pit->clksrc_base, 0); =20 sched_clock_base =3D pit->clksrc_base + PITCVAL_OFFSET; sched_clock_register(pit_read_sched_clock, 32, rate); @@ -143,9 +135,9 @@ static int pit_set_next_event(unsigned long delta, stru= ct clock_event_device *ce * and the PITLAVAL should be set to delta minus one according to pit * hardware requirement. */ - pit_timer_disable(pit); + pit_timer_disable(pit->clkevt_base); pit_timer_set_counter(pit->clkevt_base, delta - 1); - pit_timer_enable(pit); + pit_timer_enable(pit->clkevt_base, true); =20 return 0; } @@ -154,7 +146,7 @@ static int pit_shutdown(struct clock_event_device *ced) { struct pit_timer *pit =3D ced_to_pit(ced); =20 - pit_timer_disable(pit); + pit_timer_disable(pit->clkevt_base); =20 return 0; } @@ -182,7 +174,7 @@ static irqreturn_t pit_timer_interrupt(int irq, void *d= ev_id) * to stop the counter loop in ONESHOT mode. */ if (likely(clockevent_state_oneshot(ced))) - pit_timer_disable(pit); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:35 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 17/20] clocksource/drivers/vf-pit: Unify the function name for irq ack Date: Wed, 30 Jul 2025 10:27:19 +0200 Message-ID: <20250730082725.183133-18-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Most the function are under the form pit_timer_*, let's change the interrupt acknowledgement function name to have the same format. No functional changes intended. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -vf-pit.c index 3825159a0ca7..2a0ee4109ead 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -81,7 +81,7 @@ static inline void pit_timer_set_counter(void __iomem *ba= se, unsigned int cnt) writel(cnt, PITLDVAL(base)); } =20 -static inline void pit_irq_acknowledge(struct pit_timer *pit) +static inline void pit_timer_irqack(struct pit_timer *pit) { writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base)); } @@ -165,7 +165,7 @@ static irqreturn_t pit_timer_interrupt(int irq, void *d= ev_id) struct clock_event_device *ced =3D dev_id; struct pit_timer *pit =3D ced_to_pit(ced); =20 - pit_irq_acknowledge(pit); + pit_timer_irqack(pit); =20 /* * pit hardware doesn't support oneshot, it will generate an interrupt @@ -195,7 +195,7 @@ static int __init pit_clockevent_init(struct pit_timer = *pit, const char *name, =20 pit_timer_disable(pit->clkevt_base); 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:36 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 18/20] clocksource/drivers/vf-pit: Rename the VF PIT to NXP PIT Date: Wed, 30 Jul 2025 10:27:20 +0200 Message-ID: <20250730082725.183133-19-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PIT acronym stands for Periodic Interrupt Timer which is found on different NXP platforms not only on the Vybrid Family. Change the name to be more generic for the NXP platforms in general. That will be consistent with the NXP STM driver naming convention. Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 9 ++++++--- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{timer-vf-pit.c =3D> timer-nxp-pit.c} | 0 3 files changed, 7 insertions(+), 4 deletions(-) rename drivers/clocksource/{timer-vf-pit.c =3D> timer-nxp-pit.c} (100%) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 6f7d371904df..0fd662f67d29 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -474,11 +474,14 @@ config FSL_FTM_TIMER help Support for Freescale FlexTimer Module (FTM) timer. =20 -config VF_PIT_TIMER - bool "Vybrid Family Programmable timer" if COMPILE_TEST +config NXP_PIT_TIMER + bool "NXP Periodic Interrupt Timer" if COMPILE_TEST select CLKSRC_MMIO help - Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs. + Support for Periodic Interrupt Timer on Freescale / NXP + SoCs. This periodic timer is found on the Vybrid Family and + the Automotive S32G2/3 platforms. It contains 4 channels + where two can be coupled to form a 64 bits channel. =20 config SYS_SUPPORTS_SH_CMT bool diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 205bf3b0a8f3..77a0f08eb43b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -49,7 +49,7 @@ obj-$(CONFIG_CLKSRC_LPC32XX) +=3D timer-lpc32xx.o obj-$(CONFIG_CLKSRC_MPS2) +=3D mps2-timer.o obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) +=3D samsung_pwm_timer.o obj-$(CONFIG_FSL_FTM_TIMER) +=3D timer-fsl-ftm.o -obj-$(CONFIG_VF_PIT_TIMER) +=3D timer-vf-pit.o +obj-$(CONFIG_NXP_PIT_TIMER) +=3D timer-nxp-pit.o obj-$(CONFIG_CLKSRC_QCOM) +=3D timer-qcom.o obj-$(CONFIG_MTK_TIMER) +=3D timer-mediatek.o obj-$(CONFIG_MTK_CPUX_TIMER) +=3D timer-mediatek-cpux.o diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer= -nxp-pit.c similarity index 100% rename from drivers/clocksource/timer-vf-pit.c rename to drivers/clocksource/timer-nxp-pit.c --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92DF729A31D for ; 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:37 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v2 19/20] dt: bindings: fsl,vf610-pit: Add compatible for s32g2 and s32g3 Date: Wed, 30 Jul 2025 10:27:21 +0200 Message-ID: <20250730082725.183133-20-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Vybrid Family is a NXP (formerly Freescale) platform having a Programmable Interrupt Timer (PIT). This timer is an IP found also on the NXP Automotive platform S32G2 and S32G3. Add the compatible for those platforms to describe the timer. Signed-off-by: Daniel Lezcano Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/timer/fsl,vf610-pit.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/D= ocumentation/devicetree/bindings/timer/fsl,vf610-pit.yaml index bee2c35bd0e2..2aac63a58bfd 100644 --- a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml @@ -15,8 +15,12 @@ description: =20 properties: compatible: - enum: - - fsl,vf610-pit + oneOf: + - const: fsl,vf610-pit + - const: nxp,s32g2-pit + - items: + - const: nxp,s32g3-pit + - const: nxp,s32g2-pit =20 reg: maxItems: 1 --=20 2.43.0 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31AB929A9FA for ; Wed, 30 Jul 2025 08:28:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753864123; cv=none; b=d1w7IsHWeSdcHaOEiZ0rB21Lw1e/lkY/k/MqlUAZmRk10ZfoFKeRJD+lFhmDMLIkwgSlEQwJZ+944NWRqin5ImWkCl5mZPC6SKKVK2dLKwgnZ4IutE6KRuHzCJy3o+VEskj94jPlIhFHjR85v0fbW/zBFyXC/emWBsHdScjKZOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753864123; c=relaxed/simple; bh=ZcJ2JgK+m6G7VNBbCRvp0aVnvN/WcWX0nVtQG4Ay86E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XyRHiM169ked5GZrOhnLOBeiJ3up5jLAi5SxgYyE4fJUWtg6XCQb2SiUmisZ79p7BNqvRKOybhhZfTz6HpoznGXR6zSmZqmdHT15ssQe37COeRJyZXv4hY3zVCB2zQ46Jv3rOSehWun2R5X/QilUVNAyuYzAni7o0aKZyzdGrOQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WmC2dTQj; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WmC2dTQj" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4563bc166a5so3343855e9.1 for ; Wed, 30 Jul 2025 01:28:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753864119; x=1754468919; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lOXsofV7d5Y1QpSZQsIBgp8cuSodqQc2mblmLGbM94w=; b=WmC2dTQjvH0nw+sUIbvxrfV3s5+MHGavst2silOhyqGAhFYFccDU2mCikhva3J1+sn kNs/YozjCFwwPRn+1T+z7Y2f+sDi4qsekylhiqxdfX89WbcQrTkYh/yj08mfhLxjpiBi YeMYAlL+cA35eoollz+POTfOzGUhuG27UQ1yIEQgB7b52cPkzTjIQqxii+K0pwdCpKvA LTu/VF/JzD+HHmmruI1o2GVIRcKelg5PKPVdzsB2Cn0tiDhEt4ko/60M96lDWX9w36zp SU480GRLmkVkzzSKcqxSaKS88qZpy1o47CFxyY7ruziqLXFrP1vtpg+CXjPUuLWitp5F q0FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753864119; x=1754468919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lOXsofV7d5Y1QpSZQsIBgp8cuSodqQc2mblmLGbM94w=; b=PJSeVIwucZ30awmjc73jWzTAzA3gi27Lbbh5L7aGjKZET7h8PFdxLRN0ytkz8jjliq DZgW2ecDI6Ap9ygxgDK2Wc0IjvIOdouJiBUG8unXkpTtekTl2SssUDcwqhBucMK6gXTb 0z1s4ZtgxxQ5A06YcjKnCX0GLHvhXlE/h+NIuQ4WBZqu55MXnrc4vHZUCZYBAVpyzmzV ynQugY97lWtOolQqSLUm4PWjOybsL1P60nnekUKRllbkA0i7FgyLhrMvOu5NUcH105T2 RZ9jup8IpmU83IWIy1Ybn6pN7FYaoKMfEhXGoWiBtrF9cpYRFR6esE0RyH8Ug+L2lac3 4xzA== X-Forwarded-Encrypted: i=1; AJvYcCVmqRdLAE/i6Ch6tIXkOvmH5iOK4jEwZOe0e5JE1wr3ilkexWrAriuDlUEs+TxbCq/c9cHiTlJSK5qi25c=@vger.kernel.org X-Gm-Message-State: AOJu0YynSNJ4PR8aKgrV3xsY+ZJ1lOXDUpb7ZJKoWpMDjTt2qoebYXCZ Qi/MwyWXoJ3HXYs1cXSXImushGztG33JlqzGRxNzPsf2nMHc0XfSED1SkuEEcHUAeiZ3REnp9sS eATK9 X-Gm-Gg: ASbGncvWBjQ2CLVLxOJMVTGjgIsS1V+vtU/JW73m3CiBW9VXQK/3wvjr9q13VmdNhou QKKUUtrwmVuRNGCTW7wptsAGzCgUR9EMdUU4MZSnmyYVUhwI2sPlA6I10rLBORS9MJKz/bXGsIv 7aowV/mRDvdmYmRnvWzG3POKY97ZMzfu9dkdHfeXCw09hDJnXeDE4Fhw/UgXtQGfCEfZLi2soC0 GCFZW0jJ502u+uaiJPuCbCYXAwo69yKsptHlWg+Ffa5y+CZZCEnwQRkOGe+TNXuuOh/cehvDOAX tVKYto5pE/PMJNbAj6NB5ZHgoAzxB2xdJZn6on59kf602hUdcyg8Mm+Eo+uwZnjZtj7MzCBRDgQ 2+B9zqV5gHEGfPWeFvfh86OoMODNxAnxebhnEXnBY2D6KbITQ X-Google-Smtp-Source: AGHT+IHG9XCbSyvpKyHbL5s8I4UboMc3w6ID76nF1eFUwqG6ZVjNwX0+7ei9BR6ifR6BGxa85cRvvw== X-Received: by 2002:a05:600c:1382:b0:455:f7b8:235c with SMTP id 5b1f17b1804b1-4589b00a4eamr8677265e9.14.1753864119339; Wed, 30 Jul 2025 01:28:39 -0700 (PDT) Received: from mai.. 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:38 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 20/20] clocksource/drivers/nxp-pit: Add NXP Automotive s32g2 / s32g3 support Date: Wed, 30 Jul 2025 10:27:22 +0200 Message-ID: <20250730082725.183133-21-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The previous changes put in place the encapsulation of the code in order to allow multiple instances of the driver. The S32G platform has two Periodic Interrupt Timer (PIT). The IP is exactly the same as the VF platform. Each PIT has four channels which are 32 bits wide and counting down. The two first channels can be chained to implement a 64 bits counter. The channel usage is kept unchanged with the original driver, channel 2 is used as a clocksource, channel 3 is used as a clockevent. Other channels are unused. In order to support the S32G platform which has two PIT, we initialize the timer and bind it to a CPU. The S32G platforms can have 2, 4 or 8 CPUs and this kind of configuration can appear unusual as we may endup with two PIT used as a clockevent for the two first CPUs while the other CPUs use the architected timers. However, in the context of the automotive, the platform can be partioned to assign 2 CPUs for Linux and the others CPUs to third party OS. The PIT is then used with their specifities like the ability to freeze the time which is needed for instance for debugging purpose. The setup found for this platform is each timer instance is bound to CPU0 and CPU1. A counter is incremented when a timer is successfully initialized and assigned to a CPU. This counter is used as an index for the CPU number and to detect when we reach the maximum possible instances for the platform. That in turn triggers the CPU hotplug callbacks to achieve the per CPU setup. It is the exact same mechanism found in the NXP STM driver. If the timers must be bound to different CPUs, it would require an additionnal mechanism which is not part of these changes. Tested on a s32g274a-rdb2. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-nxp-pit.c | 115 +++++++++++++++++++++++----- 1 file changed, 97 insertions(+), 18 deletions(-) diff --git a/drivers/clocksource/timer-nxp-pit.c b/drivers/clocksource/time= r-nxp-pit.c index 2a0ee4109ead..f2534172b9d4 100644 --- a/drivers/clocksource/timer-nxp-pit.c +++ b/drivers/clocksource/timer-nxp-pit.c @@ -1,14 +1,16 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012-2013 Freescale Semiconductor, Inc. + * Copyright 2018,2021-2025 NXP */ - #include #include +#include #include #include #include #include +#include =20 /* * Each pit takes 0x10 Bytes register space @@ -37,11 +39,23 @@ struct pit_timer { void __iomem *clksrc_base; void __iomem *clkevt_base; - unsigned long cycle_per_jiffy; struct clock_event_device ced; struct clocksource cs; + int rate; +}; + +struct pit_timer_data { + int max_pit_instances; }; =20 +static DEFINE_PER_CPU(struct pit_timer *, pit_timers); + +/* + * Global structure for multiple PITs initialization + */ +static int pit_instances; +static int max_pit_instances =3D 1; + static void __iomem *sched_clock_base; =20 static inline struct pit_timer *ced_to_pit(struct clock_event_device *ced) @@ -98,8 +112,8 @@ static u64 pit_timer_clocksource_read(struct clocksource= *cs) return (u64)~readl(PITCVAL(pit->clksrc_base)); } =20 -static int __init pit_clocksource_init(struct pit_timer *pit, const char *= name, - void __iomem *base, unsigned long rate) +static int pit_clocksource_init(struct pit_timer *pit, const char *name, + void __iomem *base, unsigned long rate) { /* * The channels 0 and 1 can be chained to build a 64-bit @@ -155,7 +169,7 @@ static int pit_set_periodic(struct clock_event_device *= ced) { struct pit_timer *pit =3D ced_to_pit(ced); =20 - pit_set_next_event(pit->cycle_per_jiffy, ced); + pit_set_next_event(pit->rate / HZ, ced); =20 return 0; } @@ -181,24 +195,28 @@ static irqreturn_t pit_timer_interrupt(int irq, void = *dev_id) return IRQ_HANDLED; } =20 -static int __init pit_clockevent_init(struct pit_timer *pit, const char *n= ame, - void __iomem *base, unsigned long rate, - int irq, unsigned int cpu) +static int pit_clockevent_per_cpu_init(struct pit_timer *pit, const char *= name, + void __iomem *base, unsigned long rate, + int irq, unsigned int cpu) { + int ret; + /* * The channels 0 and 1 can be chained to build a 64-bit * timer. Let's use the channel 3 as a clockevent and leave * the channels 0 and 1 unused for anyone else who needs them */ pit->clkevt_base =3D base + PIT_CH(3); - pit->cycle_per_jiffy =3D rate / (HZ); + pit->rate =3D rate; =20 pit_timer_disable(pit->clkevt_base); =20 pit_timer_irqack(pit); =20 - BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - name, &pit->ced)); + ret =3D request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_NOBALANCI= NG, + name, &pit->ced); + if (ret) + return ret; =20 pit->ced.cpumask =3D cpumask_of(cpu); pit->ced.irq =3D irq; @@ -210,6 +228,23 @@ static int __init pit_clockevent_init(struct pit_timer= *pit, const char *name, pit->ced.set_next_event =3D pit_set_next_event; pit->ced.rating =3D 300; =20 + per_cpu(pit_timers, cpu) =3D pit; + + return 0; +} + +static int pit_clockevent_starting_cpu(unsigned int cpu) +{ + struct pit_timer *pit =3D per_cpu(pit_timers, cpu); + int ret; + + if (!pit) + return 0; + + ret =3D irq_force_affinity(pit->ced.irq, cpumask_of(cpu)); + if (ret) + return ret; + /* * The value for the LDVAL register trigger is calculated as: * LDVAL trigger =3D (period / clock period) - 1 @@ -218,12 +253,12 @@ static int __init pit_clockevent_init(struct pit_time= r *pit, const char *name, * LDVAL trigger value is 1. And then the min_delta is * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit. */ - clockevents_config_and_register(&pit->ced, rate, 2, 0xffffffff); + clockevents_config_and_register(&pit->ced, pit->rate, 2, 0xffffffff); =20 return 0; } =20 -static int __init pit_timer_init(struct device_node *np) +static int pit_timer_init(struct device_node *np) { struct pit_timer *pit; struct clk *pit_clk; @@ -262,16 +297,31 @@ static int __init pit_timer_init(struct device_node *= np) =20 clk_rate =3D clk_get_rate(pit_clk); =20 - /* enable the pit module */ - pit_module_enable(timer_base); + pit_module_disable(timer_base); =20 ret =3D pit_clocksource_init(pit, name, timer_base, clk_rate); - if (ret) + if (ret) { + pr_err("Failed to initialize clocksource '%pOF'\n", np); goto out_pit_module_disable; + } =20 - ret =3D pit_clockevent_init(pit, name, timer_base, clk_rate, irq, 0); - if (ret) + ret =3D pit_clockevent_per_cpu_init(pit, name, timer_base, clk_rate, irq,= pit_instances); + if (ret) { + pr_err("Failed to initialize clockevent '%pOF'\n", np); goto out_pit_clocksource_unregister; + } + + /* enable the pit module */ + pit_module_enable(timer_base); + + pit_instances++; + + if (pit_instances =3D=3D max_pit_instances) { + ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "PIT timer:starting", + pit_clockevent_starting_cpu, NULL); + if (ret < 0) + goto out_pit_clocksource_unregister; + } =20 return 0; =20 @@ -289,4 +339,33 @@ static int __init pit_timer_init(struct device_node *n= p) =20 return ret; } + +static int pit_timer_probe(struct platform_device *pdev) +{ + const struct pit_timer_data *pit_timer_data; + + pit_timer_data =3D of_device_get_match_data(&pdev->dev); + if (pit_timer_data) + max_pit_instances =3D pit_timer_data->max_pit_instances; + + return pit_timer_init(pdev->dev.of_node); +} + +static struct pit_timer_data s32g2_data =3D { .max_pit_instances =3D 2 }; + +static const struct of_device_id pit_timer_of_match[] =3D { + { .compatible =3D "nxp,s32g2-pit", .data =3D &s32g2_data }, + { } +}; +MODULE_DEVICE_TABLE(of, pit_timer_of_match); + +static struct platform_driver nxp_pit_driver =3D { + .driver =3D { + .name =3D "nxp-pit", + .of_match_table =3D pit_timer_of_match, + }, + .probe =3D pit_timer_probe, +}; +module_platform_driver(nxp_pit_driver); + TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init); --=20 2.43.0