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charset="utf-8" Enable Multi-Circular Queue (MCQ) support for the UFS host controller on the Qualcomm SM8650 platform by updating the device tree node. This includes adding new register regions and specifying the MSI parent required for MCQ operation. MCQ is a modern queuing model for UFS that improves performance and scalability by allowing multiple hardware queues.=20 Changes: - Add reg entries for mcq_sqd and mcq_vs regions. - Define reg-names for the new regions. - Specify msi-parent for interrupt routing. Signed-off-by: Ram Kumar Dwivedi --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index e14d3d778b71..5d164fe511ba 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3982,7 +3982,12 @@ ufs_mem_phy: phy@1d80000 { =20 ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0 0x01d84000 0 0x3000>; + reg =3D <0 0x01d84000 0 0x3000>, + <0 0x01da5000 0 0x2000>, + <0 0x01da4000 0 0x0010>; + reg-names =3D "ufs_mem", + "mcq_sqd", + "mcq_vs"; =20 interrupts =3D ; =20 @@ -4020,6 +4025,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 iommus =3D <&apps_smmu 0x60 0>; =20 + msi-parent =3D <&gic_its 0x60>; + lanes-per-direction =3D <2>; qcom,ice =3D <&ice>; =20 --=20 2.50.1