From nobody Sun Oct 5 20:02:13 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9A1F2512DE; Wed, 30 Jul 2025 08:23:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753863797; cv=none; b=Gwd/WMMJAszoGWczdaVWboL6Z2gtA5z8s51dayxuq2+3Pu0st4svzIQ4IR665LyexgM2Xr08zqim7Kz13y+IKch8CTttxJxSS9o2i4jlWm6NsmVzkM6Mc9h5oasYV2NvOi+6mmIWcnIOOn/iPXl7F3VyteowEj9VndASJa7yf4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753863797; c=relaxed/simple; bh=DzpfPF/m57Evw/TLSB/8MYKARqnZY5P0zmOOuitde8k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S92eNuNbeBSuIF4kMWTQ2QjjkguDiys40NjjnqMez1lzXmjWympdkVYH0/I7PAXVrrvWPCOhFZ9etJgpgHV/hmZyyR/VNIsYCzG9fSp+ySt1OcXe3Kx0eeQ/8YXyLMMVOcZF4NLhAiWKao/haZykJAOeBPyPPh9gO6fpSm5gR9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=jZqDHrnB; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jZqDHrnB" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56U5efjx031251; Wed, 30 Jul 2025 08:22:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pQNGzDEK6eKty96rgcVMx9btsxD5fTyZGxvZiaEgtp8=; b=jZqDHrnB4+rfGYcG UQWaOH1a9ghkz40r9nNSVB4y/OIhfIng0nhWO+keiGf6N0T8XCXAgEFLBlV4TI5H NIUzkv/xUh4fqoSgsPws2EgtEfd+w4EtP2KoTHMBH8jhkMJQqDtyoB/Ib98MnCA/ lI40HspDHx6gdYc29mLSh2fZc8DVeiat8VbjUY0nqit4U7yJrNm+WEM9sFKa/w67 A+VdkiEBaEI+MqonQESFrCeKpzEdoyhAIOnTiz/6f8djWRXjSaveV8k2vx3naLUB lPNCFhfYH7ZFN+QBDQ8iAdeYGI8HBcb3YI0G1OskRz3wRoV1KGSiemF285p7mnB7 9lBdYA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 485v1xgdbs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Jul 2025 08:22:57 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56U8MuSI021004 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Jul 2025 08:22:56 GMT Received: from hu-rdwivedi-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 30 Jul 2025 01:22:52 -0700 From: Ram Kumar Dwivedi To: , , , , , , , , , CC: , , , Subject: [PATCH V1 1/3] dt-bindings: ufs: qcom: Add reg and reg-names Date: Wed, 30 Jul 2025 13:52:27 +0530 Message-ID: <20250730082229.23475-2-quic_rdwivedi@quicinc.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> References: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMwMDA1NyBTYWx0ZWRfX2pFJsAHhWqjB GIcRVRTaZx0Z7ZJxzdisl2UCk5m5cjMlwJrrivrmJQSwJFn5ShCpAQcStjn6X4sxQ6nHsxNBtKL JYf+FQX6KxFsSKX9h7rAMhMmjsvLL8mqbFjl05xpXMHcFYpV51Nkx70WWq2au58xWSIDKetggNv AQBBrAsG/mceyMV3TsA4E/1sgknZGVs2rUDb8htKZLqlxdUXcyECu+vGvqUfYIwm5waHdl34VEH 3JPfQdt7AFSiOlUkn6Owx4ctlyBtjSWiddmGKH9avUIGOOrtwCXsNwBLmkn9PcTPSy6rMe+TX6C aPbKu5/F9cbwUu9KXMVmGMxFI2/4hsRK2wcHTxNVlg4ZHlIaQldUekzADVPkXE+CL4oSjfNIZ/i 6g2a2QFu1ApB+PZ1mmrFO2BUdUmvdRbnKsR9nvCPXseSpm0TZP2inVcVf91cbio/luf4j3Wn X-Authority-Analysis: v=2.4 cv=JKw7s9Kb c=1 sm=1 tr=0 ts=6889d661 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=uVvpafz-p1P7gohKaXoA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: CHKQQ8VSPPtUhH__fgUwvrq44j-Kf9Gd X-Proofpoint-GUID: CHKQQ8VSPPtUhH__fgUwvrq44j-Kf9Gd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-30_03,2025-07-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 priorityscore=1501 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 clxscore=1015 mlxlogscore=941 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507300057 Content-Type: text/plain; charset="utf-8" Update the Qualcomm UFS device tree bindings to support Multi-Circular Queue (MCQ) operation. This includes increasing the maximum number of register entries from 2 to 3 and extending the accepted values for reg-names to include "mcq_sqd" and "mcq_vs". These changes are required to enable MCQ support via Device Tree for platforms such as SM8650 and SM8750. Signed-off-by: Ram Kumar Dwivedi Tested-by: Neil Armstrong # on SM8650-QRD --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index 6c6043d9809e..de263118b552 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -86,12 +86,17 @@ properties: =20 reg: minItems: 1 - maxItems: 2 + maxItems: 3 =20 reg-names: - items: - - const: std - - const: ice + oneOf: + - items: + - const: std + - const: ice + - items: + - const: ufs_mem + - const: mcq_sqd + - const: mcq_vs =20 required-opps: maxItems: 1 @@ -177,9 +182,9 @@ allOf: - const: rx_lane1_sync_clk reg: minItems: 1 - maxItems: 1 + maxItems: 3 reg-names: - maxItems: 1 + maxItems: 3 =20 - if: properties: @@ -280,7 +285,7 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 3 clocks: minItems: 7 maxItems: 8 @@ -288,7 +293,7 @@ allOf: properties: reg: minItems: 1 - maxItems: 2 + maxItems: 3 clocks: minItems: 7 maxItems: 9 --=20 2.50.1 From nobody Sun Oct 5 20:02:13 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FCDC25DB1A; Wed, 30 Jul 2025 08:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753863801; cv=none; b=gD6xK5XPEtgdOW7G2Qal19aj4iOQiPMlsxOMXsrre+ko/MItwQIxNoztn+OwNfqEhbx3J7cj+Ng2gTHtJd8X34r/aBAkMRG/oTgF/+nTUBcFMGCWV3/MYYov4alu1fqaa8G/dDD8HQ1aMoVzw16Vxs1M3AQwdEQUtY5pF7c1JXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753863801; c=relaxed/simple; bh=l9ra1GKKdn6FbpirqvAnIMKAjTCuGHCIgwqsyoKF8bc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fj2reXqQf9HzNZms0Ftshr72nis2/LsskbwOexXGntbjFhz5aY04BI7NZeBNPrZ5VDFkxbwlVxE8mZRvoU+7mv2VkG9p8FIifNJ5UjjnXuSZaGKHOmoiRIrVltk9U9pIaDyg895Zs4DEK6xQdToNk3edRZKJwzrBcJx0zGaOC2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ipXgmDEz; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ipXgmDEz" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56U5Z2dE018853; Wed, 30 Jul 2025 08:23:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kywzoxGdItysJuKRdt2PipJB0NrYcZcf7+7OciUQHXE=; b=ipXgmDEzYRx1BzXt WCSiroe7w8WBJW22xmyUABXOQaZfMTSmSpUVqD0gKaiooFX6I1yKo8kywag0iRj5 hkaV3X7aMJsrNPaWhPu/jQj0S3E4+5vL6Z/mLUHOfWH+F4z3hU80bgq77uNMwKMg NhtJJ8YU9K7Z3174hOyHYT5bPNoFAeIDy1nJjBCEWocGndFOp/3HMWBdhp5YRShw w7zic+khohbo5aZq7EHREf1k46w+34rEI8U+i0Z623Jt5oJFZ4Hp4Au6/N2jShVa 1jPLGdqWrkkRcn9Tz+zOWidRYsQY5aqEQcolrQe8p/5Tmv60snqBjOIoXhhdUL8Y HeotQw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 484q8634hr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Jul 2025 08:23:01 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56U8N09b003151 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Jul 2025 08:23:00 GMT Received: from hu-rdwivedi-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 30 Jul 2025 01:22:56 -0700 From: Ram Kumar Dwivedi To: , , , , , , , , , CC: , , , Subject: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Enable MCQ support for UFS controller Date: Wed, 30 Jul 2025 13:52:28 +0530 Message-ID: <20250730082229.23475-3-quic_rdwivedi@quicinc.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> References: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMwMDA1NyBTYWx0ZWRfX12V5ochnhlH6 5nD4FVvYh4kRZ+WKgnuhv+QxVDhb6crL/t/etitQHKVEMKRYTQMPBnLrYJBHozHGbjPFJ2qxYhH aVjHn16Alta5nuzlJ2Nmlk93Ekzn0RHAwl4PdPMJ9pXQ42l7SAOVhda5JMOKcm6QZpuSpKs8XVv n523ZQHJcbz874UI4r8l+qbPPn3dfyFTpPDf/JP+5axjgDE3nIpn5mRP24Gx3+XB9DMyOPQZRLP YmposTOdpblz3pAg1WDWFMP5N8mZ83umJsfJHZi+JImoaS88q+H8dm4AzKBxZmCeXqBSv102Zkd KJ+hfpAHXhsRIZ7pdqbaizTJZrG88mmfGiNceyZfpWOy5ET1WlofFS9P+7OKAszBlWP+TU16pT4 yJhRQaUbzt9TODv7fWHO3IPlSNdMhYs6uaAIxQfLpHTMbOovxQRNHi1ONLP12XpLcrDFXRKL X-Authority-Analysis: v=2.4 cv=TqLmhCXh c=1 sm=1 tr=0 ts=6889d665 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=YFqID79JUgxNR6UwwXUA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: s31nA5Ix-elAvPW8FRBVK_h307gtTsLS X-Proofpoint-GUID: s31nA5Ix-elAvPW8FRBVK_h307gtTsLS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-30_03,2025-07-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxlogscore=971 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507300057 Content-Type: text/plain; charset="utf-8" Enable Multi-Circular Queue (MCQ) support for the UFS host controller on the Qualcomm SM8650 platform by updating the device tree node. This includes adding new register regions and specifying the MSI parent required for MCQ operation. MCQ is a modern queuing model for UFS that improves performance and scalability by allowing multiple hardware queues.=20 Changes: - Add reg entries for mcq_sqd and mcq_vs regions. - Define reg-names for the new regions. - Specify msi-parent for interrupt routing. Signed-off-by: Ram Kumar Dwivedi Tested-by: Neil Armstrong # on SM8650-QRD --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index e14d3d778b71..5d164fe511ba 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3982,7 +3982,12 @@ ufs_mem_phy: phy@1d80000 { =20 ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0 0x01d84000 0 0x3000>; + reg =3D <0 0x01d84000 0 0x3000>, + <0 0x01da5000 0 0x2000>, + <0 0x01da4000 0 0x0010>; + reg-names =3D "ufs_mem", + "mcq_sqd", + "mcq_vs"; =20 interrupts =3D ; =20 @@ -4020,6 +4025,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 iommus =3D <&apps_smmu 0x60 0>; =20 + msi-parent =3D <&gic_its 0x60>; + lanes-per-direction =3D <2>; qcom,ice =3D <&ice>; =20 --=20 2.50.1 From nobody Sun Oct 5 20:02:13 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 234F92512D7; Wed, 30 Jul 2025 08:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753863796; cv=none; b=vA0SwYXvQIO7lcV163bvW0pFEeZR80lfogyb+96pZxvD9bO/xPtdspxCsAGL1w+mAWbbNVdPAef09JsB+V11eFWJH2MiYlYkbLrnlFSE10BRcR165SEvJlQMH9zb7r6TiQbFkkL/t3rBRteUuw9OhnlpvIj43OSYYZ4fxGXvnM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753863796; c=relaxed/simple; bh=iIADWUHyZLwNebj8AZ9Vn0BrPX5WX6yaZsYValg9rsE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FIxZfeWDhBFwbDVY5Xf0E9cj7c0FfaD5rgkK3zpDe+9reGMFtI7+u55Nn7dkwxqdzeE7Pz/QAo7vMQycuSXAGtOFbzU907hwgOYiPv6RdTPxAK6rOWiCGseF/g+6GdEya5O3Vwf/qyv121OQERumckEFxv8Wy8CHv1Ybg1RP834= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=kCsQKrbZ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kCsQKrbZ" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56U4l3at014609; Wed, 30 Jul 2025 08:23:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9MvI1nk60WdoG2bc7QtALmUwBFVl0IUg6QvjINNa64Q=; b=kCsQKrbZ+RaaeXK+ uZa4OPB47hJcg5SPUeN087XgL2twuJqN2IyTqxXzURuSrnpGFur1A3Et53lSDCu7 uNEjpfV3yquuMkz8Vyjuda8aDo+b4Gw3/k+o3hzWuDPOjOzh+5lUAmQPa5ZO6PYD uh4NLSdI1AzjqAWOl9LuFXADsbTj4+fpfKIxarerbk8tv4t3UPFe6Q5FWfKtfAmI WGhUVxXMNGNWiInAL968sMJdNErD/gmEvQ1vHGpbYw1GZv9b3F3loyXPKhJXgpRV PmhJvJ8H4zTrp41wRh3gmMWFM+U/7yBNa9duk8BteUhJsVpD2qS5VggXss8cOHLa tzz8gw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 484q3xtx8p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Jul 2025 08:23:06 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56U8N5V4008534 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Jul 2025 08:23:05 GMT Received: from hu-rdwivedi-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 30 Jul 2025 01:23:01 -0700 From: Ram Kumar Dwivedi To: , , , , , , , , , CC: , , , Subject: [PATCH V1 3/3] arm64: dts: qcom: sm8750: Enable MCQ support for UFS controller Date: Wed, 30 Jul 2025 13:52:29 +0530 Message-ID: <20250730082229.23475-4-quic_rdwivedi@quicinc.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> References: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=JovxrN4C c=1 sm=1 tr=0 ts=6889d66a cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=Jh_ldMv1e_q4xxFTlQwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: HIBHNy8Aenk1oD5M7SAzZTHCS-RjvrJ_ X-Proofpoint-GUID: HIBHNy8Aenk1oD5M7SAzZTHCS-RjvrJ_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMwMDA1NCBTYWx0ZWRfXzycjsQAx4mGM 1cCEpT36793yYNXh4UZfleky1hL+F0DJSScmX8ocyScij/pk6SS4EZsJtXdmpdnMOe13jiSYXf8 FfIe356+qI7dPadAdwycN8eSOD/Ey7szGzLmSgqh+ho3VcdzHvoqSFNXV8ipxT8E5duNlx+xqS4 KB9EGDf0NouGm0mITVrjBOIQzQjOIXwU8bNWhLeI3Qb8YmKZQE5Slckxt3jaUL4P5RpV6LjqGsm Z1jOeqb4V5Ofxjby5vGjBCwSrcMEEmSVzqm9Yt4aUDuSyCVTLo+eV2zS0onPHCLJrxRgftyD8tu 7i8AnwAysJmeCxckfW7CimcZLkZTRgNQmNHLoCYQ35yD5nwZPHf7mmwtIT7CtOEy4r66HihxB9m XFPRPvN9S/faXOvHr56SCdTKLlM/jzOR62DsT3HXolCJdHsC45EUhTr2q6AF2a8h4+LtjJRw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-30_03,2025-07-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507300054 Content-Type: text/plain; charset="utf-8" From: Palash Kambar Enable Multi-Circular Queue (MCQ) support for the UFS host controller on the Qualcomm SM8750 platform by updating the device tree node. This includes adding new register regions and specifying the MSI parent required for MCQ operation. MCQ is a modern queuing model for UFS that improves performance and scalability by allowing multiple hardware queues. Although MCQ support has existed in the UFS driver for several years, this patch enables it via Device Tree for SM8750. Changes: - Add reg entries for mcq_sqd and mcq_vs regions. - Define reg-names for the new regions. - Specify msi-parent for interrupt routing. Signed-off-by: Palash Kambar Tested-by: Neil Armstrong # on SM8650-QRD --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 4643705021c6..401e510ee738 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3329,7 +3329,12 @@ ufs_mem_phy: phy@1d80000 { =20 ufs_mem_hc: ufs@1d84000 { compatible =3D "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0x0 0x01d84000 0x0 0x3000>; + reg =3D <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x1da5000 0x0 0x2000>, + <0x0 0x1da4000 0x0 0x10>; + reg-names =3D "ufs_mem", + "mcq_sqd", + "mcq_vs"; =20 interrupts =3D ; =20 @@ -3363,11 +3368,12 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "cpu-ufs"; =20 power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; =20 iommus =3D <&apps_smmu 0x60 0>; dma-coherent; - + msi-parent =3D <&gic_its 0x60>; lanes-per-direction =3D <2>; =20 phys =3D <&ufs_mem_phy>; --=20 2.50.1