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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-458953eaed4sm14783835e9.27.2025.07.30.00.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 00:42:57 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label Date: Wed, 30 Jul 2025 10:42:49 +0300 Message-ID: <20250730074253.1884111-2-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> References: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The '2' in 'hsi2c23' was missed while making the device tree. Fix that so we can properly reference the node. Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi b/arch/arm6= 4/boot/dts/exynos/exynos2200-pinctrl.dtsi index f618ff290..5877da7ba 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi @@ -1438,7 +1438,7 @@ i3c11_bus: i3c11-bus-pins { samsung,pin-drv =3D ; }; =20 - hsi223_bus: hsi2c23-bus-pins { + hsi2c23_bus: hsi2c23-bus-pins { samsung,pins =3D "gpp11-2", "gpp11-3"; samsung,pin-function =3D ; samsung,pin-pud =3D ; --=20 2.43.0 From nobody Sun Oct 5 20:10:33 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F187B290D81; Wed, 30 Jul 2025 07:43:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753861382; cv=none; b=GngHG5kGARzA321kFlXKmsrfBEm4AMm8+1kyKX+dPkuP2gGsSCwBMaMOhiGuWUyg7pT3DgVATtCt2YXRJvo4gx6mtL1eytsdUX1uQwfMbkCKXO/vdn73w9gzZQ6qoioWeNwBuBsVeprkeRqZ+LJNhpnSkRlOR55qEKJKsyHZYJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753861382; c=relaxed/simple; bh=O2pOeoVNeNdh4HRXZlK8yXIwnjFusw+7V/Sbd5h3ZWc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HVg9w0tbtY+OvqiYxuqsJfayM3/CcbD5sbiED+cv3XpxbOliHERMLYuj/uPjLkryUw9wo4eWxjl780Beu8bvYgT5WzZTCNMhBM9LTFo8HM+AVlRbEvJ+MBHHYc5Af9Kps4xXP1otBZb9vo5k8AAaIt5GoSVxNRr/iTjIN3e0ybQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=njA8b+uW; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="njA8b+uW" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-3b786421e36so337967f8f.3; Wed, 30 Jul 2025 00:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1753861379; x=1754466179; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p0hLEz604jvcXEN/T2mEEGr6WT4Oxp/78DXXL0VyUnc=; b=njA8b+uWvAObn3gM2D++ftCxv+XG2dnFtGoknDtjp+kptT2JS6KS25ukUvjkW8Iah2 ZJUmmuunut866GUn/8c2SZ55O4ExYXcmCE/aq7mojMGrfHNgz49HJjq7NfNZ6xJ+aYdq oKV1/FjodqRSTXXHQpOWZZTs+v+/f0NsFf4V0p5U5Agl3NKNHNrgdmFV//GY2p3T2FJP Ane5KQZHg22vPXboaF/6NEuAgKyMhJ0RRdd+nvNXmjI5LeNGIEYnre+RLf0dSwSUqbAO 4TPFAQF/V8g3g7PPViMvbTvz+jZGSVy/vJPY7k2kEkjfXu2lIWpxV5WhhAK4oojpNqmt wUig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753861379; x=1754466179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p0hLEz604jvcXEN/T2mEEGr6WT4Oxp/78DXXL0VyUnc=; b=IIQQIWy1g6oztTyl+pIZOzDG9ujGBG1uJ4RXhYKIc+FgYbSP42JFOe4UNUtiffvpxl luolTTa4Itq8dQYXq+K4iahh2gr9v8Rldv9ZOnPAUKyXkkmNZwlc+yUA1Q1d73zX4qP4 GL2P+gw+HZVmxjHifgKcwu2nx7ww3AopyGkEjfQm/zz9jQrghboUauVAHiz222xQT9nH s7oB9ZSAkPNrjrhhEINomzkcit8QBZwKs/LpgKryRiTvDWC03pHkhD7k0BC3C/pMzh0n wpdmAu/OdWHenT+NJw3dVn0j06mLnKk6ifSQS//ZS5MEXQdqDBql3Tt89yixNPsOjJmv 3xJA== X-Forwarded-Encrypted: i=1; AJvYcCXeCnap+vbTpZ8pmfbD88b6Lg2jIrSHbFAejvg3gc9G11B9ukkZvYe3UgEe1r/7hKYS3JKfUA/mDRITaxp1@vger.kernel.org, AJvYcCXr1yVvpRdQGYRPcA7y4xYRasZjOEMvCcme9CWPa+17ixKG1+JD/ORMSgvOETM1n+VTbnb7CuE1tYkM@vger.kernel.org X-Gm-Message-State: AOJu0Yz0ZKmiS3yz6JRez7ruVG8Fa096KGc5J9raTrEZWfuZNsUuVhBp E3zJO/xfUVcnZ4e7Yc/zA+ZDxi7/eD7UOf7+AlGNNy2z3YpkSY75UWYBwdXmVw== X-Gm-Gg: ASbGnctM/7Pte/5VtjjKft9MAx8CzHEIh092y+X5ebkK82uU4CTbKO+YkJCNGukqFmi cVTlNhJZe6f5YUG/crrbatRLI8WSBieabwM9980yW5vhfU8Ap/zFV6zzbRkO3b+g8FN2VNuCNfs pRcrkdyVrchYTrICvl6wOf1f3L/KqiGJb364ycdQHm33ixlUz6LrZ1/lynTwQEmF+Gdqvm08vEH AW7/L94yjKgtP7yQDnHjyidYUvBZQhshmcgmLHEDFVmVAZGuOc1j8YAI7uvphZnYWJJ+75uh58K jkz8w2JLQK+SdSHqm/m1CE5EyQ/yBC+VBjGTkDalCqqLeVxrJqeUjLcZG6UNWDkQF5U0DTy9HK8 I5LJ7jSdH6X9jq8aKg/+GA1dYMkCemm2jqVQ1ZoU7blPEN1ZbGqX6SwDo2tWn78GQcGTcOp1MNQ == X-Google-Smtp-Source: AGHT+IGhFmO4oF6kD0Ko40MEOLP56KuDL+105SXE8A6OwScEL3wiW4/hCwb6fHK70dZK1plOzP/mqg== X-Received: by 2002:a05:6000:2008:b0:3b7:8fcc:a1e3 with SMTP id ffacd0b85a97d-3b795032797mr1716620f8f.48.1753861379038; Wed, 30 Jul 2025 00:42:59 -0700 (PDT) Received: from ivaylo-T580.. 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-458953eaed4sm14783835e9.27.2025.07.30.00.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 00:42:58 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] arm64: dts: exynos2200: use 32-bit address space for /soc Date: Wed, 30 Jul 2025 10:42:50 +0300 Message-ID: <20250730074253.1884111-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> References: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All peripherals on this SoC are mapped under the 32-bit address space (0x0 -> 0x20000000), so enforce that. Suggested-by: Sam Protsenko Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- This was suggested at [1]. [1] https://lore.kernel.org/all/CAPLW+4kPN65uX0tyG_F-4u5FQpPnwX9y6F1zrobq5U= yVbks+-w@mail.gmail.com --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 72 +++++++++++----------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index 6b5ac02d0..943e83851 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -221,22 +221,22 @@ psci { method =3D "smc"; }; =20 - soc { + soc@0 { compatible =3D "simple-bus"; - ranges; + ranges =3D <0x0 0x0 0x0 0x20000000>; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; =20 chipid@10000000 { compatible =3D "samsung,exynos2200-chipid", "samsung,exynos850-chipid"; - reg =3D <0x0 0x10000000 0x0 0x24>; + reg =3D <0x10000000 0x24>; }; =20 cmu_peris: clock-controller@10020000 { compatible =3D "samsung,exynos2200-cmu-peris"; - reg =3D <0x0 0x10020000 0x0 0x8000>; + reg =3D <0x10020000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&cmu_top CLK_DOUT_TCXO_DIV3>, @@ -250,7 +250,7 @@ cmu_peris: clock-controller@10020000 { mct_peris: timer@10040000 { compatible =3D "samsung,exynos2200-mct-peris", "samsung,exynos4210-mct"; - reg =3D <0x0 0x10040000 0x0 0x800>; + reg =3D <0x10040000 0x800>; clocks =3D <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GI= C>; clock-names =3D "fin_pll", "mct"; interrupts =3D , @@ -270,8 +270,8 @@ mct_peris: timer@10040000 { =20 gic: interrupt-controller@10200000 { compatible =3D "arm,gic-v3"; - reg =3D <0x0 0x10200000 0x0 0x10000>, /* GICD */ - <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */ + reg =3D <0x10200000 0x10000>, /* GICD */ + <0x10240000 0x200000>; /* GICR * 8 */ =20 #interrupt-cells =3D <4>; interrupt-controller; @@ -294,7 +294,7 @@ ppi_cluster2: interrupt-partition-2 { =20 cmu_peric0: clock-controller@10400000 { compatible =3D "samsung,exynos2200-cmu-peric0"; - reg =3D <0x0 0x10400000 0x0 0x8000>; + reg =3D <0x10400000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -306,17 +306,17 @@ cmu_peric0: clock-controller@10400000 { =20 syscon_peric0: syscon@10420000 { compatible =3D "samsung,exynos2200-peric0-sysreg", "syscon"; - reg =3D <0x0 0x10420000 0x0 0x2000>; + reg =3D <0x10420000 0x2000>; }; =20 pinctrl_peric0: pinctrl@10430000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x10430000 0x0 0x1000>; + reg =3D <0x10430000 0x1000>; }; =20 cmu_peric1: clock-controller@10700000 { compatible =3D "samsung,exynos2200-cmu-peric1"; - reg =3D <0x0 0x10700000 0x0 0x8000>; + reg =3D <0x10700000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -328,23 +328,23 @@ cmu_peric1: clock-controller@10700000 { =20 syscon_peric1: syscon@10720000 { compatible =3D "samsung,exynos2200-peric1-sysreg", "syscon"; - reg =3D <0x0 0x10720000 0x0 0x2000>; + reg =3D <0x10720000 0x2000>; }; =20 pinctrl_peric1: pinctrl@10730000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x10730000 0x0 0x1000>; + reg =3D <0x10730000 0x1000>; }; =20 cmu_hsi0: clock-controller@10a00000 { compatible =3D "samsung,exynos2200-cmu-hsi0"; - reg =3D <0x0 0x10a00000 0x0 0x8000>; + reg =3D <0x10a00000 0x8000>; #clock-cells =3D <1>; }; =20 usb32drd: phy@10aa0000 { compatible =3D "samsung,exynos2200-usb32drd-phy"; - reg =3D <0x0 0x10aa0000 0x0 0x10000>; + reg =3D <0x10aa0000 0x10000>; =20 clocks =3D <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names =3D "phy"; @@ -360,7 +360,7 @@ usb32drd: phy@10aa0000 { =20 usb_hsphy: phy@10ab0000 { compatible =3D "samsung,exynos2200-eusb2-phy"; - reg =3D <0x0 0x10ab0000 0x0 0x10000>; + reg =3D <0x10ab0000 0x10000>; =20 clocks =3D <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>, <&cmu_hsi0 CLK_MOUT_HSI0_NOC>, @@ -374,7 +374,7 @@ usb_hsphy: phy@10ab0000 { =20 usb: usb@10b00000 { compatible =3D "samsung,exynos2200-dwusb3"; - ranges =3D <0x0 0x0 0x10b00000 0x10000>; + ranges =3D <0x0 0x10b00000 0x10000>; =20 clocks =3D <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names =3D "link_aclk"; @@ -406,7 +406,7 @@ usb_dwc3: usb@0 { =20 cmu_ufs: clock-controller@11000000 { compatible =3D "samsung,exynos2200-cmu-ufs"; - reg =3D <0x0 0x11000000 0x0 0x8000>; + reg =3D <0x11000000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -418,27 +418,27 @@ cmu_ufs: clock-controller@11000000 { =20 syscon_ufs: syscon@11020000 { compatible =3D "samsung,exynos2200-ufs-sysreg", "syscon"; - reg =3D <0x0 0x11020000 0x0 0x2000>; + reg =3D <0x11020000 0x2000>; }; =20 pinctrl_ufs: pinctrl@11040000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11040000 0x0 0x1000>; + reg =3D <0x11040000 0x1000>; }; =20 pinctrl_hsi1ufs: pinctrl@11060000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11060000 0x0 0x1000>; + reg =3D <0x11060000 0x1000>; }; =20 pinctrl_hsi1: pinctrl@11240000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11240000 0x0 0x1000>; + reg =3D <0x11240000 0x1000>; }; =20 cmu_peric2: clock-controller@11c00000 { compatible =3D "samsung,exynos2200-cmu-peric2"; - reg =3D <0x0 0x11c00000 0x0 0x8000>; + reg =3D <0x11c00000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -450,17 +450,17 @@ cmu_peric2: clock-controller@11c00000 { =20 syscon_peric2: syscon@11c20000 { compatible =3D "samsung,exynos2200-peric2-sysreg", "syscon"; - reg =3D <0x0 0x11c20000 0x0 0x4000>; + reg =3D <0x11c20000 0x4000>; }; =20 pinctrl_peric2: pinctrl@11c30000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11c30000 0x0 0x1000>; + reg =3D <0x11c30000 0x1000>; }; =20 cmu_cmgp: clock-controller@14e00000 { compatible =3D "samsung,exynos2200-cmu-cmgp"; - reg =3D <0x0 0x14e00000 0x0 0x8000>; + reg =3D <0x14e00000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -471,12 +471,12 @@ cmu_cmgp: clock-controller@14e00000 { =20 syscon_cmgp: syscon@14e20000 { compatible =3D "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg =3D <0x0 0x14e20000 0x0 0x2000>; + reg =3D <0x14e20000 0x2000>; }; =20 pinctrl_cmgp: pinctrl@14e30000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x14e30000 0x0 0x1000>; + reg =3D <0x14e30000 0x1000>; =20 wakeup-interrupt-controller { compatible =3D "samsung,exynos2200-wakeup-eint", @@ -487,7 +487,7 @@ wakeup-interrupt-controller { =20 cmu_vts: clock-controller@15300000 { compatible =3D "samsung,exynos2200-cmu-vts"; - reg =3D <0x0 0x15300000 0x0 0x8000>; + reg =3D <0x15300000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -497,12 +497,12 @@ cmu_vts: clock-controller@15300000 { =20 pinctrl_vts: pinctrl@15320000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x15320000 0x0 0x1000>; + reg =3D <0x15320000 0x1000>; }; =20 cmu_alive: clock-controller@15800000 { compatible =3D "samsung,exynos2200-cmu-alive"; - reg =3D <0x0 0x15800000 0x0 0x8000>; + reg =3D <0x15800000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -512,7 +512,7 @@ cmu_alive: clock-controller@15800000 { =20 pinctrl_alive: pinctrl@15850000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x15850000 0x0 0x1000>; + reg =3D <0x15850000 0x1000>; =20 wakeup-interrupt-controller { compatible =3D "samsung,exynos2200-wakeup-eint", @@ -524,7 +524,7 @@ wakeup-interrupt-controller { pmu_system_controller: system-controller@15860000 { compatible =3D "samsung,exynos2200-pmu", "samsung,exynos7-pmu", "syscon"; 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-458953eaed4sm14783835e9.27.2025.07.30.00.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 00:42:59 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes Date: Wed, 30 Jul 2025 10:42:51 +0300 Message-ID: <20250730074253.1884111-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> References: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some USI instances have swconfig offsets that reside over the currently defined syscon ranges for peric1 and cmgp. Increase their sizes. Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index 943e83851..bab77b442 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 { =20 syscon_peric1: syscon@10720000 { compatible =3D "samsung,exynos2200-peric1-sysreg", "syscon"; - reg =3D <0x10720000 0x2000>; + reg =3D <0x10720000 0x3000>; }; =20 pinctrl_peric1: pinctrl@10730000 { @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 { =20 syscon_cmgp: syscon@14e20000 { compatible =3D "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg =3D <0x14e20000 0x2000>; + reg =3D <0x14e20000 0x3000>; }; =20 pinctrl_cmgp: pinctrl@14e30000 { --=20 2.43.0 From nobody Sun Oct 5 20:10:33 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C996291C1B; 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-458953eaed4sm14783835e9.27.2025.07.30.00.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 00:43:01 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes Date: Wed, 30 Jul 2025 10:42:52 +0300 Message-ID: <20250730074253.1884111-5-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> References: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which allows using them. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index bab77b442..22c6da907 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -336,6 +336,19 @@ pinctrl_peric1: pinctrl@10730000 { reg =3D <0x10730000 0x1000>; }; =20 + serial_1: serial@10840000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10840000 0x100>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_UART_BT>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart1_bus>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + cmu_hsi0: clock-controller@10a00000 { compatible =3D "samsung,exynos2200-cmu-hsi0"; reg =3D <0x10a00000 0x8000>; @@ -458,6 +471,19 @@ pinctrl_peric2: pinctrl@11c30000 { reg =3D <0x11c30000 0x1000>; }; =20 + serial_0: serial@11c40000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11c40000 0x100>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart0_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + cmu_cmgp: clock-controller@14e00000 { compatible =3D "samsung,exynos2200-cmu-cmgp"; reg =3D <0x14e00000 0x8000>; --=20 2.43.0 From nobody Sun Oct 5 20:10:33 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96625292936; Wed, 30 Jul 2025 07:43:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-458953eaed4sm14783835e9.27.2025.07.30.00.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 00:43:02 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes Date: Wed, 30 Jul 2025 10:42:53 +0300 Message-ID: <20250730074253.1884111-6-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> References: <20250730074253.1884111-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Universal Serial Interface (USI) supports three types of serial interfaces - uart, i2c and spi. Each protocol can work independently and configured using external configuration inputs. As each USI instance has access to 4 pins, there are multiple possible configurations: - the first 2 and the last 2 pins can be i2c (sda/scl) or uart (rx/tx) - the 4 pins can be used for 4 pin uart or spi Such configuration can be achieved by setting the mode property of usiX and usiX_i2c nodes correctly - if usiX is set to take up 2 pins, then usiX_i2c can be set to take the other 2. If usiX is set for 4 pins, then usiX_i2c should be left disabled. Define all the USI nodes from peric0 (usi4), peric1 (usi7-10), peric2 (usi0-6, usi11) and cmgp (usi0-6_cmgp, 2 pin usi7_cmgp) blocks, as well as their respective uart and i2c subnodes. As Samsung, for some reason, has decided to restart the counting of usi instances for cmgp, suffix labels for nodes of such with _cmgp. Spi support will be added later on. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1361 ++++++++++++++++++++ 1 file changed, 1361 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index 22c6da907..f83e6cf24 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include =20 / { compatible =3D "samsung,exynos2200"; @@ -314,6 +315,76 @@ pinctrl_peric0: pinctrl@10430000 { reg =3D <0x10430000 0x1000>; }; =20 + usi4: usi@105000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x105000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric0 0x1024>; + status =3D "disabled"; + + hsi2c_8: i2c@10500000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10500000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric0 CLK_DOUT_PERIC0_USI04>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c8_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_6: serial@10500000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10500000 0xc0>; + clocks =3D <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart6_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi4_i2c: usi@105100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x105100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric0 0x1024>; + status =3D "disabled"; + + hsi2c_9: i2c@10510000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10510000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric0 CLK_DOUT_PERIC0_I2C>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c9_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + cmu_peric1: clock-controller@10700000 { compatible =3D "samsung,exynos2200-cmu-peric1"; reg =3D <0x10700000 0x8000>; @@ -349,6 +420,287 @@ serial_1: serial@10840000 { status =3D "disabled"; }; =20 + usi7: usi@109000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2030>; + status =3D "disabled"; + + hsi2c_14: i2c@10900000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10900000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI07>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c14_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_9: serial@10900000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10900000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart9_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi7_i2c: usi@109100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x2034>; + status =3D "disabled"; + + hsi2c_15: i2c@10910000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10910000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c15_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi8: usi@109200c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109200c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2038>; + status =3D "disabled"; + + hsi2c_16: i2c@10920000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10920000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI08>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c16_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_10: serial@10920000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10920000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart10_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi8_i2c: usi@109300c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109300c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x203c>; + status =3D "disabled"; + + hsi2c_17: i2c@10930000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10930000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c17_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi9: usi@109400c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109400c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2040>; + status =3D "disabled"; + + hsi2c_18: i2c@10940000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10940000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI09>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c18_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_11: serial@10940000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10940000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart11_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi9_i2c: usi@109500c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109500c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x2044>; + status =3D "disabled"; + + hsi2c_19: i2c@10950000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10950000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c19_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi10: usi@109600c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109600c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2048>; + status =3D "disabled"; + + hsi2c_20: i2c@10960000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10960000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI10>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c20_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_12: serial@10960000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10960000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart12_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi10_i2c: usi@109700c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109700c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x204c>; + status =3D "disabled"; + + hsi2c_21: i2c@10970000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10970000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c21_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + }; + cmu_hsi0: clock-controller@10a00000 { compatible =3D "samsung,exynos2200-cmu-hsi0"; reg =3D <0x10a00000 0x8000>; @@ -484,6 +836,496 @@ serial_0: serial@11c40000 { status =3D "disabled"; }; =20 + usi0: usi@11d000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2000>; + status =3D "disabled"; + + hsi2c_0: i2c@11d00000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d00000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI00>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c0_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_2: serial@11d00000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d00000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart2_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi0_i2c: usi@11d100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x2004>; + status =3D "disabled"; + + hsi2c_1: i2c@11d10000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d10000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c1_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi1: usi@11d200c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d200c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2008>; + status =3D "disabled"; + + hsi2c_2: i2c@11d20000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d20000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI01>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c2_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_3: serial@11d20000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d20000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart3_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi1_i2c: usi@11d300c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d300c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x200c>; + status =3D "disabled"; + + hsi2c_3: i2c@11d30000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d30000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c3_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi2: usi@11d400c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d400c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2010>; + status =3D "disabled"; + + hsi2c_4: i2c@11d40000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d40000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI02>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c4_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_4: serial@11d40000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d40000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart4_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + }; + + usi2_i2c: usi@11d500c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d500c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x2014>; + status =3D "disabled"; + + hsi2c_5: i2c@11d50000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d50000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c5_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi3: usi@11d600c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d600c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2018>; + status =3D "disabled"; + + hsi2c_6: i2c@11d60000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d60000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI03>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c6_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_5: serial@11d60000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d60000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart5_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + }; + + usi3_i2c: usi@11d700c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d700c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x201c>; + status =3D "disabled"; + + hsi2c_7: i2c@11d70000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d70000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c7_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi5_i2c: usi@11d800c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d800c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x102c>; + status =3D "disabled"; + + hsi2c_11: i2c@11d80000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d80000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c11_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi6_i2c: usi@11d900c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d900c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x1004>; + status =3D "disabled"; + + hsi2c_13: i2c@11d90000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d90000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c13_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi11: usi@11da00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11da00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x1058>; + status =3D "disabled"; + + hsi2c_22: i2c@11da0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11da0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI11>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c22_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_13: serial@11da0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11da0000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart13_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi11_i2c: usi@11db00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11db00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x105c>; + status =3D "disabled"; + + hsi2c_23: i2c@11db0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11db0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c23_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi5: usi@11dd00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11dd00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x117c>; + status =3D "disabled"; + + hsi2c_10: i2c@11dd0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11dd0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI05>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c10_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_7: serial@11dd0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11dd0000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart7_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + }; + + usi6: usi@11de00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11de00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x1180>; + status =3D "disabled"; + + hsi2c_12: i2c@11de0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11de0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI06>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c12_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_8: serial@11de0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11de0000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart8_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + cmu_cmgp: clock-controller@14e00000 { compatible =3D "samsung,exynos2200-cmu-cmgp"; reg =3D <0x14e00000 0x8000>; @@ -511,6 +1353,525 @@ wakeup-interrupt-controller { }; }; =20 + usi0_cmgp: usi@14f000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2000>; + status =3D "disabled"; + + hsi2c_24: i2c@14f00000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f00000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c24_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_14: serial@14f00000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f00000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart14_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi0_i2c_cmgp: usi@14f100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2070>; + status =3D "disabled"; + + hsi2c_25: i2c@14f10000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f10000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c25_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi1_cmgp: usi@14f200c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f200c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2010>; + status =3D "disabled"; + + hsi2c_26: i2c@14f20000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f20000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c26_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_15: serial@14f20000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f20000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart15_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi1_i2c_cmgp: usi@14f300c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f300c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2074>; + status =3D "disabled"; + + hsi2c_27: i2c@14f30000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f30000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c27_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi2_cmgp: usi@14f400c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f400c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2020>; + status =3D "disabled"; + + hsi2c_28: i2c@14f40000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f40000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI2>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c28_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_16: serial@14f40000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f40000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart16_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi2_i2c_cmgp: usi@14f500c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f500c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2024>; + status =3D "disabled"; + + hsi2c_29: i2c@14f50000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f50000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c29_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi3_cmgp: usi@14f600c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f600c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2030>; + status =3D "disabled"; + + hsi2c_30: i2c@14f60000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f60000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI3>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c30_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_17: serial@14f60000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f60000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart17_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi3_i2c_cmgp: usi@14f700c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f700c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2034>; + status =3D "disabled"; + + hsi2c_31: i2c@14f70000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f70000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c31_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi4_cmgp: usi@14f800c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f800c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2040>; + status =3D "disabled"; + + hsi2c_32: i2c@14f80000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f80000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI4>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c32_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_18: serial@14f80000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f80000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart18_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi4_i2c_cmgp: usi@14f900c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f900c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2044>; + status =3D "disabled"; + + hsi2c_33: i2c@14f90000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f90000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c33_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi5_cmgp: usi@14fa00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fa00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2050>; + status =3D "disabled"; + + hsi2c_34: i2c@14fa0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fa0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI5>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c34_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_19: serial@14fa0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14fa0000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart19_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi5_i2c_cmgp: usi@14fb00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fb00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2054>; + status =3D "disabled"; + + hsi2c_35: i2c@14fb0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fb0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c35_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi6_cmgp: usi@14fc00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fc00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2060>; + status =3D "disabled"; + + hsi2c_36: i2c@14fc0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fc0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI6>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c36_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_20: serial@14fc0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14fc0000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart20_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi6_i2c_cmgp: usi@14fd00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fd00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2064>; + status =3D "disabled"; + + hsi2c_37: i2c@14fd0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fd0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c37_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi7_i2c_cmgp: usi@14fe00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fe00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2080>; + status =3D "disabled"; + + hsi2c_38: i2c@14fe0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fe0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c38_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + cmu_vts: clock-controller@15300000 { compatible =3D "samsung,exynos2200-cmu-vts"; reg =3D <0x15300000 0x8000>; --=20 2.43.0