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Wed, 30 Jul 2025 04:47:06 -0700 (PDT) From: Abel Vesa Date: Wed, 30 Jul 2025 14:46:48 +0300 Subject: [PATCH 1/3] dt-bindings: phy: qcom-edp: Add missing clock for X Elite Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-phy-qcom-edp-add-missing-refclk-v1-1-6f78afeadbcf@linaro.org> References: <20250730-phy-qcom-edp-add-missing-refclk-v1-0-6f78afeadbcf@linaro.org> In-Reply-To: <20250730-phy-qcom-edp-add-missing-refclk-v1-0-6f78afeadbcf@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Dmitry Baryshkov , Konrad Dybcio , Sibi Sankar , Rajendra Nayak Cc: Johan Hovold , Taniya Das , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , stable@vger.kernel.org X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE On X Elite platform, the eDP PHY uses one more clock called refclk. Add it to the schema. Cc: stable@vger.kernel.org # v6.10 Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatib= les") Signed-off-by: Abel Vesa --- .../devicetree/bindings/phy/qcom,edp-phy.yaml | 23 ++++++++++++++++++= +++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 293fb6a9b1c330438bceba15226c91e392c840fb..2e594b2ea81d385118684bf58da= 3440c88ca32b9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -32,12 +32,14 @@ properties: - description: PLL register block =20 clocks: - maxItems: 2 + minItems: 2 + maxItems: 3 =20 clock-names: items: - const: aux - const: cfg_ahb + - const: refclk =20 "#clock-cells": const: 1 @@ -59,6 +61,25 @@ required: - "#clock-cells" - "#phy-cells" =20 +allOf: + - if: + properties: + compatible: + enum: + - qcom,x1e80100-dp-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + additionalProperties: false =20 examples: --=20 2.34.1 From nobody Sun Oct 5 20:17:13 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C83F296163 for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE On X Elite, the DP PHY needs another clock called refclk. Rework the match data to allow passing different number of clocks and add the refclk to the X1E80100 config data. Cc: stable@vger.kernel.org # v6.10 Fixes: db83c107dc29 ("phy: qcom: edp: Add v6 specific ops and X1E80100 plat= form support") Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 43 +++++++++++++++++++++++++++++++--= ---- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index f1b51018683d51df064f60440864c6031638670c..785de5bc6d1a8b11bd4cb87d8fa= 52dc2baa56646 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -85,6 +85,8 @@ struct qcom_edp_phy_cfg { const u8 *aux_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; + const char * const *clks; + int num_clks; }; =20 struct qcom_edp { @@ -103,9 +105,11 @@ struct qcom_edp { =20 struct phy_configure_opts_dp dp_opts; =20 - struct clk_bulk_data clks[2]; struct regulator_bulk_data supplies[2]; =20 + struct clk_bulk_data *clks; + int num_clks; + bool is_edp; }; =20 @@ -218,7 +222,7 @@ static int qcom_edp_phy_init(struct phy *phy) if (ret) return ret; =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); + ret =3D clk_bulk_prepare_enable(edp->num_clks, edp->clks); if (ret) goto out_disable_supplies; =20 @@ -524,6 +528,10 @@ static int qcom_edp_com_configure_pll_v4(const struct = qcom_edp *edp) return 0; } =20 +static const char * const qcom_edp_clks_v4[] =3D { + "aux", "cfg_ahb", +}; + static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D { .com_power_on =3D qcom_edp_phy_power_on_v4, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, @@ -537,17 +545,23 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_c= fg =3D { .aux_cfg =3D edp_phy_aux_cfg_v5, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, .ver_ops =3D &qcom_edp_phy_ops_v4, + .clks =3D qcom_edp_clks_v4, + .num_clks =3D ARRAY_SIZE(qcom_edp_clks_v4), }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, + .clks =3D qcom_edp_clks_v4, + .num_clks =3D ARRAY_SIZE(qcom_edp_clks_v4), }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, + .clks =3D qcom_edp_clks_v4, + .num_clks =3D ARRAY_SIZE(qcom_edp_clks_v4), }; =20 static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { @@ -555,6 +569,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_c= fg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, + .clks =3D qcom_edp_clks_v4, + .num_clks =3D ARRAY_SIZE(qcom_edp_clks_v4), }; =20 static int qcom_edp_phy_power_on_v6(const struct qcom_edp *edp) @@ -730,10 +746,16 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = =3D { .com_configure_ssc =3D qcom_edp_com_configure_ssc_v6, }; =20 +static const char * const qcom_edp_clks_v6[] =3D { + "aux", "cfg_ahb", "refclk", +}; + static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, + .clks =3D qcom_edp_clks_v6, + .num_clks =3D ARRAY_SIZE(qcom_edp_clks_v6), }; =20 static int qcom_edp_phy_power_on(struct phy *phy) @@ -885,7 +907,7 @@ static int qcom_edp_phy_exit(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); =20 - clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks); + clk_bulk_disable_unprepare(edp->num_clks, edp->clks); regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); =20 return 0; @@ -1066,7 +1088,7 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) struct phy_provider *phy_provider; struct device *dev =3D &pdev->dev; struct qcom_edp *edp; - int ret; + int ret, i; =20 edp =3D devm_kzalloc(dev, sizeof(*edp), GFP_KERNEL); if (!edp) @@ -1092,9 +1114,16 @@ static int qcom_edp_phy_probe(struct platform_device= *pdev) if (IS_ERR(edp->pll)) return PTR_ERR(edp->pll); =20 - edp->clks[0].id =3D "aux"; - edp->clks[1].id =3D "cfg_ahb"; - ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); + edp->clks =3D devm_kcalloc(dev, edp->cfg->num_clks, sizeof(*edp->clks), G= FP_KERNEL); + if (IS_ERR(edp->clks)) + return PTR_ERR(edp->clks); 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The eDP PHY on X1E80100 needs the refclk which is provided by the TCSR CC. So add it to the PHY. Cc: stable@vger.kernel.org # v6.9 Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 5e9a8fa3cf96468b12775f91192cbd779d5ce946..6cc0c85191fdd0563e62e08d505= 90d546387b827 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5655,9 +5655,11 @@ mdss_dp3_phy: phy@aec5a00 { <0 0x0aec5000 0 0x1c8>; =20 clocks =3D <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "refclk"; =20 power-domains =3D <&rpmhpd RPMHPD_MX>; =20 --=20 2.34.1