From nobody Sun Oct 5 19:59:31 2025 Received: from mslow3.mail.gandi.net (mslow3.mail.gandi.net [217.70.178.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F30D92DECBF; Wed, 30 Jul 2025 17:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.178.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753897818; cv=none; b=oJd2ZDcvv0SwplSTOt8EBwb2ptRfMNgWFAj0r8Sj8JWZ0niOwYGt8SHh8QHmyyOP9Mb84Pzlhs5/d9OQsLQ67A6UrT+d657tdYd3Vmf4EZT9kjk4tT20lF2og3IEaTxw7sMINx5drlcWHMjRfruQEZkUIVEPkcEiJpblBpXvt68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753897818; c=relaxed/simple; bh=u/DBPrrXi1YUBX587wY3HEnl0jSOb8wEheVaHESnVqk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QK3kVApRqrqUg7nfm0uvFoNeI5cvLcZR0nQsOfJVfogqyUIKkhvirM0qO2NOILWH+2lNSqXdaIqpiyt5FurN+uPubJ+CC4eEFrm27KvGUTgcL3BSWkL6I4q8Vg6ivvMwzhXfEiM6OQbeFXkHFGd10CK+U5YfG3qD6d1k+Kteav4= ARC-Authentication-Results: i=1; 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bh=Kp/er0tAcwSGh4h0rLep0cfDaCG3r32BhF8cj5ZTgVk=; b=Jyl9vUZJ4ufUq1ms4UZ/7fOnDkbDMxSZhF3bF8bgP0IY+3gWu5ROhf7v96XzIsQxFlePLO uRLVQ0YctxEXbu8CMbFOm8VhEDWrHGNRcZ+4yQQ4tosRmF/yPKYvyNZ9vABFwPCY43lgAm nk2zLRmMOVq7WvXWpJAJu8Eygu3/Ua6tYjeMYiKAcXB4SM1KYoVbEWg02EK/w+XQSJGHPh VirFa0cl1GYVP/Kgx3zUsvWlN7d/9aaa9xLUy+1tblitRXTAiqQRPbGkccRpTjINMbg3+3 /yreuk97z2R5Cgu5hsAQxlFN305sUYhVXdQWtVbkHe9+THgfbfoZ/K3RqKmBQg== From: Louis Chauvet Date: Wed, 30 Jul 2025 19:02:44 +0200 Subject: [PATCH 1/4] dt-bindings: display: ti,am65x-dss: Add clk property for data edge synchronization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-fix-edge-handling-v1-1-1bdfb3fe7922@bootlin.com> References: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> In-Reply-To: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sam Ravnborg , Benoit Parrot , Lee Jones , Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: thomas.petazzoni@bootlin.com, Jyri Sarha , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Louis Chauvet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=8B7104AE9A272D6693F527F2EC1883F55E0B40A5 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdelkeegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephfffufggtgfgkfhfjgfvvefosehtjeertdertdejnecuhfhrohhmpefnohhuihhsucevhhgruhhvvghtuceolhhouhhishdrtghhrghuvhgvthessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhephedtjedttdetieeigfeljeekteetvefhudekgeelffejheegieevhfegudffvddvnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopegludelvddrudeikedrtddrvddtngdpmhgrihhlfhhrohhmpehlohhuihhsrdgthhgruhhvvghtsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopedvhedprhgtphhtthhopehjhihrihdrshgrrhhhrgesihhkihdrfhhipdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhriihkodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhrihhsthhosehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrihhrlhhivggusehgmhgrihhlrdgtohhmpdhrtghpthhtoheps hhimhhonhgrsehffhiflhhlrdgthhdprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehnmhesthhirdgtohhm The dt-bindings for the display, specifically ti,am65x-dss, need to include a clock property for data edge synchronization. The current implementation does not correctly apply the data edge sampling property. To address this, synchronization of writes to two different registers is required: one in the TIDSS IP (which is already described in the tidss node) and one is in the Memory Mapped Control Register Modules (added by the previous commit). As the Memory Mapped Control Register Modules is located in a different IP, we need to use a phandle to write values in its registers. Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Signed-off-by: Louis Chauvet --- Cc: stable@vger.kernel.org --- Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 361e9cae6896c1f4d7fa1ec47a6e3a73bca2b102..b9a373b569170332f671416eb7b= bc0c83f7b5ea6 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -133,6 +133,12 @@ properties: and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI interface to work. =20 + ti,clk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to syscon device node mapping CFG0_CLK_CTRL registers. + This property is needed for proper data sampling edge. + max-memory-bandwidth: $ref: /schemas/types.yaml#/definitions/uint32 description: --=20 2.50.1