From nobody Sun Oct 5 18:15:12 2025 Received: from mslow3.mail.gandi.net (mslow3.mail.gandi.net [217.70.178.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F30D92DECBF; Wed, 30 Jul 2025 17:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.178.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753897818; cv=none; b=oJd2ZDcvv0SwplSTOt8EBwb2ptRfMNgWFAj0r8Sj8JWZ0niOwYGt8SHh8QHmyyOP9Mb84Pzlhs5/d9OQsLQ67A6UrT+d657tdYd3Vmf4EZT9kjk4tT20lF2og3IEaTxw7sMINx5drlcWHMjRfruQEZkUIVEPkcEiJpblBpXvt68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753897818; c=relaxed/simple; bh=u/DBPrrXi1YUBX587wY3HEnl0jSOb8wEheVaHESnVqk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QK3kVApRqrqUg7nfm0uvFoNeI5cvLcZR0nQsOfJVfogqyUIKkhvirM0qO2NOILWH+2lNSqXdaIqpiyt5FurN+uPubJ+CC4eEFrm27KvGUTgcL3BSWkL6I4q8Vg6ivvMwzhXfEiM6OQbeFXkHFGd10CK+U5YfG3qD6d1k+Kteav4= ARC-Authentication-Results: i=1; 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bh=Kp/er0tAcwSGh4h0rLep0cfDaCG3r32BhF8cj5ZTgVk=; b=Jyl9vUZJ4ufUq1ms4UZ/7fOnDkbDMxSZhF3bF8bgP0IY+3gWu5ROhf7v96XzIsQxFlePLO uRLVQ0YctxEXbu8CMbFOm8VhEDWrHGNRcZ+4yQQ4tosRmF/yPKYvyNZ9vABFwPCY43lgAm nk2zLRmMOVq7WvXWpJAJu8Eygu3/Ua6tYjeMYiKAcXB4SM1KYoVbEWg02EK/w+XQSJGHPh VirFa0cl1GYVP/Kgx3zUsvWlN7d/9aaa9xLUy+1tblitRXTAiqQRPbGkccRpTjINMbg3+3 /yreuk97z2R5Cgu5hsAQxlFN305sUYhVXdQWtVbkHe9+THgfbfoZ/K3RqKmBQg== From: Louis Chauvet Date: Wed, 30 Jul 2025 19:02:44 +0200 Subject: [PATCH 1/4] dt-bindings: display: ti,am65x-dss: Add clk property for data edge synchronization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-fix-edge-handling-v1-1-1bdfb3fe7922@bootlin.com> References: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> In-Reply-To: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sam Ravnborg , Benoit Parrot , Lee Jones , Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: thomas.petazzoni@bootlin.com, Jyri Sarha , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Louis Chauvet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=8B7104AE9A272D6693F527F2EC1883F55E0B40A5 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdelkeegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephfffufggtgfgkfhfjgfvvefosehtjeertdertdejnecuhfhrohhmpefnohhuihhsucevhhgruhhvvghtuceolhhouhhishdrtghhrghuvhgvthessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhephedtjedttdetieeigfeljeekteetvefhudekgeelffejheegieevhfegudffvddvnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopegludelvddrudeikedrtddrvddtngdpmhgrihhlfhhrohhmpehlohhuihhsrdgthhgruhhvvghtsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopedvhedprhgtphhtthhopehjhihrihdrshgrrhhhrgesihhkihdrfhhipdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhriihkodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhrihhsthhosehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrihhrlhhivggusehgmhgrihhlrdgtohhmpdhrtghpthhtoheps hhimhhonhgrsehffhiflhhlrdgthhdprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehnmhesthhirdgtohhm The dt-bindings for the display, specifically ti,am65x-dss, need to include a clock property for data edge synchronization. The current implementation does not correctly apply the data edge sampling property. To address this, synchronization of writes to two different registers is required: one in the TIDSS IP (which is already described in the tidss node) and one is in the Memory Mapped Control Register Modules (added by the previous commit). As the Memory Mapped Control Register Modules is located in a different IP, we need to use a phandle to write values in its registers. Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Signed-off-by: Louis Chauvet --- Cc: stable@vger.kernel.org --- Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 361e9cae6896c1f4d7fa1ec47a6e3a73bca2b102..b9a373b569170332f671416eb7b= bc0c83f7b5ea6 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -133,6 +133,12 @@ properties: and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI interface to work. =20 + ti,clk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to syscon device node mapping CFG0_CLK_CTRL registers. + This property is needed for proper data sampling edge. + max-memory-bandwidth: $ref: /schemas/types.yaml#/definitions/uint32 description: --=20 2.50.1 From nobody Sun Oct 5 18:15:12 2025 Received: from mslow3.mail.gandi.net (mslow3.mail.gandi.net [217.70.178.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 979142DECBF; Wed, 30 Jul 2025 17:50:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.178.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753897826; cv=none; b=kaTQqnB0DIuRUWPakNPMGSbXNsitfAVDsYp6hzswq2gwkzUeFcOgyG39J+cRbVMvaEfGX4iPLhMuIWyLulofY5HqE01UbJQs7wZcsRNuH6wB7bCtlIZ1crmw/TA9B2gRT6ZGvaaXNjzgU5TNq5Js4aqrnJt4PRm3s6nOU5e8PM0= ARC-Message-Signature: i=1; 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Wed, 30 Jul 2025 17:03:02 +0000 (UTC) Received: by mail.gandi.net (Postfix) with ESMTPSA id BE0E6442A6; Wed, 30 Jul 2025 17:02:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1753894975; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N+xY4UZr8LvAM8jYcOJRM8hzadDR3NumATbc214IapM=; b=QrZJunuzAe9A32IXdLxegg+gs4exspfjaG6mJNmOBcAId+g/COu7BRFQUYml/7aUdlElg/ 5k019XhQbOTZakt5FNPO68V8akrtj04+biWh8SQvGRQOUPgDMvbHD1fZGBeDz45Ixctlsk PKwvSnyHqcNG+NyrMVm1mbF9njC7cm5l8roFPbJn8DbfXqYTzQnVn3fcQrGVEc3jgAx4ky IT/9gKcgJqkt3+pS6TkO9nGSvJ7Q1GVdhsQLbL5V0C1FC8QqHDFaROVS3yvIFS+eiG2b2O 0vu2hi2xpPqRJ/GWLNBCQS1sF2qLKQ3rptTpHoRghTgJcYyXvh4I/3CBVu3rUQ== From: Louis Chauvet Date: Wed, 30 Jul 2025 19:02:45 +0200 Subject: [PATCH 2/4] dt-bindings: mfd: syscon: Add ti,am625-dss-clk-ctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-fix-edge-handling-v1-2-1bdfb3fe7922@bootlin.com> References: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> In-Reply-To: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sam Ravnborg , Benoit Parrot , Lee Jones , Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: thomas.petazzoni@bootlin.com, Jyri Sarha , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Louis Chauvet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1779; i=louis.chauvet@bootlin.com; h=from:subject:message-id; bh=+vQmzWOpJ3o7m/vAWofAcDWRydefU96Ll29wNpFlYIo=; b=owEBbQKS/ZANAwAIASCtLsZbECziAcsmYgBoilA3M4ea0dmIilicR6aW0qGwK4i4ICkosRsvt d60pygWKgmJAjMEAAEIAB0WIQRPj7g/vng8MQxQWQQgrS7GWxAs4gUCaIpQNwAKCRAgrS7GWxAs 4upxD/9zxSfXLrFH5tI+71ohX67Q17YO5UDoErAp8zVlMW9VQFTihgpw0Ulexzo5d2Hj9OgZl01 SfQPcsgnY4J6Zm3lL6584731SIlWk3xkH77d3bSotXbkLhlMcOa5GaUJlV4aHOmnGv1Q7aDbw0W TARRvPlLlGPRqAqTUJ53I7cUnbq6edBc2CzOD3D6v/NS3NqArH9Um9vVoi+DKZxvQWFt4IHnc2k 4uSQ2hl05y1oJi8uMlK2slSpysT5lwcdkj5rQ807cRw/AYXDM0Ftr3VbA+JKJj6uid/ngC9m2fY 2HqinTX07O3pojp4hoKrCWTPRnsGJldzqispnktmQClZpq93W0gbsfa/tLXwuzWcke1vqqdAatv DCsU4M1dAEHE4v3Z6Fa9ogDw/n1dxQBAZ+LuqAVVeI9NO88/cZWrPBLTXXqvdcs9B51ImzSiFeC AMnGnG8pJeBNiA0NxsDtYS+Lo6YeDMoJbRx5huwzaKtc8100GsB41vZoykPFixIdLgqWHGPukPI KGs8NJRfQQdJBfIxym3w5v2AhI5+gnjH6mXF8HPv7DT9dgJIXY/+euv8krKh5XjniHVadMeD0Fe MxwqXZ2VW3tU/gEIjYD2Ok3gvpoy+lGr/WbBOIusOZLGQtxluZHSAiL07boSFEil0LqxqNxw5Uv HkMjHdbq7Qd0qNQ== X-Developer-Key: i=louis.chauvet@bootlin.com; a=openpgp; fpr=8B7104AE9A272D6693F527F2EC1883F55E0B40A5 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdelkeegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephfffufggtgfgkfhfjgfvvefosehtjeertdertdejnecuhfhrohhmpefnohhuihhsucevhhgruhhvvghtuceolhhouhhishdrtghhrghuvhgvthessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhephedtjedttdetieeigfeljeekteetvefhudekgeelffejheegieevhfegudffvddvnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopegludelvddrudeikedrtddrvddtngdpmhgrihhlfhhrohhmpehlohhuihhsrdgthhgruhhvvghtsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopedvhedprhgtphhtthhopehjhihrihdrshgrrhhhrgesihhkihdrfhhipdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhriihkodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhrihhsthhosehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrihhrlhhivggusehgmhgrihhlrdgtohhmpdhrtghpthhtoheps hhimhhonhgrsehffhiflhhlrdgthhdprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehnmhesthhirdgtohhm The dt-bindings for the multi-function device (mfd) syscon need to include ti,am625-dss-clk-ctrl. On AM625 chips, the display controller (tidss) has external registers to control certain clock properties. These registers are located in the device configuration registers, so they need to be declared using syscon. They will later be used with a phandle in the tidss node. Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Signed-off-by: Louis Chauvet --- Cc: stable@vger.kernel.org --- Documentation/devicetree/bindings/mfd/syscon.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 27672adeb1fedb7c81b8ae86c35f4f3b26d5516f..afe4a2a19591e90c850c05ef588= 8f18bdb64eac9 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -121,6 +121,7 @@ select: - ti,am62-opp-efuse-table - ti,am62-usb-phy-ctrl - ti,am625-dss-oldi-io-ctrl + - ti,am625-dss-clk-ctrl - ti,am62p-cpsw-mac-efuse - ti,am654-dss-oldi-io-ctrl - ti,j784s4-acspcie-proxy-ctrl @@ -228,6 +229,7 @@ properties: - ti,am62-opp-efuse-table - ti,am62-usb-phy-ctrl - ti,am625-dss-oldi-io-ctrl + - ti,am625-dss-clk-ctrl - ti,am62p-cpsw-mac-efuse - ti,am654-dss-oldi-io-ctrl - ti,j784s4-acspcie-proxy-ctrl @@ -256,4 +258,3 @@ examples: compatible =3D "allwinner,sun8i-h3-system-controller", "syscon"; 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bh=VkEcz9Od8lumPLGSI2mDm7zd90f2J6ysx2IIFyeMJqI=; b=f7GHXv1lkyC5Z5PHrKkyeT6qbn/8ObZkq64MuI3kVq6v9CyV1NhYlJVFLHHtSITgx+Xlse pAtAm8R27EtjZxv5oceulWPucQ7w+ki+9KS88kW9zdAYQCbA/fG3I/oep1o+Ju4MGZQB9d moZqJVWvw5DbMycog67ggCgSpQbRgsjluKNYyiiihkDKZfIoiNTGLrlYYCOYtzqBZgewqf cZqN9Ehm9Kfo0FT5Sl5QlcnKZhli2bhXS7j9T2Q/ZcFyZNZ67LlTRZNVtbkYOJ2TpKBrcL /I+LSeg+q029Lk569x4SPkI2E6yoTWQPrKcoskHC8cfmDP30FJKcLQFaRxthDA== From: Louis Chauvet Date: Wed, 30 Jul 2025 19:02:46 +0200 Subject: [PATCH 3/4] arm64: dts: ti: k3-am62-main: Add tidss clk-ctrl property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-fix-edge-handling-v1-3-1bdfb3fe7922@bootlin.com> References: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> In-Reply-To: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sam Ravnborg , Benoit Parrot , Lee Jones , Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: thomas.petazzoni@bootlin.com, Jyri Sarha , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Louis Chauvet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=8B7104AE9A272D6693F527F2EC1883F55E0B40A5 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdelkeegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephfffufggtgfgkfhfjgfvvefosehtjeertdertdejnecuhfhrohhmpefnohhuihhsucevhhgruhhvvghtuceolhhouhhishdrtghhrghuvhgvthessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhephedtjedttdetieeigfeljeekteetvefhudekgeelffejheegieevhfegudffvddvnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopegludelvddrudeikedrtddrvddtngdpmhgrihhlfhhrohhmpehlohhuihhsrdgthhgruhhvvghtsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopedvhedprhgtphhtthhopehjhihrihdrshgrrhhhrgesihhkihdrfhhipdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhriihkodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhrihhsthhosehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrihhrlhhivggusehgmhgrihhlrdgtohhmpdhrtghpthhtoheps hhimhhonhgrsehffhiflhhlrdgthhdprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehnmhesthhirdgtohhm For am62 processors, we need to use the newly created clk-ctrl property to properly handle data edge sampling configuration. Add them in the main device tree. Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Signed-off-by: Louis Chauvet --- Cc: stable@vger.kernel.org --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 9e0b6eee9ac77d66869915b2d7bec3e2275c03ea..d3131e6da8e70fde035d3c44716= f939e8167795a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -76,6 +76,11 @@ audio_refclk1: clock-controller@82e4 { assigned-clock-parents =3D <&k3_clks 157 18>; #clock-cells =3D <0>; }; + + dss_clk_ctrl: dss_clk_ctrl@8300 { + compatible =3D "ti,am625-dss-clk-ctrl", "syscon"; + reg =3D <0x8300 0x4>; + }; }; =20 dmss: bus@48000000 { @@ -787,6 +792,7 @@ dss: dss@30200000 { <&k3_clks 186 2>; clock-names =3D "fck", "vp1", "vp2"; interrupts =3D ; + ti,clk-ctrl =3D <&dss_clk_ctrl>; status =3D "disabled"; =20 dss_ports: ports { --=20 2.50.1 From nobody Sun Oct 5 18:15:12 2025 Received: from mslow3.mail.gandi.net (mslow3.mail.gandi.net [217.70.178.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3B951E0DE8; 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b=ahu2yZS5PpM6RqG4gIA/3xnCkg4qml3y3KjQG8RWCeS0mvQ8P3OO48pA1rjRhGSrKzrK7i xxkgydLuwN02xdb5Ml6RPck3kBzCDx+pkpu5ylKcKwPORFhLh8pcpuLaYUiDiF8tg+5cAv glJgPdehk+mWn7F0mT65XneDhDEyWbo+itCG78QK53R5CMcaxIXTAdpS7ALLA6xKJWjVKA b9Qfv5dmHeIaaouIiJVme4EiM4UyXGpj+CXD4PkLcdT2bu7dHbL2zd88p7K/SzgCeMxxFo PjPaPgg+Ccs6LAfJztYZtdj7421A95gj0SUdHn9FKnjKBuFY4dZ4M0n2GyRw3A== From: Louis Chauvet Date: Wed, 30 Jul 2025 19:02:47 +0200 Subject: [PATCH 4/4] drm/tidss: Fix sampling edge configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-fix-edge-handling-v1-4-1bdfb3fe7922@bootlin.com> References: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> In-Reply-To: <20250730-fix-edge-handling-v1-0-1bdfb3fe7922@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sam Ravnborg , Benoit Parrot , Lee Jones , Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: thomas.petazzoni@bootlin.com, Jyri Sarha , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Louis Chauvet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=8B7104AE9A272D6693F527F2EC1883F55E0B40A5 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdelkeegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephfffufggtgfgkfhfjgfvvefosehtjeertdertdejnecuhfhrohhmpefnohhuihhsucevhhgruhhvvghtuceolhhouhhishdrtghhrghuvhgvthessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhephedtjedttdetieeigfeljeekteetvefhudekgeelffejheegieevhfegudffvddvnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopegludelvddrudeikedrtddrvddtngdpmhgrihhlfhhrohhmpehlohhuihhsrdgthhgruhhvvghtsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopedvhedprhgtphhtthhopehjhihrihdrshgrrhhhrgesihhkihdrfhhipdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhriihkodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhrihhsthhosehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrihhrlhhivggusehgmhgrihhlrdgtohhmpdhrtghpthhtoheps hhimhhonhgrsehffhiflhhlrdgthhdprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehnmhesthhirdgtohhm As stated in the AM62x Technical Reference Manual (SPRUIV7B), the data sampling edge needs to be configured in two distinct registers: one in the TIDSS IP and another in the memory-mapped control register modules. Since the latter is not within the same address range, a phandle to a syscon device is used to access the regmap. Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Signed-off-by: Louis Chauvet --- Cc: stable@vger.kernel.org --- drivers/gpu/drm/tidss/tidss_dispc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index c0277fa36425ee1f966dccecf2b69a2d01794899..65ca7629a2e75437023bf58f8a1= bddc24db5e3da 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -498,6 +498,7 @@ struct dispc_device { const struct dispc_features *feat; =20 struct clk *fclk; + struct regmap *clk_ctrl; =20 bool is_enabled; =20 @@ -1267,6 +1268,11 @@ void dispc_vp_enable(struct dispc_device *dispc, u32= hw_videoport, FLD_VAL(mode->vdisplay - 1, 27, 16)); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); + + if (dispc->clk_ctrl) { + regmap_update_bits(dispc->clk_ctrl, 0, 0x100, ipc ? 0x100 : 0x000); + regmap_update_bits(dispc->clk_ctrl, 0, 0x200, rf ? 0x200 : 0x000); + } } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) @@ -3012,6 +3018,14 @@ int dispc_init(struct tidss_device *tidss) =20 dispc_init_errata(dispc); =20 + dispc->clk_ctrl =3D syscon_regmap_lookup_by_phandle_optional(tidss->dev->= of_node, + "ti,clk-ctrl"); + if (IS_ERR(dispc->clk_ctrl)) { + r =3D dev_err_probe(dispc->dev, PTR_ERR(dispc->clk_ctrl), + "DISPC: syscon_regmap_lookup_by_phandle failed.\n"); + return r; + } + dispc->fourccs =3D devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), sizeof(*dispc->fourccs), GFP_KERNEL); if (!dispc->fourccs) --=20 2.50.1