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Wed, 30 Jul 2025 05:36:00 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 30 Jul 2025 14:35:37 +0200 Subject: [PATCH 2/2] dt-bindings: ufs: qcom: Split SC7280 and similar Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-dt-bindings-ufs-qcom-v1-2-4cec9ff202dc@linaro.org> References: <20250730-dt-bindings-ufs-qcom-v1-0-4cec9ff202dc@linaro.org> In-Reply-To: <20250730-dt-bindings-ufs-qcom-v1-0-4cec9ff202dc@linaro.org> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Kumar Dwivedi , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11790; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=boCA9V7sdFxzCI0LILmKKujCbe1eahhsFvEftXk76ec=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoihGmr6jo7Aor+3UbS6k3j6a1qWb3wcXpYEu+S T1fluxxheSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaIoRpgAKCRDBN2bmhouD 17SAEACBDvyabLZV9xW21iI3QDfAHNg47RgcHyKNjkIuhv7ybSQQxw5B+DBbI4ZAxwJzZAUdshl 7MPRQi2TIxISDnVlYJaihDuewG+yDg+oCzUDOf4Phb3vwAqr/IhNAZXOaHi3jKbrk9vzGiH25gi jIlzKZGPJaq4isRelT3qHTuED60497uQ/dEKqLeER2SUv+WuBmt0mUpsQoqUlcCzq7kzWj35uW2 H7R8LaDnc/KgY4/RyuO2EIb9rxFaP/DnLK1UXXqOO+rvmDTwbXaax8yzDWLpFDDueAaYAvtpgIl Dhb4vSG9zG7LhP60gL7+QTjow+9dv5daju1pG4G6QvpItb+1lHjvmMk2qrwaTwaJsqvB3mer1zr XYkzTOVtPjQGUytlWbneoBCjgoBS1jWUgeeot9d/OiZdGevgs7ZkD5e2pCdZHRUYU15Wx65OWwL 3uyZvMEsa6Ivxdl2dgNWjdVCe5+t1W8PFwcyDF1PpKSWNKlKtLDYMD0Z2nBwdGa3zWHT0w+5y81 JbpMhsC/U8VGeqsGSBfOAe4YbFxLh5PCKHjKZK1Kh8UjZpT4mlus/R37CM2mjN/f6TB6ELrYs0T xcFFPGBet1lxlBXc2WqOh4GQUQRWzABPoGWgMMcSvUsO7eB70356rm06XECyZbWs+tmkT4tihP2 Pxm5As5ZuT2v5Fg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The binding for Qualcomm SoC UFS controllers grew and it will grow further. Split SC7280 and several other devices which: 1. Do not reference ICE as IO address space, but as phandle, 2. Have same order of clocks. The split allows easier review and further growth with MCQ IO address space. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml | 149 +++++++++++++++++= ++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 107 +++++---------- 2 files changed, 183 insertions(+), 73 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml b= /Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0f2fe48860a7847819f325bb817= 0692a82af2ae3 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,sc7280-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 and Other SoCs UFS Controllers + +maintainers: + - Bjorn Andersson + +# Select only our matches, not all jedec,ufs-2.0 +select: + properties: + compatible: + contains: + enum: + - qcom,msm8998-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,msm8998-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + - const: qcom,ufshc + - const: jedec,ufs-2.0 + + reg: + maxItems: 1 + + reg-names: + items: + - const: std + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: rx_lane1_sync_clk + + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Inline Crypto Engine node + +required: + - compatible + - reg + +allOf: + - $ref: qcom,ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + ufs@1d84000 { + compatible =3D "qcom,sm8450-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_mem_phy_lanes>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l7b_2p5>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l9b_1p2>; + vccq-max-microamp =3D <1200000>; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + iommus =3D <&apps_smmu 0xe0 0x0>; + interconnects =3D <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_E= BI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_= UFS_MEM_CFG>; + interconnect-names =3D "ufs-ddr", "cpu-ufs"; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + qcom,ice =3D <&ice>; + }; + }; diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index fc0f7b8d1cd1c4a2168f29cffcc0c2ff660424df..b34da3df841a11eb50022fa7d09= 1ebfbb33b1d17 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -15,7 +15,16 @@ select: properties: compatible: contains: - const: qcom,ufshc + enum: + - qcom,msm8994-ufshc + - qcom,msm8996-ufshc + - qcom,qcs615-ufshc + - qcom,sc7180-ufshc + - qcom,sdm845-ufshc + - qcom,sm6115-ufshc + - qcom,sm6125-ufshc + - qcom,sm6350-ufshc + - qcom,sm8150-ufshc required: - compatible =20 @@ -25,25 +34,13 @@ properties: - enum: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - - qcom,msm8998-ufshc - qcom,qcs615-ufshc - - qcom,qcs8300-ufshc - - qcom,sa8775p-ufshc - qcom,sc7180-ufshc - - qcom,sc7280-ufshc - - qcom,sc8180x-ufshc - - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - - qcom,sm8250-ufshc - - qcom,sm8350-ufshc - - qcom,sm8450-ufshc - - qcom,sm8550-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 =20 @@ -92,44 +89,6 @@ allOf: reg-names: maxItems: 1 =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-ufshc - - qcom,qcs8300-ufshc - - qcom,sa8775p-ufshc - - qcom,sc7280-ufshc - - qcom,sc8180x-ufshc - - qcom,sc8280xp-ufshc - - qcom,sm8250-ufshc - - qcom,sm8350-ufshc - - qcom,sm8450-ufshc - - qcom,sm8550-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: core_clk - - const: bus_aggr_clk - - const: iface_clk - - const: core_clk_unipro - - const: ref_clk - - const: tx_lane0_sync_clk - - const: rx_lane0_sync_clk - - const: rx_lane1_sync_clk - reg: - minItems: 1 - maxItems: 1 - reg-names: - maxItems: 1 - - if: properties: compatible: @@ -246,10 +205,10 @@ unevaluatedProperties: false =20 examples: - | - #include + #include #include #include - #include + #include #include =20 soc { @@ -257,9 +216,12 @@ examples: #size-cells =3D <2>; =20 ufs@1d84000 { - compatible =3D "qcom,sm8450-ufshc", "qcom,ufshc", + compatible =3D "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0 0x01d84000 0 0x3000>; + reg =3D <0x0 0x01d84000 0x0 0x2500>, + <0x0 0x01d90000 0x0 0x8000>; + reg-names =3D "std", "ice"; + interrupts =3D ; phys =3D <&ufs_mem_phy_lanes>; phy-names =3D "ufsphy"; @@ -275,19 +237,8 @@ examples: vccq-max-microamp =3D <1200000>; =20 power-domains =3D <&gcc UFS_PHY_GDSC>; - iommus =3D <&apps_smmu 0xe0 0x0>; - interconnects =3D <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_E= BI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_= UFS_MEM_CFG>; - interconnect-names =3D "ufs-ddr", "cpu-ufs"; + iommus =3D <&apps_smmu 0x300 0>; =20 - clock-names =3D "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -295,15 +246,25 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz =3D <75000000 300000000>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk", + "ice_core_clk"; + freq-table-hz =3D <37500000 300000000>, <0 0>, <0 0>, - <75000000 300000000>, - <75000000 300000000>, + <37500000 300000000>, <0 0>, <0 0>, - <0 0>; - qcom,ice =3D <&ice>; + <0 0>, + <0 0>, + <0 300000000>; }; }; --=20 2.48.1