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Wed, 30 Jul 2025 05:35:57 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 30 Jul 2025 14:35:36 +0200 Subject: [PATCH 1/2] dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-dt-bindings-ufs-qcom-v1-1-4cec9ff202dc@linaro.org> References: <20250730-dt-bindings-ufs-qcom-v1-0-4cec9ff202dc@linaro.org> In-Reply-To: <20250730-dt-bindings-ufs-qcom-v1-0-4cec9ff202dc@linaro.org> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Kumar Dwivedi , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3812; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The binding for Qualcomm SoC UFS controllers grew and it will grow further. It already includes several conditionals, partially for difference in handling encryption block (ICE, either as phandle or as IO address space) but it will further grow for MCQ. Prepare for splitting this one big binding into several ones for common group of devices by defining common part for all Qualcomm UFS schemas. This only moves code, no functional impact expected. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/ufs/qcom,ufs-common.yaml | 67 ++++++++++++++++++= ++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 53 +---------------- 2 files changed, 68 insertions(+), 52 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml b/D= ocumentation/devicetree/bindings/ufs/qcom,ufs-common.yaml new file mode 100644 index 0000000000000000000000000000000000000000..962dffcd28b44b3489be5615c75= e7270a0c45dc4 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,ufs-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Flash Storage (UFS) Controller Common Properties + +maintainers: + - Bjorn Andersson + +properties: + clocks: + minItems: 7 + maxItems: 9 + + clock-names: + minItems: 7 + maxItems: 9 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 2 + + interconnect-names: + items: + - const: ufs-ddr + - const: cpu-ufs + + iommus: + minItems: 1 + maxItems: 2 + + phys: + maxItems: 1 + + phy-names: + items: + - const: ufsphy + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + resets: + maxItems: 1 + + '#reset-cells': + const: 1 + + reset-names: + items: + - const: rst + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RESET pin of the UFS memory device. + +allOf: + - $ref: ufs-common.yaml + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index 6c6043d9809e1d6bf489153ab0aea5186d3563cc..fc0f7b8d1cd1c4a2168f29cffcc= 0c2ff660424df 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -47,39 +47,6 @@ properties: - const: qcom,ufshc - const: jedec,ufs-2.0 =20 - clocks: - minItems: 7 - maxItems: 9 - - clock-names: - minItems: 7 - maxItems: 9 - - dma-coherent: true - - interconnects: - minItems: 2 - maxItems: 2 - - interconnect-names: - items: - - const: ufs-ddr - - const: cpu-ufs - - iommus: - minItems: 1 - maxItems: 2 - - phys: - maxItems: 1 - - phy-names: - items: - - const: ufsphy - - power-domains: - maxItems: 1 - qcom,ice: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the Inline Crypto Engine node @@ -93,30 +60,12 @@ properties: - const: std - const: ice =20 - required-opps: - maxItems: 1 - - resets: - maxItems: 1 - - '#reset-cells': - const: 1 - - reset-names: - items: - - const: rst - - reset-gpios: - maxItems: 1 - description: - GPIO connected to the RESET pin of the UFS memory device. - required: - compatible - reg =20 allOf: - - $ref: ufs-common.yaml + - $ref: qcom,ufs-common.yaml =20 - if: properties: --=20 2.48.1 From nobody Sun Oct 5 20:17:12 2025 Received: from mail-qv1-f49.google.com (mail-qv1-f49.google.com [209.85.219.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B053299943 for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The binding for Qualcomm SoC UFS controllers grew and it will grow further. Split SC7280 and several other devices which: 1. Do not reference ICE as IO address space, but as phandle, 2. Have same order of clocks. The split allows easier review and further growth with MCQ IO address space. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml | 149 +++++++++++++++++= ++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 107 +++++---------- 2 files changed, 183 insertions(+), 73 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml b= /Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0f2fe48860a7847819f325bb817= 0692a82af2ae3 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,sc7280-ufshc.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,sc7280-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 and Other SoCs UFS Controllers + +maintainers: + - Bjorn Andersson + +# Select only our matches, not all jedec,ufs-2.0 +select: + properties: + compatible: + contains: + enum: + - qcom,msm8998-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,msm8998-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + - const: qcom,ufshc + - const: jedec,ufs-2.0 + + reg: + maxItems: 1 + + reg-names: + items: + - const: std + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: rx_lane1_sync_clk + + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Inline Crypto Engine node + +required: + - compatible + - reg + +allOf: + - $ref: qcom,ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + ufs@1d84000 { + compatible =3D "qcom,sm8450-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_mem_phy_lanes>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l7b_2p5>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l9b_1p2>; + vccq-max-microamp =3D <1200000>; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + iommus =3D <&apps_smmu 0xe0 0x0>; + interconnects =3D <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_E= BI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_= UFS_MEM_CFG>; + interconnect-names =3D "ufs-ddr", "cpu-ufs"; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + qcom,ice =3D <&ice>; + }; + }; diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index fc0f7b8d1cd1c4a2168f29cffcc0c2ff660424df..b34da3df841a11eb50022fa7d09= 1ebfbb33b1d17 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -15,7 +15,16 @@ select: properties: compatible: contains: - const: qcom,ufshc + enum: + - qcom,msm8994-ufshc + - qcom,msm8996-ufshc + - qcom,qcs615-ufshc + - qcom,sc7180-ufshc + - qcom,sdm845-ufshc + - qcom,sm6115-ufshc + - qcom,sm6125-ufshc + - qcom,sm6350-ufshc + - qcom,sm8150-ufshc required: - compatible =20 @@ -25,25 +34,13 @@ properties: - enum: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - - qcom,msm8998-ufshc - qcom,qcs615-ufshc - - qcom,qcs8300-ufshc - - qcom,sa8775p-ufshc - qcom,sc7180-ufshc - - qcom,sc7280-ufshc - - qcom,sc8180x-ufshc - - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - - qcom,sm8250-ufshc - - qcom,sm8350-ufshc - - qcom,sm8450-ufshc - - qcom,sm8550-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 =20 @@ -92,44 +89,6 @@ allOf: reg-names: maxItems: 1 =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-ufshc - - qcom,qcs8300-ufshc - - qcom,sa8775p-ufshc - - qcom,sc7280-ufshc - - qcom,sc8180x-ufshc - - qcom,sc8280xp-ufshc - - qcom,sm8250-ufshc - - qcom,sm8350-ufshc - - qcom,sm8450-ufshc - - qcom,sm8550-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: core_clk - - const: bus_aggr_clk - - const: iface_clk - - const: core_clk_unipro - - const: ref_clk - - const: tx_lane0_sync_clk - - const: rx_lane0_sync_clk - - const: rx_lane1_sync_clk - reg: - minItems: 1 - maxItems: 1 - reg-names: - maxItems: 1 - - if: properties: compatible: @@ -246,10 +205,10 @@ unevaluatedProperties: false =20 examples: - | - #include + #include #include #include - #include + #include #include =20 soc { @@ -257,9 +216,12 @@ examples: #size-cells =3D <2>; =20 ufs@1d84000 { - compatible =3D "qcom,sm8450-ufshc", "qcom,ufshc", + compatible =3D "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0 0x01d84000 0 0x3000>; + reg =3D <0x0 0x01d84000 0x0 0x2500>, + <0x0 0x01d90000 0x0 0x8000>; + reg-names =3D "std", "ice"; + interrupts =3D ; phys =3D <&ufs_mem_phy_lanes>; phy-names =3D "ufsphy"; @@ -275,19 +237,8 @@ examples: vccq-max-microamp =3D <1200000>; =20 power-domains =3D <&gcc UFS_PHY_GDSC>; - iommus =3D <&apps_smmu 0xe0 0x0>; - interconnects =3D <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_E= BI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_= UFS_MEM_CFG>; - interconnect-names =3D "ufs-ddr", "cpu-ufs"; + iommus =3D <&apps_smmu 0x300 0>; =20 - clock-names =3D "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -295,15 +246,25 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz =3D <75000000 300000000>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk", + "ice_core_clk"; + freq-table-hz =3D <37500000 300000000>, <0 0>, <0 0>, - <75000000 300000000>, - <75000000 300000000>, + <37500000 300000000>, <0 0>, <0 0>, - <0 0>; - qcom,ice =3D <&ice>; + <0 0>, + <0 0>, + <0 300000000>; }; }; --=20 2.48.1