From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3883F23741 for ; Wed, 30 Jul 2025 08:57:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865837; cv=none; b=to7BEOsq9bJrIHJ/APesUVUxwg2PtGEKj78yi5TCzxTUbKMYvLTR2JE29vCeI1Ez0NCM9wL0bWJBRtaoT8q93FBUWBIJXxfQW/zILjCJX6YmA9CzYEamyFDzck8nqtLCLK53nJAtwa+tk/I/DI50fPRmyZsI16/8d8P0sxEuPW4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865837; c=relaxed/simple; bh=7M8WQ93AaEVDFJvrP9tpFEBFhyFY0X5kFY5fADadnZw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qwVD2EgrXAZTzoq2UaVm+wzXRsVRKqT6jFIr66SSqRrPEX7f2eS5hAGOpEt72T56D415g196mZDBHIQymr/0PxjEx+/5hUCKB2VlmxNHJurBQl09qIUo60DXjTu95Z9drwZmW22xJk2bljgq9h5kR3/4LVM4ixmrbIAhXTI5xn8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kS7Lxf7W; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kS7Lxf7W" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A563CC4CEE7; Wed, 30 Jul 2025 08:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865836; bh=7M8WQ93AaEVDFJvrP9tpFEBFhyFY0X5kFY5fADadnZw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kS7Lxf7WKc3ULnfBuTrkt7Wb+v46BmyQvieQnusgIYqCjX8FiwcsiTla7QSs4GfOg UEO0I+Wwlp9swsUV5K47l64x5JIV7BJyawp8PJGpUtCkqBiWmQcGuMqOURm+NB0foD 46bMjN2xlnT8c0HpM0/pvoz5H88maCcr0PeegO0Sib+CbWj/EqOG7NIUx1o5xIaVGJ kyfSvYSDVtqVwJ8sLbnHv1EdUEV4o+LV7vxCAYdPqKbWAGSu4YiiK9OhGgVZ5l8maK vxF2ZdFRwM6AljzTudUa40XwYynFgvTOxFPNTKbgwY9qN7In34C84mueN3l3Sw9jJk A0fvrlJJ/DK7w== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:01 +0200 Subject: [PATCH 01/14] drm/tidss: dispc: Remove unused OVR_REG_GET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-1-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1128; i=mripard@kernel.org; h=from:subject:message-id; bh=7M8WQ93AaEVDFJvrP9tpFEBFhyFY0X5kFY5fADadnZw=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd9xIsGLcZn3htqnv9KuPZp85BrEqz89JDEzZem+Pc6 6GUftq5YyoLgzAng6yYIssTmbDTy9sXVznYr/wBM4eVCWQIAxenAEykw52xhkfhT4jl6jX7jDeZ b4nr6EhND0278PXbM8d7866f2NjVOnsb/1WBOb9Uv0bX7/I6KHfPjrE+eH3ApcC56a9WuE503aJ qsvnhw+kckkc7IgvOZgp3P9y7svvy9693s/QvNui9Z/k1gXcSAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The OVR_REG_GET function in the dispc driver is not used anywhere. Let's drop it. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 975d94547c3f9d5e9ad61aefd4eeb8ada8874cb0..8ec06412cffa71512cead9725bb= 43440258eb1ec 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -666,17 +666,10 @@ static void VP_REG_FLD_MOD(struct dispc_device *dispc= , u32 vp, u32 idx, u32 val, { dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), val, start, end)); } =20 -__maybe_unused -static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, - u32 start, u32 end) -{ - return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); -} - static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, u32 val, u32 start, u32 end) { dispc_ovr_write(dispc, ovr, idx, FLD_MOD(dispc_ovr_read(dispc, ovr, idx), --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED660293457 for ; Wed, 30 Jul 2025 08:57:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865839; cv=none; b=nbJNoIiV8sNObShZkCqmaAF+S+3QLQlvhfytw4xAHJZTct+paCdYwXiKGRaKaRvs9emRW4e/xXBlTsbSllm4GPHsaDv4rGjjKYM7vYreqA3ZCwo8eoc4fCoftsU3XGs2/5rKJisITvamItDlTUAml+Ty1RaIgZQI641v/O4tCUk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865839; c=relaxed/simple; bh=bkLVe2XldDNNSNpRPNT/dLJIjNP/DhhAJl1lPaX/SsQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LihLBaTz5rjNhoxUsYukgIuZjJ9M2pqsxauzg1srpr8iR/xToVaEHB4hXSaRcGtbQyDLerwzcfHbNJ2R+0usuT4MfKcuw19GnAcfGsX9tL8hkMFgbmbj+g10qYXNdx74hovAknaBUPJ8fkGcB6kHX5CPI6T5aBNWPxEnGoQ6ZrU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Hyl9tMrt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Hyl9tMrt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D3C3C4CEE7; Wed, 30 Jul 2025 08:57:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865838; bh=bkLVe2XldDNNSNpRPNT/dLJIjNP/DhhAJl1lPaX/SsQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Hyl9tMrt6H46igkWQMrC4KuPDiVeh53jAxZsEZ3MD5VsSbblYHRlmBq+cce4DlYMC 1Z2tQbS8TLexrsILrcjCVaGwib7AXdmb3XELo8FVMtEvLaKwaxowlPGpW3Az9+OVM+ CdO4g/k8HOlvSvbrt12XKytowS43sCTKtX+j9kCgpG4PGuH9eWf4gUOpRSxNbbHTYP t8ASYrE0uNizjGiNlYS8ovcsHimMp5LGLEi9ozyrRAUjDduouDVOHoltb6rHz1+9Hn MHNHO1At+ejsTpd67wP1NkOnzIA8WGYbXt3ZCiAtMnh+NqAakFyEtzknbnJZ24wYZh DjpZs7ahOKuiQ== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:02 +0200 Subject: [PATCH 02/14] drm/tidss: dispc: Switch to GENMASK instead of FLD_MASK Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-2-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1532; i=mripard@kernel.org; h=from:subject:message-id; bh=bkLVe2XldDNNSNpRPNT/dLJIjNP/DhhAJl1lPaX/SsQ=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd9xKmbpyxo8Ih/+jppS8TWVa8X9m67c/9RUqKhWeyv ALjpk2b2TGVhUGYk0FWTJHliUzY6eXti6sc7Ff+gJnDygQyhIGLUwAmsrWQsU7NWtfQu/nvceag C/Yvgsrrpq/b8Z733NTlVapu/+I1Le5zrgmWEfCxaKxheLPHO2hfNGPD3hfiK3+yvn1pNPW9Unz +Ga/Tv3Nm/rzskZlxOUnVykYpw6S1MVgkz1/2N5NoTEH0jx4A X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The dispc FLD_MASK function is an exact equivalent of the GENMASK macro. Let's convert the dispc driver to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 8ec06412cffa71512cead9725bb43440258eb1ec..5a0904acbed279506df2edad559= dfe06f25cd7b5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,28 +607,23 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -static u32 FLD_MASK(u32 start, u32 end) -{ - return ((1 << (start - end + 1)) - 1) << end; -} - static u32 FLD_VAL(u32 val, u32 start, u32 end) { - return (val << end) & FLD_MASK(start, end); + return (val << end) & GENMASK(start, end); } =20 static u32 FLD_GET(u32 val, u32 start, u32 end) { - return (val & FLD_MASK(start, end)) >> end; + return (val & GENMASK(start, end)) >> end; } =20 static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) { - return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); + return (orig & ~GENMASK(start, end)) | FLD_VAL(val, start, end); } =20 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) { return FLD_GET(dispc_read(dispc, idx), start, end); --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11F8F293457 for ; Wed, 30 Jul 2025 08:57:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865842; cv=none; b=VSUB85xu/f09KPLaKT0yD16I9sFWzToz5SpcrdTclI4+/aD+S54HRv02p9c4vUZwY/tBwTamai/4fdupqIDdAMn95ec23PlKyjtrBVnAA+MZcyzVwF4fkUWfGK5KweVU44z+E0gz91tnkUu2Beg4BTyWMEVznxHqtxWDsSo449g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865842; c=relaxed/simple; bh=H/6/5bAJLbAq+nuixRMqwlb5Gusenrm0K1/fZ3hIW4I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MJrLN5BhSQHyEWF7iAQpF0JTFyUUXIgBqKVaNbaKEDxGAdzIgFLLlm6ZDxSWySuU4xEwD2Z90KW+L/y8ARzl2HEz3NGUXG5+kmYWCx8wST2nKZ84YxSqVzFrY+0EhwpQ5yLdSSvUZQxPwCx4ENwO5joUpuxpXZz7agZoS0aEa50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i5GdIDge; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i5GdIDge" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54412C4CEF5; Wed, 30 Jul 2025 08:57:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865841; bh=H/6/5bAJLbAq+nuixRMqwlb5Gusenrm0K1/fZ3hIW4I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i5GdIDgeuGlIiIA3wR9Rs9JJnKFpuc2eviF1jmVGo64vVIpEi5ApdBe9Trj3hRX46 quFS0hzcVYDwjYjjmzHwL6EpTdRPxmS6TaDN1j3TWfibcAr4lWnRkTtHj8JXat+QLu Cpu7KCS7TjaoUA9RpAS2OhM7dmZpd1pBDpiH/dUWgJYV6emhtC+ivs2S0LHOfKn9jP PtFpZjTcNbOecNrsnFUA4hFtoZnc3MuVnymuOOG2dMQfFNvNRSHS9O+8JFSn/vA/te fj7uoXBGTlL3g6D+eJ6/9LoWMvCAaIQU7NugogaPaoBNDxeoMHLWxXMiZrnOYd8vMh PcOw08aS84e1Q== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:03 +0200 Subject: [PATCH 03/14] drm/tidss: dispc: Switch to FIELD_PREP for FLD_VAL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-3-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=943; i=mripard@kernel.org; h=from:subject:message-id; bh=H/6/5bAJLbAq+nuixRMqwlb5Gusenrm0K1/fZ3hIW4I=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd9xJCLIrEl5pk5V7bMq9SzTOwcO/3+f6nj7zYpOmin 9pQ5BbQMZWFQZiTQVZMkeWJTNjp5e2LqxzsV/6AmcPKBDKEgYtTACZyV4exYXvx38ur0t9eyLyn wm1zXV91wbm0TaUbe5zkdVymzVyjysruahURqxAy98LfnstnGb7LMdZHTp296NKV0NKMO78rp65 fu25zZ1JUpkxS5KL/E2L+u01f4fHF4I5I85dz+yrbPbjYLpoCAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_VAL function in the dispc driver hand-rolls what the FIELD_PREP macro provides. Let's switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 5a0904acbed279506df2edad559dfe06f25cd7b5..7e36f5af666342dc4f5fa9159d8= 29d88362de18c 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -609,11 +609,11 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) * number. For example 7:0 */ =20 static u32 FLD_VAL(u32 val, u32 start, u32 end) { - return (val << end) & GENMASK(start, end); + return FIELD_PREP(GENMASK(start, end), val); } =20 static u32 FLD_GET(u32 val, u32 start, u32 end) { return (val & GENMASK(start, end)) >> end; --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84913293C76 for ; Wed, 30 Jul 2025 08:57:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865844; cv=none; b=ST0yRvKRnkC/F+GimwKlnXDld5PMB/CNwDMkS2CFZig+BqeLjsh+39KEm7Z8EuXsfUpNg1HTyme7fbfmaQLaDuFcPDCKRY5bahOZlvVtxUD1WSgPcg6VMUhx494BbrKtqUEvoWChtQp6GjzIX48Ku5EuIbwZGR0rK64hBxqitmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865844; c=relaxed/simple; bh=w27UoqUceMQEYOVXBT40nQLYhN3aneD/BafQ1QuXRhE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eiomYnw5104iCcajIM8BV80lTMxKiFPfEjr0xb7+sZ6lamtB9W4+OB2TEL1sc7sscGLXwznGj8fBmjdSMic38J5h3EgJeV7sW9WGyAMoxaE99bxE14vPK+1Jl+rsWlRka7Ik9EPRABjV9RmDhCCA0v7LKgQD7wdXJAPikXV2UhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IeRfxubk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IeRfxubk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00987C4CEF8; Wed, 30 Jul 2025 08:57:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865844; bh=w27UoqUceMQEYOVXBT40nQLYhN3aneD/BafQ1QuXRhE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IeRfxubkqu4oxCBCwwetWWfBurhzTe+I5K5H3PULR5TpgEs5pDN14Q1Lw78amLSLM Acs3AaTQ35tLjmqjlytUAy46ev+xvO9IvcTg6Wy7E95kY3chcsyvn3v+FWHSR2ACME dOUr+B9p8ktpODQ8A9FZU8i9W9Jc1p29a2u+698VEUY+QP5/Us6elinR+TAxpGWBGj H/9B0OabvgjLUs0XZN/GcH5URkvUMBM8GcTWso/qQGlN0UjhE6zZKWllC+OcwpB05u rwpZdZMUGJekcy4meX86BaaP6csaeWqdLA7GkEcrKw5LAO51fbGk2kjqcuBPmEwe4n wgl09sTdmsS3g== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:04 +0200 Subject: [PATCH 04/14] drm/tidss: dispc: Get rid of FLD_GET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-4-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2296; i=mripard@kernel.org; h=from:subject:message-id; bh=w27UoqUceMQEYOVXBT40nQLYhN3aneD/BafQ1QuXRhE=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd9xK/JR/mvPhui2Zes3Dkaad/7F9FimVXJJVd5lHfp Rl6qPdIx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZjIxK2MDX8O9y8oVFbyYvu0 9iPLw/c+uZLBNubvXmSEpNk/YO9Ie8rzaev5n++5Wz79zgw7Y8M/l7E+NM31hFGTgVPFudIeq1c 90w8ETTa+/fOr60WRvRplz4WZNT3nftFewfOmVeHn21/3pP4DAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_GET function is an equivalent to what FIELD_GET + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 7e36f5af666342dc4f5fa9159d829d88362de18c..974387313632cc85fb6c4d559b4= d35656b1119da 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -612,23 +612,18 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) static u32 FLD_VAL(u32 val, u32 start, u32 end) { return FIELD_PREP(GENMASK(start, end), val); } =20 -static u32 FLD_GET(u32 val, u32 start, u32 end) -{ - return (val & GENMASK(start, end)) >> end; -} - static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) { return (orig & ~GENMASK(start, end)) | FLD_VAL(val, start, end); } =20 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) { - return FLD_GET(dispc_read(dispc, idx), start, end); + return FIELD_GET(GENMASK(start, end), dispc_read(dispc, idx)); } =20 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, u32 start, u32 end) { @@ -637,11 +632,12 @@ static void REG_FLD_MOD(struct dispc_device *dispc, u= 32 idx, u32 val, } =20 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, u32 start, u32 end) { - return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); + return FIELD_GET(GENMASK(start, end), + dispc_vid_read(dispc, hw_plane, idx)); } =20 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 = idx, u32 val, u32 start, u32 end) { @@ -651,11 +647,11 @@ static void VID_REG_FLD_MOD(struct dispc_device *disp= c, u32 hw_plane, u32 idx, } =20 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, u32 start, u32 end) { - return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); + return FIELD_GET(GENMASK(start, end), dispc_vp_read(dispc, vp, idx)); } =20 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u3= 2 val, u32 start, u32 end) { --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 372C8292B4D for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L8Qy6r2N" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA761C4CEE7; Wed, 30 Jul 2025 08:57:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865847; bh=9K35uZwPjzxtwzKo6ZMyRr2kFSxlchGdQNRiwtz6A4A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=L8Qy6r2N2P4DyRaoxYb2FLtMV6r7CURqncUtCIFEnb91vrw7mMK4KWw1rbdXG7Ry8 F5zHdmA+l77uTJkNHkr18a4tK6Tn8z+jDAOWrwuwYxpE7uY1pf4mrY1g00KliWfXnt 3aUlJ6r7R1TqpsVQB3MaHDm9NY0p4YyhVYCS0zFpsR2HTSC7jTsevsgafwh248pV1U K3nRCKHJLgb9nloRuA61nxoQP3DCyxkqbjFVyqemV7tAFs5rB5SazoAFi+zp1CldM/ gatwOif5qi3iZvSgPVPmhJajbZ28P5IueB5asmwWUph6znpXUP17bQFJ+IVGKZ0Qc1 uO3LiICyJsU9g== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:05 +0200 Subject: [PATCH 05/14] drm/tidss: dispc: Get rid of FLD_VAL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-5-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6831; i=mripard@kernel.org; h=from:subject:message-id; bh=9K35uZwPjzxtwzKo6ZMyRr2kFSxlchGdQNRiwtz6A4A=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd9xLvnmThOWqneFgtjt+Wab7saovtW5dF1/BcOL/z/ YVWtXktHVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAiV6MYGxp/xLJv2NI5xVnf rGr/scDdL/7wCCyyvbXw1ld+PXNOy98tNfa75ro1eRTd+f/z/gKuJ4wNSxf5ZjPEfHiYNEtH5Kv U5twpb+0n35ugP/fxQpfCI/3/VXY014rErNt8vLyH7blO4ScNAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_VAL function is an equivalent to what FIELD_PREP + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 57 ++++++++++++++++++---------------= ---- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 974387313632cc85fb6c4d559b4d35656b1119da..30f281221a5de6b69cc3edd2bf6= 43cf0f8bea63b 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,18 +607,14 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -static u32 FLD_VAL(u32 val, u32 start, u32 end) -{ - return FIELD_PREP(GENMASK(start, end), val); -} - static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) { - return (orig & ~GENMASK(start, end)) | FLD_VAL(val, start, end); + return (orig & ~GENMASK(start, end)) | FIELD_PREP(GENMASK(start, end), + val); } =20 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) { return FIELD_GET(GENMASK(start, end), dispc_read(dispc, idx)); @@ -1221,18 +1217,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, vfp =3D mode->vsync_start - mode->vdisplay; vsw =3D mode->vsync_end - mode->vsync_start; vbp =3D mode->vtotal - mode->vsync_end; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, - FLD_VAL(hsw - 1, 7, 0) | - FLD_VAL(hfp - 1, 19, 8) | - FLD_VAL(hbp - 1, 31, 20)); + FIELD_PREP(GENMASK(7, 0), hsw - 1) | + FIELD_PREP(GENMASK(19, 8), hfp - 1) | + FIELD_PREP(GENMASK(31, 20), hbp - 1)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, - FLD_VAL(vsw - 1, 7, 0) | - FLD_VAL(vfp, 19, 8) | - FLD_VAL(vbp, 31, 20)); + FIELD_PREP(GENMASK(7, 0), vsw - 1) | + FIELD_PREP(GENMASK(19, 8), vfp) | + FIELD_PREP(GENMASK(31, 20), vbp)); =20 ivs =3D !!(mode->flags & DRM_MODE_FLAG_NVSYNC); =20 ihs =3D !!(mode->flags & DRM_MODE_FLAG_NHSYNC); =20 @@ -1251,21 +1247,21 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, /* always use DE_HIGH for OLDI */ if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) ieo =3D false; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, - FLD_VAL(align, 18, 18) | - FLD_VAL(onoff, 17, 17) | - FLD_VAL(rf, 16, 16) | - FLD_VAL(ieo, 15, 15) | - FLD_VAL(ipc, 14, 14) | - FLD_VAL(ihs, 13, 13) | - FLD_VAL(ivs, 12, 12)); + FIELD_PREP(GENMASK(18, 18), align) | + FIELD_PREP(GENMASK(17, 17), onoff) | + FIELD_PREP(GENMASK(16, 16), rf) | + FIELD_PREP(GENMASK(15, 15), ieo) | + FIELD_PREP(GENMASK(14, 14), ipc) | + FIELD_PREP(GENMASK(13, 13), ihs) | + FIELD_PREP(GENMASK(12, 12), ivs)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, - FLD_VAL(mode->hdisplay - 1, 11, 0) | - FLD_VAL(mode->vdisplay - 1, 27, 16)); + FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) | + FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1)); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) @@ -1577,18 +1573,18 @@ struct dispc_csc_coef { #define DISPC_CSC_REGVAL_LEN 8 =20 static void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) { -#define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19)) +#define OVAL(x, y) (FIELD_PREP(GENMASK(15, 3), x) | FIELD_PREP(GENMASK(31,= 19), y)) regval[5] =3D OVAL(csc->preoffset[0], csc->preoffset[1]); regval[6] =3D OVAL(csc->preoffset[2], csc->postoffset[0]); regval[7] =3D OVAL(csc->postoffset[1], csc->postoffset[2]); #undef OVAL } =20 -#define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16)) +#define CVAL(x, y) (FIELD_PREP(GENMASK(10, 0), x) | FIELD_PREP(GENMASK(26,= 16), y)) static void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regva= l) { regval[0] =3D CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); regval[1] =3D CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); @@ -1823,11 +1819,12 @@ static void dispc_vid_write_fir_coefs(struct dispc_= device *dispc, s16 c1, c2; u32 c12; =20 c1 =3D coefs->c1[phase]; c2 =3D coefs->c2[phase]; - c12 =3D FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20); + c12 =3D FIELD_PREP(GENMASK(19, 10), c1) | FIELD_PREP(GENMASK(29, 20), + c2); =20 dispc_vid_write(dispc, hw_plane, reg, c12); } } =20 @@ -2321,18 +2318,18 @@ static u32 dispc_vid_get_fifo_size(struct dispc_dev= ice *dispc, u32 hw_plane) =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_k2g_plane_init(struct dispc_device *dispc) { unsigned int hw_plane; @@ -2469,12 +2466,12 @@ static void dispc_initial_config(struct dispc_devic= e *dispc) dispc_vp_init(dispc); =20 /* Note: Hardcoded DPI routing on J721E for now */ if (dispc->feat->subrev =3D=3D DISPC_J721E) { dispc_write(dispc, DISPC_CONNECTIONS, - FLD_VAL(2, 3, 0) | /* VP1 to DPI0 */ - FLD_VAL(8, 7, 4) /* VP3 to DPI1 */ + FIELD_PREP(GENMASK(3, 0), 2) | /* VP1 to DPI0 */ + FIELD_PREP(GENMASK(7, 4), 8) /* VP3 to DPI1 */ ); } } =20 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, @@ -2648,12 +2645,12 @@ static void dispc_k2g_cpr_from_ctm(const struct drm= _color_ctm *ctm, cpr->m[CSC_BR] =3D dispc_S31_32_to_s2_8(ctm->matrix[6]); cpr->m[CSC_BG] =3D dispc_S31_32_to_s2_8(ctm->matrix[7]); cpr->m[CSC_BB] =3D dispc_S31_32_to_s2_8(ctm->matrix[8]); } =20 -#define CVAL(xR, xG, xB) (FLD_VAL(xR, 9, 0) | FLD_VAL(xG, 20, 11) | \ - FLD_VAL(xB, 31, 22)) +#define CVAL(xR, xG, xB) (FIELD_PREP(GENMASK(9, 0), xR) | FIELD_PREP(GENMA= SK(20, 11), xG) | \ + FIELD_PREP(GENMASK(31, 22), xB)) =20 static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc, u32 *regval) { regval[0] =3D CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); 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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CAggZeWQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CAggZeWQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61F25C4CEF8; Wed, 30 Jul 2025 08:57:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865849; bh=fsk1q+vbHOBdJ2fmmzNm81hQGwxIASDXY28bXs1Y6uU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CAggZeWQ3/LTmz0mqZSSau3DZMlBPU5t9p73DwEnDhUADqCswDKH8Z3+Lxpopf11o gPC7Xz9jhghVBQS05Iu9OCXASWV93rcet9MFyfXdEIZMkpP2Yw7zfBmFYTJ2N51hEu zf5yElaGkDa3B53aIpvTuWqci20UjVBAzNyydQ2zio87YE5MuHrdHuSRLW+yQH6sed 8C5vcfpZnHw3YeTDxcgQFmB/oHtR8H3GQpR1MilHxxJdri+xqXs4mRKVcPl+JOVYYV qbkFeGBxOGjKy7gGC/nbJc5TbN3wvKei1QfxU/Fmv2timvLMeTcs1a4J0bbTdT3tl0 UHnsOeOYogsdA== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:06 +0200 Subject: [PATCH 06/14] drm/tidss: dispc: Switch FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-6-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3538; i=mripard@kernel.org; h=from:subject:message-id; bh=fsk1q+vbHOBdJ2fmmzNm81hQGwxIASDXY28bXs1Y6uU=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd95KWHZ+xKmJemGuareipfWYv7cOZv6SqyoYEzLPj8 3+fcc+lYyoLgzAng6yYIssTmbDTy9sXVznYr/wBM4eVCWQIAxenAEzkjiZjfWHj4rdqSpNCZGqO 3v8qxzR5/p1bUVuaj26N6PbI6M489/76hzZvRnUnqSshv/Pn/vl6kLG+Qo718n1u8R9HIt9/VtT ROLTs6YZNkcv5pmQxvy2zOF7ewJLl6px4d+FNGYlorsD1utcB X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them, twice. Let's pass the mask, so the caller can generate it once and we would use it twice. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 30f281221a5de6b69cc3edd2bf643cf0f8bea63b..e4729a5b79ed5d554e05c020adb= 7e2d3e7a8f4d3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,26 +607,25 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) +static u32 FLD_MOD(u32 orig, u32 val, u32 mask) { - return (orig & ~GENMASK(start, end)) | FIELD_PREP(GENMASK(start, end), - val); + return (orig & ~mask) | FIELD_PREP(mask, val); } =20 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) { return FIELD_GET(GENMASK(start, end), dispc_read(dispc, idx)); } =20 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, u32 start, u32 end) { - dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, - start, end)); + dispc_write(dispc, idx, + FLD_MOD(dispc_read(dispc, idx), val, GENMASK(start, end))); } =20 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, u32 start, u32 end) { @@ -636,12 +635,11 @@ static u32 VID_REG_GET(struct dispc_device *dispc, u3= 2 hw_plane, u32 idx, =20 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 = idx, u32 val, u32 start, u32 end) { dispc_vid_write(dispc, hw_plane, idx, - FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), - val, start, end)); + FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), val, GENMASK(start, end))= ); } =20 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, u32 start, u32 end) { @@ -649,20 +647,19 @@ static u32 VP_REG_GET(struct dispc_device *dispc, u32= vp, u32 idx, } =20 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u3= 2 val, u32 start, u32 end) { - dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), - val, start, end)); + dispc_vp_write(dispc, vp, idx, + FLD_MOD(dispc_vp_read(dispc, vp, idx), val, GENMASK(start, end))); } =20 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, u32 val, u32 start, u32 end) { dispc_ovr_write(dispc, ovr, idx, - FLD_MOD(dispc_ovr_read(dispc, ovr, idx), - val, start, end)); + FLD_MOD(dispc_ovr_read(dispc, ovr, idx), val, GENMASK(start, end))); } =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { dispc_irq_t vp_stat =3D 0; @@ -1155,11 +1152,12 @@ static void dispc_enable_am65x_oldi(struct dispc_de= vice *dispc, u32 hw_videoport dev_warn(dispc->dev, "%s: %d port width not supported\n", __func__, fmt->data_width); =20 oldi_cfg |=3D BIT(7); /* DEPOL */ =20 - oldi_cfg =3D FLD_MOD(oldi_cfg, fmt->am65x_oldi_mode_reg_val, 3, 1); + oldi_cfg =3D FLD_MOD(oldi_cfg, fmt->am65x_oldi_mode_reg_val, + GENMASK(3, 1)); =20 oldi_cfg |=3D BIT(12); /* SOFTRST */ =20 oldi_cfg |=3D BIT(0); /* ENABLE */ =20 --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEF89296159 for ; Wed, 30 Jul 2025 08:57:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865852; cv=none; b=omQAHoqPB4PskNdClsrKzi3/zSkvhs4k3hxpBQ+chpMq03BEtFiIRWdiTs9pMbriMugttKViAPvdgBnl+/+QRjtd5myQqGu7U4sx4HXA5GDx88cueYM5uG0FdGMucdwEhWTB4akHw1S0k1ovt9Z9SKO6A1d9/x3Mj8w2Y+CokhE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865852; c=relaxed/simple; bh=NXOHjZ58aGBvwMQrtBkDomOQELY6ttJK1yROEv5Iv3k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SMD6PxeGmdGoBe+qLHIIuchPk7eiObxMDc+JcFrjCQbKhMJwXls2Sig3Iasj1GAk8xdydF7NNFezxAcJ/CtOEwzyTyxC695/Qme9cC/qic3stH5tTbZydx/8iNrAoxzroLm6za8FFd4Dq7WeTNx/MxoUEgyMcwQKiwB8VymGj48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SO2hbWaq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SO2hbWaq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E8E4C4CEF5; Wed, 30 Jul 2025 08:57:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865852; bh=NXOHjZ58aGBvwMQrtBkDomOQELY6ttJK1yROEv5Iv3k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SO2hbWaqBX+2PMs8syTDt8lJb8OZEyqKfN31Gvroq5Qzaaw3sgdcf79vgpWdhGpdN 1mBT001jGpmrfnRrwDyEWqTEWbnDTQy7m7eADhsPtmsN+hoTUIQcmXYNK5F7bHqf3H pdX3b1KYrk9H4FneyKCJfDvkupe8EFRaROkYQhBNnpYHYkOFX83aXg/Y5KqWR7la5b PY+QJ77Aj4gJB1Z2qx8q7nch+9cfTETdIyAv9iZ4gUbNacMdiPEPwPFDntHoIz6SNb ysLs35y7r5EblxMilH3GMkGiFTNozkN4KNVsdk+rTHaIt8ea2sYIHl+bRSNXSAmEWo VRG5b2pLWzx+A== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:07 +0200 Subject: [PATCH 07/14] drm/tidss: dispc: Switch REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-7-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2793; i=mripard@kernel.org; h=from:subject:message-id; bh=NXOHjZ58aGBvwMQrtBkDomOQELY6ttJK1yROEv5Iv3k=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd95Lu+JoHfiwMmsy34av3FbGI299XPribdO2Lms71U 9sXK/Z7dUxlYRDmZJAVU2R5IhN2enn74ioH+5U/YOawMoEMYeDiFICJvG5nrJV6ued+8ZuDTIu0 pD/OXJYdbcHlvHfOohQzrmWB06STZCu9MkX2d8neTH4w44jk80unwhgbbrsGznUS2Ltm8pbptua N7jPml7u2rDXWfbD9+OkPiYr558vWyW87r73x9hlra5Eep9MrAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index e4729a5b79ed5d554e05c020adb7e2d3e7a8f4d3..cfd6c4cf716904cf78699baf2eb= 4c3a0f57a1abe 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -612,13 +612,13 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) static u32 FLD_MOD(u32 orig, u32 val, u32 mask) { return (orig & ~mask) | FIELD_PREP(mask, val); } =20 -static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) +static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 mask) { - return FIELD_GET(GENMASK(start, end), dispc_read(dispc, idx)); + return FIELD_GET(mask, dispc_read(dispc, idx)); } =20 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, u32 start, u32 end) { @@ -2808,30 +2808,30 @@ int dispc_runtime_resume(struct dispc_device *dispc) { dev_dbg(dispc->dev, "resume\n"); =20 clk_prepare_enable(dispc->fclk); =20 - if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) =3D=3D 0) + if (REG_GET(dispc, DSS_SYSSTATUS, GENMASK(0, 0)) =3D=3D 0) dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); =20 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", dispc_read(dispc, DSS_REVISION)); =20 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", - REG_GET(dispc, DSS_SYSSTATUS, 1, 1), - REG_GET(dispc, DSS_SYSSTATUS, 2, 2), - REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(1, 1)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(2, 2)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(3, 3))); =20 if (dispc->feat->subrev =3D=3D DISPC_AM625 || dispc->feat->subrev =3D=3D DISPC_AM65X) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", - REG_GET(dispc, DSS_SYSSTATUS, 5, 5), - REG_GET(dispc, DSS_SYSSTATUS, 6, 6), - REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(5, 5)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(6, 6)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(7, 7))); =20 dev_dbg(dispc->dev, "DISPC IDLE %d\n", - REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(9, 9))); =20 dispc_initial_config(dispc); =20 dispc->is_enabled =3D true; =20 --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D735293462 for ; Wed, 30 Jul 2025 08:57:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865856; cv=none; b=Us70YgoVi1tbWiURcS7F3sHIuijOwqZbZM4oNDwyobZQSmWVcnLmzZu1CL+HpKqQv07GDhHMr+kk5WHSd4I0e7JDJLnEM/WJHEKWcdSiklKrVJb0S+GSp/liswungTtNae7y6Qtq2bJQTEGUtb4xJ2Oyc+8UVVSL6VG+gjqupy8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865856; c=relaxed/simple; bh=ckCwm94y3ouF4hgWKkHBVkDuFkJwr4qX5s2Tfa6qQQk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KybrDxC5TwR0K2UdQiQI1DvigHVA+QldU5fNO8+bwQ15An8cAphnm14Trael/O3S2lJXkKSNc+4yNeq7E/bVLcxlxuC9wuSqppw9rpEoHHdYwn7r19zG6eb6gjNfs8RwB87gyEvmoM+FYHYdqV6gWpb0lHxaAcqTVLaUdIXqOYY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=toeAzCqu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="toeAzCqu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD493C4CEF5; Wed, 30 Jul 2025 08:57:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865855; bh=ckCwm94y3ouF4hgWKkHBVkDuFkJwr4qX5s2Tfa6qQQk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=toeAzCqukiNeh8TyTn4Rv9ItK4BjOD723XP5Y1jnm9JP30X29Uhld7DOXJXLrY5l4 mMGvCHYrzhAuNcQi29uh2Vfb9El0L6XfHnQTaNhM3nFGceKnX4P5/DRcYsZGfrc65B 4gJZhtFABafln5Wkp0p+GmtZDdLOYDdLkBPkgAhr8j/1Q5h5U2IRFiUAxuoAhODvcZ yoAvAb4wvgNGx2YXDRjKUxI0UO771atLC3EDv0+0E34FgPrCahss6z7iL/d/pXX0YK sk1zzG2tbUWhlPwskk6jp5Snyenpq8gesDuyCaIWQ5gRqmmuqWfxRsV3NqSfimaMbr ihkqVPHCFkt+Q== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:08 +0200 Subject: [PATCH 08/14] drm/tidss: dispc: Switch REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-8-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3590; i=mripard@kernel.org; h=from:subject:message-id; bh=ckCwm94y3ouF4hgWKkHBVkDuFkJwr4qX5s2Tfa6qQQk=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd95JbpC/G7EndwyyYu/KS4tRQBsOWz9tm9RR/yfgjn JuVczK/YyoLgzAng6yYIssTmbDTy9sXVznYr/wBM4eVCWQIAxenAEzkpABjfdwZj7kxZrcjIhcJ v19+/0CW46wq7ugd+zfPZ2CR42Gfby4/cYcDb8Fe1e19EmfWzpj3ibHh++fHvdx5DhVtWjYfUyc HKa0QZHTIZGHgvx3DGalSvM/jd+GLwC7llZ48Xl0Xc/qdnQE= X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index cfd6c4cf716904cf78699baf2eb4c3a0f57a1abe..2d9bd95ded873232d22a1ecd812= 7cb0edc95c24c 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -617,15 +617,14 @@ static u32 FLD_MOD(u32 orig, u32 val, u32 mask) static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 mask) { return FIELD_GET(mask, dispc_read(dispc, idx)); } =20 -static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, - u32 start, u32 end) +static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, u32 = mask) { dispc_write(dispc, idx, - FLD_MOD(dispc_read(dispc, idx), val, GENMASK(start, end))); + FLD_MOD(dispc_read(dispc, idx), val, mask)); } =20 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, u32 start, u32 end) { @@ -2333,13 +2332,13 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) unsigned int hw_plane; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2384,17 +2383,17 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) u32 cba_lo_pri =3D 1; u32 cba_hi_pri =3D 0; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0)); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3)); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2918,11 +2917,11 @@ static int dispc_softreset(struct dispc_device *dis= pc) dispc_softreset_k2g(dispc); return 0; } =20 /* Soft reset */ - REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1)); /* Wait for reset to complete */ ret =3D readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, val, val & 1, 100, 5000); if (ret) { dev_err(dispc->dev, "failed to reset dispc\n"); --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52C9D2980A5 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UWVFvQxB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5FC7EC4CEE7; Wed, 30 Jul 2025 08:57:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865857; bh=yVhms9N5GqAzMLUA3rkSwf/i/c2WOIyLpO8RY/i5zhg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UWVFvQxBsqsAKLDzacN00rm+Mz0Fsa2dFr+cUNkV613T7CLdX9a0/sDdmZkjbKm6T tYnhUM2BQ0l60cj5kKY02C4+jTVh0/LEBt1ZIrqXBTvV09IqafHwo3TzWyCbQKKOBx m/uk3JzvEutC91gg4DnRVl5DGzZmWYUH29J6o8nwNPCH3326XQM6dIrga5P4gKAta4 ijQUXS6ZrXgkQBdME0YhHnrVSUq/x7Oh5iVayEckBDj1V5WRIrt3S8kRI7P233AKzJ aw3wu8kzsk7XvPa8rPc7q3I1a89tCiNPFUVRVKjwZbhBk1JrfmNu87lpk4OvreCEtV c4kdrK5+DCP0A== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:09 +0200 Subject: [PATCH 09/14] drm/tidss: dispc: Switch VID_REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-9-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1997; i=mripard@kernel.org; h=from:subject:message-id; bh=yVhms9N5GqAzMLUA3rkSwf/i/c2WOIyLpO8RY/i5zhg=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd95LVmqMfZ9zQjI+Me6rp1LMkaokb8xehP2m1x11t7 F49ltzRMZWFQZiTQVZMkeWJTNjp5e2LqxzsV/6AmcPKBDKEgYtTACbS/5SxzqJho4KmxenFrhlT Pzv5nLxo0P3/3CGWwr9SCReiLrx8uOq2qxGfw6XiXDvpqN0B96Y3MNZKvv5uNvMY912TVUxW56z yn3smbgrfV+PSarxhfc8hQ39btW+qM6vz+/7EPsncHMXaJQcA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VID_REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VID_REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 2d9bd95ded873232d22a1ecd8127cb0edc95c24c..d276ad881706057acabf6895f0c= 1f6758693504a 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -624,14 +624,13 @@ static void REG_FLD_MOD(struct dispc_device *dispc, u= 32 idx, u32 val, u32 mask) dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, mask)); } =20 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, - u32 start, u32 end) + u32 mask) { - return FIELD_GET(GENMASK(start, end), - dispc_vid_read(dispc, hw_plane, idx)); + return FIELD_GET(mask, dispc_vid_read(dispc, hw_plane, idx)); } =20 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 = idx, u32 val, u32 start, u32 end) { @@ -2308,11 +2307,12 @@ void dispc_plane_enable(struct dispc_device *dispc,= u32 hw_plane, bool enable) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { - return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); + return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, + GENMASK(15, 0)); } =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFA85298255 for ; Wed, 30 Jul 2025 08:57:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865861; cv=none; b=D9i4W81zlnxfY7CZqOeF9jhDWPPAXAjx8QfbF1ipjJXXlT2zhSW3+w/Lkd64dxPa2iaachUPJuNk/RZgVyG1Df73LMfj98lzYbQ+IxNnFn3GISwA1Pj1rNlYEwPvu/zXVOrQFcnqSZ8FS+9+xTHVhp1UiVXCd23G4AyjjYxdA74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865861; c=relaxed/simple; bh=34elvM1s2AFsn1IFdmSPZJm2lK5jpkaAUPc9/D4aLec=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=l7HjgHnjjuC91n+248pEdrrm1srQO4xFvg8bybYMrsJ2COTnqy/JqBCtPFGDUeaoIrmnsYe8VLNUya94Fsb73F0wkK16IM2wTqXJZeIj87LWSTXGuDpQ/byK9hjFwO7m717MsgjEiYHQwOPV+VsuSYWG/NyCwDq1nRi9udvBzBc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LcLiha0M; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LcLiha0M" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DB7AC4CEE7; Wed, 30 Jul 2025 08:57:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865860; bh=34elvM1s2AFsn1IFdmSPZJm2lK5jpkaAUPc9/D4aLec=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LcLiha0M0yBg+7g59jzHzw1eG0bIfsJNeRlyvoC01bzjF1rhKHlPPOyGsZMKD7aIt L7yyf09i0vcbko5hptfEAbORtdheVALmYX+71m3/PuNazKhfnh8kkBAUG0GTrSKwK1 w8YPf0MMuGkwBfiOZJkg97q9bqSA9IfF2gv0L1N5uhLKA2NAznZj0e32iOnJialF79 8xIiXNkCA6IsrziJzalIa7QpywowxfxvBxYLvZEemVaE94hsgKgHWdohTOaVOOZWgi xGohmcri7cWRGrF6Iri6cSaPdu8jihXO2ubaU5W6xSDdlKJIaFcBxPrLYqsKgjQIQc JW3UW0jHPQ5fg== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:10 +0200 Subject: [PATCH 10/14] drm/tidss: dispc: Switch VID_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-10-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5036; i=mripard@kernel.org; h=from:subject:message-id; bh=34elvM1s2AFsn1IFdmSPZJm2lK5jpkaAUPc9/D4aLec=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd91IuHz3/uupuwPpPWbqTc70KSr2D9u9euOjtBAOdW 2I3mh+Jd0xlYRDmZJAVU2R5IhN2enn74ioH+5U/YOawMoEMYeDiFICJ2H5nbDiQ/IF9otmj+Vq2 qXPPL1j79+7W1vnHpE5L7/64c8sZpb7+p9NlFqws3Wkh1H/5ol92yXHGhgeqckvei03V619++jQ jo/T3qt7MyriqnDjp/HIZDlWGteWfvj1p46z3vnB1Fnvk9GlsAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VID_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VID_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index d276ad881706057acabf6895f0c1f6758693504a..c22036d2b1dc2115245014d2e05= 72ac6bffa77ef 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -630,14 +630,14 @@ static u32 VID_REG_GET(struct dispc_device *dispc, u3= 2 hw_plane, u32 idx, { return FIELD_GET(mask, dispc_vid_read(dispc, hw_plane, idx)); } =20 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 = idx, - u32 val, u32 start, u32 end) + u32 val, u32 mask) { dispc_vid_write(dispc, hw_plane, idx, - FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), val, GENMASK(start, end))= ); + FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), val, mask)); } =20 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, u32 start, u32 end) { @@ -1756,11 +1756,12 @@ static void dispc_vid_csc_setup(struct dispc_device= *dispc, u32 hw_plane, } =20 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(9, 9)); } =20 /* SCALER */ =20 static u32 dispc_calc_fir_inc(u32 in, u32 out) @@ -2013,24 +2014,24 @@ static void dispc_vid_set_scaling(struct dispc_devi= ce *dispc, u32 hw_plane, struct dispc_scaling_params *sp, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_x, 7, 7); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, + GENMASK(7, 7)); =20 /* VERTICAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_y, 8, 8); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, + GENMASK(8, 8)); =20 /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; =20 /* VERTICAL 5-TAPS */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->five_taps, 21, 21); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, + GENMASK(21, 21)); =20 if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, sp->fir_xinc_uv); @@ -2116,11 +2117,11 @@ static void dispc_plane_set_pixel_format(struct dis= pc_device *dispc, =20 for (i =3D 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { if (dispc_color_formats[i].fourcc =3D=3D fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - 6, 1); + GENMASK(6, 1)); return; } } =20 WARN_ON(1); @@ -2294,19 +2295,20 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, 0xFF & (state->alpha >> 8)); =20 if (state->pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 28, 28); + GENMASK(28, 28)); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 28, 28); + GENMASK(28, 28)); } =20 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool ena= ble) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(0, 0)); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, @@ -2371,11 +2373,11 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) * Prefetch up to fifo high-threshold value to minimize the * possibility of underflows. Note that this means the PRELOAD * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_k3_plane_init(struct dispc_device *dispc) { @@ -2422,11 +2424,11 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); =20 /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_plane_init(struct dispc_device *dispc) { --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D5462989A4 for ; Wed, 30 Jul 2025 08:57:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865863; cv=none; b=R7rxPst9t7l8UnTyDP0qm92ouW0tm8UXzdu70aLkhn79YhEiDJuJxiI9rTvl6ZU3PI6/TBZKpD+GL6YC0FrFqqG37C34T+jJsHGcjYj7Rj5GlpytGQC5O8TGbwPfT+PXs91F4pjfzJP2gWqo/u1cGnLbOXCn2oeentj9E6JL1Q0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865863; c=relaxed/simple; bh=y/c4VTmZ0jPiB79L7NuH6C7jeoGGjEz6ZCtnpEsS0wk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OeWQvhfVYiqomGPA3emITmTDFsOYAvzFFRsROR1QpIWrnQtMbDKUPRjb8lGbCL4xxMh0GctPNOjpDCL6tKFzZ/qyhJptVttCdA4SC73xaJ8jxIrHP0TXxewcK1ApNS1r7uNAPIc7z1HrbF2e725D+z5g5c07FTCsbYTwr/RTlpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vmc62PIK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vmc62PIK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E705C4CEF5; Wed, 30 Jul 2025 08:57:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865863; bh=y/c4VTmZ0jPiB79L7NuH6C7jeoGGjEz6ZCtnpEsS0wk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Vmc62PIKmw6uls7QGZCtw0LLrEQvSk6IzRAfQxfgzw5WXLVQ8HNHBRg3ZjphsChT8 MUVGDy1xa/XBwvM5HyS7TlI4ILK+DBxPGGuMNdyRiX6nBe64wYDGpi305AtHsA2UhK Zv8RewpwOSmHiXodNqPBZsa+Zdw7vrC8K5EVg1/BLQwlbO9/K7jsrS0igSzqoy32t7 xQ4MeeI92iJ4WSLrE+9xkmKdO68msJ6jPJNb+7I4ls4NSBPNK8FWELo/1wq3BGvxNB mSl6NZ7rD83y22q0Q/VgAjl4isPEgucjkNAl5nWx477pKMKXV87F9lf2d6OX+Twsab XA96KQiTTA8Jw== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:11 +0200 Subject: [PATCH 11/14] drm/tidss: dispc: Switch VP_REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-11-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2197; i=mripard@kernel.org; h=from:subject:message-id; bh=y/c4VTmZ0jPiB79L7NuH6C7jeoGGjEz6ZCtnpEsS0wk=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd91JmNXJbZbesO/LgQm5En08Qy6G4k/kv9nyu1ubUW R+TvYexYyoLgzAng6yYIssTmbDTy9sXVznYr/wBM4eVCWQIAxenAEykcgFjwzKx53LsrNP2+5Vm pBY/mdzL/lDq9iZt1y6jmqxDb9emCT/ePlnJjp0v/T7DhhPMOe2ajA2TulLrZZavDuxl9NC6NOW d5WLnByxtLKy1vyymPWDjsgl7FRte612WXCa3umzF21KdHQA= X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VP_REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VP_REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index c22036d2b1dc2115245014d2e0572ac6bffa77ef..743ceca721691b3944d36bdd5e5= fb929d19ab82c 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -636,14 +636,13 @@ static void VID_REG_FLD_MOD(struct dispc_device *disp= c, u32 hw_plane, u32 idx, { dispc_vid_write(dispc, hw_plane, idx, FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), val, mask)); } =20 -static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, - u32 start, u32 end) +static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, u32 mas= k) { - return FIELD_GET(GENMASK(start, end), dispc_vp_read(dispc, vp, idx)); + return FIELD_GET(mask, dispc_vp_read(dispc, vp, idx)); } =20 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u3= 2 val, u32 start, u32 end) { @@ -1274,16 +1273,17 @@ void dispc_vp_unprepare(struct dispc_device *dispc,= u32 hw_videoport) } } =20 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) { - return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); + return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, + GENMASK(5, 5)); } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { - WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); + WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 983F9298CDC for ; Wed, 30 Jul 2025 08:57:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865866; cv=none; b=Q03iALAHpp0v7/tvWfAm8zZHEfkpF070atQdWTVY84qbNoA8B0WqXX32Dop6v+BWWRrXW70/oVTDsnl64VTYZZSshkpcxFbbhDDYNEtFck1GmsEPkNUWymDiE/VZLMPD60QefJWPCC348b0z0MreHj1+j/d3cKt+VPUvRY7HtgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865866; c=relaxed/simple; bh=bRiJmUbTP2CEaFqChGX+gLzEeA4bppzlIogVCcpgRyo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xe2aPlfwElqAYHu4IsZAAHu12YNxx5yJFQBSitqTeVM6lNAFhfdh3y0m4h0f+xMqjUDD38f5yVPDxPoL7/UfS0Z5suOVdGTHxUcagDH3IdPvAkhhqHnqIg988SwoDXdreexRt4cCMILebuNlfzO3kOmdawOLp7y4lb0/oeqdU/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lvmSNeQf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lvmSNeQf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BFE88C4CEF5; Wed, 30 Jul 2025 08:57:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865866; bh=bRiJmUbTP2CEaFqChGX+gLzEeA4bppzlIogVCcpgRyo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lvmSNeQfr5sCOAv6uVdS7m8FgOdk5DWbIwygX7/SmSCchR/D2u4H0swCQZZOBRLkX taDrhpypCNIbpdBoCjhto+a4+lsnyWFxxh8M2yBy+h5LhyFV7HBAjLO6InfrkM/hVB DYGD0yP9907NJj/P3pK/KeSXcnaRoojbGR7GQcw/vKp2FtpL6JKqmpqqGo/8hUKG5h uiRXq4kqJGN6SJDIPh/4W4wX0qYRCiJFPaXih0XXKFfXXIjAMY4ef97Okscd+AYyVV YzJE+4ligGxsEbQ2L0LXnZJparAT6oONbrq4Nn+mDcg3pS4sOiCS8MNO7pNlobJF4f VMFGpEFaqnHiw== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:12 +0200 Subject: [PATCH 12/14] drm/tidss: dispc: Switch VP_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-12-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5302; i=mripard@kernel.org; h=from:subject:message-id; bh=bRiJmUbTP2CEaFqChGX+gLzEeA4bppzlIogVCcpgRyo=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd91I4Ptk76H/SO7N1x9kbikuXtkTbnOl8nhFw6n6Rn 2C9rv+mjqksDMKcDLJiiixPZMJOL29fXOVgv/IHzBxWJpAhDFycAjCRqxcZazhUxC/stHVuNVn5 89CBBIaZqvoy+yIeHdnWODFpXt+JfROe7Lt7Rst1htIFzRuaq84s9GGs4dd4MOP627UPrr746fV 9Fd/yA6G2xt3+K8NnfroausN42XoZkSxR0e7579dlXJH4pZ15EQA= X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VP_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VP_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 743ceca721691b3944d36bdd5e5fb929d19ab82c..ba843248749d98f08a2393bc54f= 92f26bba4223d 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -642,14 +642,14 @@ static u32 VP_REG_GET(struct dispc_device *dispc, u32= vp, u32 idx, u32 mask) { return FIELD_GET(mask, dispc_vp_read(dispc, vp, idx)); } =20 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u3= 2 val, - u32 start, u32 end) + u32 mask) { dispc_vp_write(dispc, vp, idx, - FLD_MOD(dispc_vp_read(dispc, vp, idx), val, GENMASK(start, end))); + FLD_MOD(dispc_vp_read(dispc, vp, idx), val, mask)); } =20 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, u32 val, u32 start, u32 end) { @@ -1126,11 +1126,12 @@ static void dispc_set_num_datalines(struct dispc_de= vice *dispc, default: WARN_ON(1); v =3D 3; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, + GENMASK(10, 8)); } =20 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_vid= eoport, const struct dispc_bus_format *fmt) { @@ -1254,16 +1255,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) | FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1)); =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(0, 0)); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } =20 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) { @@ -1280,11 +1283,12 @@ bool dispc_vp_go_busy(struct dispc_device *dispc, u= 32 hw_videoport) } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(5, 5)); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) @@ -2454,11 +2458,11 @@ static void dispc_vp_init(struct dispc_device *disp= c) =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* Enable the gamma Shadow bit-field for all VPs*/ for (i =3D 0; i < dispc->feat->num_vps; i++) - VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2)); } =20 static void dispc_initial_config(struct dispc_device *dispc) { dispc_plane_init(dispc); @@ -2687,12 +2691,12 @@ static void dispc_k2g_vp_set_ctm(struct dispc_devic= e *dispc, u32 hw_videoport, dispc_k2g_cpr_from_ctm(ctm, &cpr); dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); cprenable =3D 1; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - cprenable, 15, 15); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable, + GENMASK(15, 15)); } =20 static s16 dispc_S31_32_to_s3_8(s64 coef) { u64 sign_bit =3D 1ULL << 63; @@ -2753,12 +2757,12 @@ static void dispc_k3_vp_set_ctm(struct dispc_device= *dispc, u32 hw_videoport, dispc_csc_from_ctm(ctm, &csc); dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); colorconvenable =3D 1; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - colorconvenable, 24, 24); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, + GENMASK(24, 24)); } =20 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, @@ -2905,11 +2909,12 @@ static void dispc_softreset_k2g(struct dispc_device= *dispc) dispc_set_irqenable(dispc, 0); dispc_read_and_clear_irqstatus(dispc); spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) - VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } =20 static int dispc_softreset(struct dispc_device *dispc) { u32 val; --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42C91293C4E for ; Wed, 30 Jul 2025 08:57:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865869; cv=none; b=r60MvKeWhJ2IDbD6KKEKKPfCtQPhd25xq6Nd4VLWP8/QLFhb5i8fExXeIkXLa+zjm70p1NgGtzsFMHLluQhczCGKxAHXvxfd+lAhuIm244e3SaPgeGTK1Fj1Y8oIbq1HBi8ACTIE88r8Uhb8bFhfmNO5/rEoy26VXKZLKMfNNgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753865869; c=relaxed/simple; bh=Or3Q43rgPLCeQ0Em2GhlqejtpCoF84H9jnqNFSiNMEc=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-13-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3314; i=mripard@kernel.org; h=from:subject:message-id; bh=Or3Q43rgPLCeQ0Em2GhlqejtpCoF84H9jnqNFSiNMEc=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd91J/KOXq/kqce8ywxd363e8FdY8m/rLwZVDNzhDP8 /9Wtm1Vx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZiITBFjnbb14bniF5KYjVfv 1p4izBqbJWty+9OLLa72E3d1TDt+ZeJU/pQ/lw50y1268FaB+4mHBmNDs8LbVSnmEql664rYZEO lBY+dXfuzzsGAVXpDXbH6ba5M5rCX7PsZN7dd0J9/O0Ld/x0A X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The OVR_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change OVR_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index ba843248749d98f08a2393bc54f92f26bba4223d..088a454271d45aef4ae264c78c6= 27c24d0ef0347 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -649,14 +649,14 @@ static void VP_REG_FLD_MOD(struct dispc_device *dispc= , u32 vp, u32 idx, u32 val, dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), val, mask)); } =20 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, - u32 val, u32 start, u32 end) + u32 val, u32 mask) { dispc_ovr_write(dispc, ovr, idx, - FLD_MOD(dispc_ovr_read(dispc, ovr, idx), val, GENMASK(start, end))); + FLD_MOD(dispc_ovr_read(dispc, ovr, idx), val, mask)); } =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { dispc_irq_t vp_stat =3D 0; @@ -1484,29 +1484,29 @@ static void dispc_am65x_ovr_set_plane(struct dispc_= device *dispc, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - x, 17, 6); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - y, 30, 19); + hw_id, GENMASK(4, 1)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, + GENMASK(17, 6)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, + GENMASK(30, 19)); } =20 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), - x, 13, 0); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), - y, 29, 16); + hw_id, GENMASK(4, 1)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, + GENMASK(13, 0)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y, + GENMASK(29, 16)); } =20 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { @@ -1537,11 +1537,11 @@ void dispc_ovr_enable_layer(struct dispc_device *di= spc, { if (dispc->feat->subrev =3D=3D DISPC_K2G) return; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - !!enable, 0, 0); + !!enable, GENMASK(0, 0)); } =20 /* CSC */ enum csc_ctm { CSC_RR, CSC_RG, CSC_RB, --=20 2.50.1 From nobody Sun Oct 5 20:15:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28865299A90 for ; Wed, 30 Jul 2025 08:57:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 30 Jul 2025 08:57:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753865872; bh=aBoNJIvy/es7TgTc92mwscadgmWoPkqKdh1SWsMgbM8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GISXFMoGPWLfzI2QAS0W5H5KueEDB6inSqGYwfAY5JcnDKhYGB3k6MeMF6UJZiwq8 Ta7qlIK6hfewUSuHxLSflDNe4E8FciLVD8OOspjfWEfvlwIRfgbwiCMhGnBbs6SVts vMGuhJqn7eN9yfw2U9/N2ArvbKvYzS6K5u4DdnZlrPoWG7JIiF3Z9QgzA9e/MYoru0 3RwmYxzDJpg33GE7bckoSdWZJWCEMTXkFspZ+MglfwIiSkQVZu/A/scQ8BupzI8gx9 +cAy8xFWQhcYGHe2Qzg2u6VnPRods5ezz2oMlEAu/T0konOqstonUtqYrVsr7j2d/j wk/v1oMDyoxfQ== From: Maxime Ripard Date: Wed, 30 Jul 2025 10:57:14 +0200 Subject: [PATCH 14/14] drm/tidss: dispc: Define field masks being used Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250730-drm-tidss-field-api-v1-14-a71ae8dd2782@kernel.org> References: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> In-Reply-To: <20250730-drm-tidss-field-api-v1-0-a71ae8dd2782@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=26927; i=mripard@kernel.org; h=from:subject:message-id; bh=aBoNJIvy/es7TgTc92mwscadgmWoPkqKdh1SWsMgbM8=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBmd91KF73yLXl8b+br//oMwHZdFkU2BdxfseZAbd1D42 9Z7ITLZHVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAiasmMDdPSn2vNOy2+ZAXr ZfmPe9oFKmpbU56mPGzz07OZHp39pFqzNMF4zmLP499cZu4pmFsqzVhnYy/2bsYNIc7u2dyqjmc Y9uixntZnujhVMiB6+aGjAkJMy6aJzzxzNfuIVOEOsS9BEbcB X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D Now that we have all the accessors taking masks, we can create defines for them and reuse them as needed. It makes the driver easier to read, less prone to consistency issues, and allows to reuse defines when needed. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 136 +++++++++++++++++----------= ---- drivers/gpu/drm/tidss/tidss_dispc_regs.h | 76 +++++++++++++++++ 2 files changed, 151 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 088a454271d45aef4ae264c78c627c24d0ef0347..0045e8b21982883c32a7b0df241= 26dc84978ffb6 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1127,11 +1127,11 @@ static void dispc_set_num_datalines(struct dispc_de= vice *dispc, WARN_ON(1); v =3D 3; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, - GENMASK(10, 8)); + DISPC_VP_CONTROL_DATALINES_MASK); } =20 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_vid= eoport, const struct dispc_bus_format *fmt) { @@ -1151,11 +1151,11 @@ static void dispc_enable_am65x_oldi(struct dispc_de= vice *dispc, u32 hw_videoport __func__, fmt->data_width); =20 oldi_cfg |=3D BIT(7); /* DEPOL */ =20 oldi_cfg =3D FLD_MOD(oldi_cfg, fmt->am65x_oldi_mode_reg_val, - GENMASK(3, 1)); + DISPC_VP_DSS_OLDI_CFG_MAP_MASK); =20 oldi_cfg |=3D BIT(12); /* SOFTRST */ =20 oldi_cfg |=3D BIT(0); /* ENABLE */ =20 @@ -1213,18 +1213,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, vfp =3D mode->vsync_start - mode->vdisplay; vsw =3D mode->vsync_end - mode->vsync_start; vbp =3D mode->vtotal - mode->vsync_end; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, - FIELD_PREP(GENMASK(7, 0), hsw - 1) | - FIELD_PREP(GENMASK(19, 8), hfp - 1) | - FIELD_PREP(GENMASK(31, 20), hbp - 1)); + FIELD_PREP(DISPC_VP_TIMING_H_SYNC_PULSE_MASK, hsw - 1) | + FIELD_PREP(DISPC_VP_TIMING_H_FRONT_PORCH_MASK, hfp - 1) | + FIELD_PREP(DISPC_VP_TIMING_H_BACK_PORCH_MASK, hbp - 1)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, - FIELD_PREP(GENMASK(7, 0), vsw - 1) | - FIELD_PREP(GENMASK(19, 8), vfp) | - FIELD_PREP(GENMASK(31, 20), vbp)); + FIELD_PREP(DISPC_VP_TIMING_V_SYNC_PULSE_MASK, vsw - 1) | + FIELD_PREP(DISPC_VP_TIMING_V_FRONT_PORCH_MASK, vfp) | + FIELD_PREP(DISPC_VP_TIMING_V_BACK_PORCH_MASK, vbp)); =20 ivs =3D !!(mode->flags & DRM_MODE_FLAG_NVSYNC); =20 ihs =3D !!(mode->flags & DRM_MODE_FLAG_NHSYNC); =20 @@ -1243,30 +1243,30 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, /* always use DE_HIGH for OLDI */ if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) ieo =3D false; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, - FIELD_PREP(GENMASK(18, 18), align) | - FIELD_PREP(GENMASK(17, 17), onoff) | - FIELD_PREP(GENMASK(16, 16), rf) | - FIELD_PREP(GENMASK(15, 15), ieo) | - FIELD_PREP(GENMASK(14, 14), ipc) | - FIELD_PREP(GENMASK(13, 13), ihs) | - FIELD_PREP(GENMASK(12, 12), ivs)); + FIELD_PREP(DISPC_VP_POL_FREQ_ALIGN_MASK, align) | + FIELD_PREP(DISPC_VP_POL_FREQ_ONOFF_MASK, onoff) | + FIELD_PREP(DISPC_VP_POL_FREQ_RF_MASK, rf) | + FIELD_PREP(DISPC_VP_POL_FREQ_IEO_MASK, ieo) | + FIELD_PREP(DISPC_VP_POL_FREQ_IPC_MASK, ipc) | + FIELD_PREP(DISPC_VP_POL_FREQ_IHS_MASK, ihs) | + FIELD_PREP(DISPC_VP_POL_FREQ_IVS_MASK, ivs)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, - FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) | - FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1)); + FIELD_PREP(DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK, mode->hdisplay - 1= ) | + FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK, mode->vdisplay - 1= )); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) { @@ -1277,18 +1277,19 @@ void dispc_vp_unprepare(struct dispc_device *dispc,= u32 hw_videoport) } =20 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) { return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, - GENMASK(5, 5)); + DISPC_VP_CONTROL_GOBIT_MASK); } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { - WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); + WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, + DISPC_VP_CONTROL_GOBIT_MASK)); VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, - GENMASK(5, 5)); + DISPC_VP_CONTROL_GOBIT_MASK); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) @@ -1484,29 +1485,29 @@ static void dispc_am65x_ovr_set_plane(struct dispc_= device *dispc, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, GENMASK(4, 1)); + hw_id, DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, - GENMASK(17, 6)); + DISPC_OVR_ATTRIBUTES_POSX_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, - GENMASK(30, 19)); + DISPC_OVR_ATTRIBUTES_POSY_MASK); } =20 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, GENMASK(4, 1)); + hw_id, DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, - GENMASK(13, 0)); + DISPC_OVR_ATTRIBUTES2_POSX_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y, - GENMASK(29, 16)); + DISPC_OVR_ATTRIBUTES2_POSY_MASK); } =20 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { @@ -1537,11 +1538,11 @@ void dispc_ovr_enable_layer(struct dispc_device *di= spc, { if (dispc->feat->subrev =3D=3D DISPC_K2G) return; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - !!enable, GENMASK(0, 0)); + !!enable, DISPC_OVR_ATTRIBUTES_ENABLE_MASK); } =20 /* CSC */ enum csc_ctm { CSC_RR, CSC_RG, CSC_RB, @@ -1761,11 +1762,11 @@ static void dispc_vid_csc_setup(struct dispc_device= *dispc, u32 hw_plane, =20 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, - GENMASK(9, 9)); + DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK); } =20 /* SCALER */ =20 static u32 dispc_calc_fir_inc(u32 in, u32 out) @@ -2019,23 +2020,23 @@ static void dispc_vid_set_scaling(struct dispc_devi= ce *dispc, struct dispc_scaling_params *sp, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, - GENMASK(7, 7)); + DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK); =20 /* VERTICAL RESIZE ENABLE */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, - GENMASK(8, 8)); + DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK); =20 /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; =20 /* VERTICAL 5-TAPS */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, - GENMASK(21, 21)); + DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK); =20 if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, sp->fir_xinc_uv); @@ -2121,11 +2122,11 @@ static void dispc_plane_set_pixel_format(struct dis= pc_device *dispc, =20 for (i =3D 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { if (dispc_color_formats[i].fourcc =3D=3D fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - GENMASK(6, 1)); + DISPC_VID_ATTRIBUTES_FORMAT_MASK); return; } } =20 WARN_ON(1); @@ -2243,11 +2244,12 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32); dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff); dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32); =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, - (scale.in_w - 1) | ((scale.in_h - 1) << 16)); + FIELD_PREP(DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK, scale.in_h - 1) | + FIELD_PREP(DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK, scale.in_w - 1)); =20 /* For YUV422 format we use the macropixel size for pixel inc */ if (fourcc =3D=3D DRM_FORMAT_YUYV || fourcc =3D=3D DRM_FORMAT_UYVY) dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, pixinc(scale.xinc, cpp * 2)); @@ -2280,12 +2282,14 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, cpp_uv)); } =20 if (!lite) { dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, - (state->crtc_w - 1) | - ((state->crtc_h - 1) << 16)); + FIELD_PREP(DISPC_VID_SIZE_SIZEY_MASK, + state->crtc_h - 1) | + FIELD_PREP(DISPC_VID_SIZE_SIZEX_MASK, + state->crtc_w - 1)); =20 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); } =20 /* enable YUV->RGB color conversion */ @@ -2295,56 +2299,63 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, } else { dispc_vid_csc_enable(dispc, hw_plane, false); } =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, - 0xFF & (state->alpha >> 8)); + FIELD_PREP(DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK, + state->alpha >> 8)); =20 if (state->pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - GENMASK(28, 28)); + DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - GENMASK(28, 28)); + DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK); } =20 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool ena= ble) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, - GENMASK(0, 0)); + DISPC_VID_ATTRIBUTES_ENABLE_MASK); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, - GENMASK(15, 0)); + DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK); } =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, - FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); + FIELD_PREP(DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK, high) | + FIELD_PREP(DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK, low)); } =20 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, - FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); + FIELD_PREP(DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK, + high) | + FIELD_PREP(DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK, + low)); } =20 static void dispc_k2g_plane_init(struct dispc_device *dispc) { unsigned int hw_plane; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2377,11 +2388,11 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) * Prefetch up to fifo high-threshold value to minimize the * possibility of underflows. Note that this means the PRELOAD * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - GENMASK(19, 19)); + DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK); } } =20 static void dispc_k3_plane_init(struct dispc_device *dispc) { @@ -2389,17 +2400,19 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) u32 cba_lo_pri =3D 1; u32 cba_hi_pri =3D 0; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0)); - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3)); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, DSS_CBA_CFG_PRI_LO_MASK); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, DSS_CBA_CFG_PRI_HI_MASK); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2428,11 +2441,11 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); =20 /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - GENMASK(19, 19)); + DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK); } } =20 static void dispc_plane_init(struct dispc_device *dispc) { @@ -2458,23 +2471,24 @@ static void dispc_vp_init(struct dispc_device *disp= c) =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* Enable the gamma Shadow bit-field for all VPs*/ for (i =3D 0; i < dispc->feat->num_vps; i++) - VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2)); + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, + DISPC_VP_CONFIG_GAMMAENABLE_MASK); } =20 static void dispc_initial_config(struct dispc_device *dispc) { dispc_plane_init(dispc); dispc_vp_init(dispc); =20 /* Note: Hardcoded DPI routing on J721E for now */ if (dispc->feat->subrev =3D=3D DISPC_J721E) { dispc_write(dispc, DISPC_CONNECTIONS, - FIELD_PREP(GENMASK(3, 0), 2) | /* VP1 to DPI0 */ - FIELD_PREP(GENMASK(7, 4), 8) /* VP3 to DPI1 */ + FIELD_PREP(DISPC_CONNECTIONS_DPI_0_CONN_MASK, 2) | /* VP1 to DPI0 = */ + FIELD_PREP(DISPC_CONNECTIONS_DPI_1_CONN_MASK, 8) /* VP3 to DPI1 */ ); } } =20 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, @@ -2692,11 +2706,11 @@ static void dispc_k2g_vp_set_ctm(struct dispc_devic= e *dispc, u32 hw_videoport, dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); cprenable =3D 1; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable, - GENMASK(15, 15)); + DISPC_VP_CONFIG_CPR_MASK); } =20 static s16 dispc_S31_32_to_s3_8(s64 coef) { u64 sign_bit =3D 1ULL << 63; @@ -2758,11 +2772,11 @@ static void dispc_k3_vp_set_ctm(struct dispc_device= *dispc, u32 hw_videoport, dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); colorconvenable =3D 1; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, - GENMASK(24, 24)); + DISPC_VP_CONFIG_COLORCONVENABLE_MASK); } =20 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, @@ -2813,11 +2827,11 @@ int dispc_runtime_resume(struct dispc_device *dispc) { dev_dbg(dispc->dev, "resume\n"); =20 clk_prepare_enable(dispc->fclk); =20 - if (REG_GET(dispc, DSS_SYSSTATUS, GENMASK(0, 0)) =3D=3D 0) + if (REG_GET(dispc, DSS_SYSSTATUS, DSS_SYSSTATUS_DISPC_FUNC_RESETDONE) =3D= =3D 0) dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); =20 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", dispc_read(dispc, DSS_REVISION)); =20 @@ -2832,11 +2846,11 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, GENMASK(5, 5)), REG_GET(dispc, DSS_SYSSTATUS, GENMASK(6, 6)), REG_GET(dispc, DSS_SYSSTATUS, GENMASK(7, 7))); =20 dev_dbg(dispc->dev, "DISPC IDLE %d\n", - REG_GET(dispc, DSS_SYSSTATUS, GENMASK(9, 9))); + REG_GET(dispc, DSS_SYSSTATUS, DSS_SYSSTATUS_DISPC_IDLE_STATUS)); =20 dispc_initial_config(dispc); =20 dispc->is_enabled =3D true; =20 @@ -2910,11 +2924,11 @@ static void dispc_softreset_k2g(struct dispc_device= *dispc) dispc_read_and_clear_irqstatus(dispc); spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 static int dispc_softreset(struct dispc_device *dispc) { u32 val; @@ -2924,11 +2938,11 @@ static int dispc_softreset(struct dispc_device *dis= pc) dispc_softreset_k2g(dispc); return 0; } =20 /* Soft reset */ - REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1)); + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, DSS_SYSCONFIG_SOFTRESET_MASK); /* Wait for reset to complete */ ret =3D readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, val, val & 1, 100, 5000); if (ret) { dev_err(dispc->dev, "failed to reset dispc\n"); diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tid= ss/tidss_dispc_regs.h index 50a3f28250efe61f1d98a456bf8907000109411c..382027dddce894b3b7d11172e23= bf11883e25958 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -54,11 +54,16 @@ enum dispc_common_regs { =20 #define REG(r) (dispc_common_regmap[r ## _OFF]) =20 #define DSS_REVISION REG(DSS_REVISION) #define DSS_SYSCONFIG REG(DSS_SYSCONFIG) +#define DSS_SYSCONFIG_SOFTRESET_MASK GENMASK(1, 1) + #define DSS_SYSSTATUS REG(DSS_SYSSTATUS) +#define DSS_SYSSTATUS_DISPC_IDLE_STATUS GENMASK(9, 9) +#define DSS_SYSSTATUS_DISPC_FUNC_RESETDONE GENMASK(0, 0) + #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI) #define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW) #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS) #define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET) #define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR) @@ -68,13 +73,19 @@ enum dispc_common_regs { #define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4) #define WB_IRQENABLE REG(WB_IRQENABLE) #define WB_IRQSTATUS REG(WB_IRQSTATUS) =20 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE) +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK GENMASK(6, 6) +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK GENMASK(1, 0) + #define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE) #define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER) #define DSS_CBA_CFG REG(DSS_CBA_CFG) +#define DSS_CBA_CFG_PRI_HI_MASK GENMASK(5, 3) +#define DSS_CBA_CFG_PRI_LO_MASK GENMASK(2, 0) + #define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL) #define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS) #define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE) #define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE) =20 @@ -86,10 +97,13 @@ enum dispc_common_regs { #define FBDC_REVISION_6 REG(FBDC_REVISION_6) #define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) #define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) #define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) #define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS) +#define DISPC_CONNECTIONS_DPI_1_CONN_MASK GENMASK(7, 4) +#define DISPC_CONNECTIONS_DPI_0_CONN_MASK GENMASK(3, 0) + #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1) #define DISPC_MSS_VP3 REG(DISPC_MSS_VP3) =20 /* VID */ =20 @@ -100,17 +114,31 @@ enum dispc_common_regs { #define DISPC_VID_ACCUV_0 0x10 #define DISPC_VID_ACCUV_1 0x14 #define DISPC_VID_ACCUV2_0 0x18 #define DISPC_VID_ACCUV2_1 0x1c #define DISPC_VID_ATTRIBUTES 0x20 +#define DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK GENMASK(28, 28) +#define DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK GENMASK(21, 21) +#define DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK GENMASK(19, 19) +#define DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK GENMASK(9, 9) +#define DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK GENMASK(8, 8) +#define DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK GENMASK(7, 7) +#define DISPC_VID_ATTRIBUTES_FORMAT_MASK GENMASK(6, 1) +#define DISPC_VID_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0) + #define DISPC_VID_ATTRIBUTES2 0x24 #define DISPC_VID_BA_0 0x28 #define DISPC_VID_BA_1 0x2c #define DISPC_VID_BA_UV_0 0x30 #define DISPC_VID_BA_UV_1 0x34 #define DISPC_VID_BUF_SIZE_STATUS 0x38 +#define DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK GENMASK(15, 0) + #define DISPC_VID_BUF_THRESHOLD 0x3c +#define DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK GENMASK(31, 16) +#define DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK GENMASK(15, 0) + #define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) =20 #define DISPC_VID_FIRH 0x5c #define DISPC_VID_FIRH2 0x60 #define DISPC_VID_FIRV 0x64 @@ -135,19 +163,30 @@ enum dispc_common_regs { #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) #define DISPC_VID_FIR_COEFS_V12_C 0x1bc #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) =20 #define DISPC_VID_GLOBAL_ALPHA 0x1fc +#define DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK GENMASK(7, 0) + #define DISPC_VID_K2G_IRQENABLE 0x200 /* K2G */ #define DISPC_VID_K2G_IRQSTATUS 0x204 /* K2G */ #define DISPC_VID_MFLAG_THRESHOLD 0x208 +#define DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK GENMASK(31, 16) +#define DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK GENMASK(15, 0) + #define DISPC_VID_PICTURE_SIZE 0x20c +#define DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK GENMASK(27, 16) +#define DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK GENMASK(11, 0) + #define DISPC_VID_PIXEL_INC 0x210 #define DISPC_VID_K2G_POSITION 0x214 /* K2G */ #define DISPC_VID_PRELOAD 0x218 #define DISPC_VID_ROW_INC 0x21c #define DISPC_VID_SIZE 0x220 +#define DISPC_VID_SIZE_SIZEY_MASK GENMASK(27, 16) +#define DISPC_VID_SIZE_SIZEX_MASK GENMASK(11, 0) + #define DISPC_VID_BA_EXT_0 0x22c #define DISPC_VID_BA_EXT_1 0x230 #define DISPC_VID_BA_UV_EXT_0 0x234 #define DISPC_VID_BA_UV_EXT_1 0x238 #define DISPC_VID_CSC_COEF7 0x23c @@ -171,15 +210,31 @@ enum dispc_common_regs { #define DISPC_OVR_TRANS_COLOR_MAX 0x10 #define DISPC_OVR_TRANS_COLOR_MAX2 0x14 #define DISPC_OVR_TRANS_COLOR_MIN 0x18 #define DISPC_OVR_TRANS_COLOR_MIN2 0x1c #define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) +#define DISPC_OVR_ATTRIBUTES_POSY_MASK GENMASK(30, 19) +#define DISPC_OVR_ATTRIBUTES_POSX_MASK GENMASK(17, 6) +#define DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK GENMASK(4, 1) +#define DISPC_OVR_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0) + #define DISPC_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ +#define DISPC_OVR_ATTRIBUTES2_POSY_MASK GENMASK(29, 16) +#define DISPC_OVR_ATTRIBUTES2_POSX_MASK GENMASK(13, 0) + /* VP */ =20 #define DISPC_VP_CONFIG 0x0 +#define DISPC_VP_CONFIG_COLORCONVENABLE_MASK GENMASK(24, 24) +#define DISPC_VP_CONFIG_CPR_MASK GENMASK(15, 15) +#define DISPC_VP_CONFIG_GAMMAENABLE_MASK GENMASK(2, 2) + #define DISPC_VP_CONTROL 0x4 +#define DISPC_VP_CONTROL_DATALINES_MASK GENMASK(10, 8) +#define DISPC_VP_CONTROL_GOBIT_MASK GENMASK(5, 5) +#define DISPC_VP_CONTROL_ENABLE_MASK GENMASK(0, 0) + #define DISPC_VP_CSC_COEF0 0x8 #define DISPC_VP_CSC_COEF1 0xc #define DISPC_VP_CSC_COEF2 0x10 #define DISPC_VP_DATA_CYCLE_0 0x14 #define DISPC_VP_DATA_CYCLE_1 0x18 @@ -187,13 +242,32 @@ enum dispc_common_regs { #define DISPC_VP_K2G_IRQENABLE 0x3c /* K2G */ #define DISPC_VP_K2G_IRQSTATUS 0x40 /* K2G */ #define DISPC_VP_DATA_CYCLE_2 0x1c #define DISPC_VP_LINE_NUMBER 0x44 #define DISPC_VP_POL_FREQ 0x4c +#define DISPC_VP_POL_FREQ_ALIGN_MASK GENMASK(18, 18) +#define DISPC_VP_POL_FREQ_ONOFF_MASK GENMASK(17, 17) +#define DISPC_VP_POL_FREQ_RF_MASK GENMASK(16, 16) +#define DISPC_VP_POL_FREQ_IEO_MASK GENMASK(15, 15) +#define DISPC_VP_POL_FREQ_IPC_MASK GENMASK(14, 14) +#define DISPC_VP_POL_FREQ_IHS_MASK GENMASK(13, 13) +#define DISPC_VP_POL_FREQ_IVS_MASK GENMASK(12, 12) + #define DISPC_VP_SIZE_SCREEN 0x50 +#define DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK GENMASK(11, 0) +#define DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK GENMASK(27, 16) + #define DISPC_VP_TIMING_H 0x54 +#define DISPC_VP_TIMING_H_SYNC_PULSE_MASK GENMASK(7, 0) +#define DISPC_VP_TIMING_H_FRONT_PORCH_MASK GENMASK(19, 8) +#define DISPC_VP_TIMING_H_BACK_PORCH_MASK GENMASK(31, 20) + #define DISPC_VP_TIMING_V 0x58 +#define DISPC_VP_TIMING_V_SYNC_PULSE_MASK GENMASK(7, 0) +#define DISPC_VP_TIMING_V_FRONT_PORCH_MASK GENMASK(19, 8) +#define DISPC_VP_TIMING_V_BACK_PORCH_MASK GENMASK(31, 20) + #define DISPC_VP_CSC_COEF3 0x5c #define DISPC_VP_CSC_COEF4 0x60 #define DISPC_VP_CSC_COEF5 0x64 #define DISPC_VP_CSC_COEF6 0x68 #define DISPC_VP_CSC_COEF7 0x6c @@ -218,10 +292,12 @@ enum dispc_common_regs { #define DISPC_VP_SAFETY_SIZE_2 0xf8 #define DISPC_VP_SAFETY_SIZE_3 0xfc #define DISPC_VP_SAFETY_LFSR_SEED 0x110 #define DISPC_VP_GAMMA_TABLE 0x120 #define DISPC_VP_DSS_OLDI_CFG 0x160 +#define DISPC_VP_DSS_OLDI_CFG_MAP_MASK GENMASK(3, 1) + #define DISPC_VP_DSS_OLDI_STATUS 0x164 #define DISPC_VP_DSS_OLDI_LB 0x168 #define DISPC_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ #define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ #define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ --=20 2.50.1