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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2025 20:48:07.8840 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d615fda6-7a9b-436f-a4e4-08ddcee1393c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6914 Content-Type: text/plain; charset="utf-8" Starting with Zen6, AMD's Scalable MCA systems will incorporate two new bits in MCA_STATUS and MCA_CONFIG MSRs. These bits will indicate if a valid System Physical Address (SPA) is present in MCA_ADDR. PhysAddrValidSupported bit (MCA_CONFIG[11]) serves as the architectural indicator and states if PhysAddrV bit (MCA_STATUS[54]) is Reserved or if it indicates validity of SPA in MCA_ADDR. PhysAddrV bit (MCA_STATUS[54]) advertises if MCA_ADDR contains valid SPA or if it is implementation specific. Signed-off-by: Avadhut Naik --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/amd.c | 16 +++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6c77c03139f7..387cf250525f 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -48,6 +48,7 @@ =20 /* AMD-specific bits */ #define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */ +#define MCI_STATUS_PADDRVAL BIT_ULL(54) /* Valid System Physical Address = */ #define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */ #define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred ex= ception */ #define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */ @@ -62,6 +63,7 @@ */ #define MCI_CONFIG_MCAX 0x1 #define MCI_CONFIG_FRUTEXT BIT_ULL(9) +#define MCI_CONFIG_PAVALID BIT_ULL(11) #define MCI_IPID_MCATYPE 0xFFFF0000 #define MCI_IPID_HWID 0xFFF =20 diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 5c4eb28c3ac9..6ac222aec28d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -748,9 +748,9 @@ bool amd_mce_is_memory_error(struct mce *m) } =20 /* - * AMD systems do not have an explicit indicator that the value in MCA_ADD= R is - * a system physical address. Therefore, individual cases need to be detec= ted. - * Future cases and checks will be added as needed. + * Some AMD systems have an explicit indicator that the value in MCA_ADDR = is a + * system physical address. Individual cases though, need to be detected f= or + * other systems. Future cases will be added as needed. * * 1) General case * a) Assume address is not usable. @@ -764,11 +764,21 @@ bool amd_mce_is_memory_error(struct mce *m) * a) Reported in legacy bank 4 with extended error code (XEC) 8. * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefor= e, * this bit should not be checked. + * 4) MCI_STATUS_PADDRVAL is set + * a)Will provide a valid system physical address. * * NOTE: SMCA UMC memory errors fall into case #1. */ bool amd_mce_usable_address(struct mce *m) { + u64 smca_config; + + rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), smca_config); + if (smca_config & MCI_CONFIG_PAVALID) { + if(m->status & MCI_STATUS_PADDRVAL) + return true; + return false; + } /* Check special northbridge case 3) first. */ if (!mce_flags.smca) { if (legacy_mce_is_memory_error(m)) base-commit: d69139008b6dcd9c18483e956f61d187b0c214a2 --=20 2.43.0