From nobody Sun Oct 5 22:01:49 2025 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBA50298990 for ; Tue, 29 Jul 2025 15:38:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803516; cv=none; b=Zz4n9LiAqqCe1xq6agRo1egdz5WcKUj5AbX5DrY7abMhSZBpW59x0BTpTXx3S22pyTPpuGttAPL35XCw3scI8AAQ2y10AcIgMGdTy3yFnhYUp/CzlcSoKH6fjjXMefk0e4OlMyjxCnKtflqzknoaWX5UABbiQ6TP0f3B4hh2hHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803516; c=relaxed/simple; bh=35gOphLUnY+QgbjDNDrxI4suISxXiDI6dzAEOVeM/eQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VnKyFlxUP/9h9VzvrDabHjuCxNtQir2a5sowq2y5K0PXmwLIF1OVU4plGxhQRG3f1ehPLcLXPZaNWiyRaKHOn4HU9T8m+J5FD4w0upgKQLs9DODF4GyurvhsCd6f8cd3Zt2AhllPfPuELDurKL991wOYQ4d9NxTYDpOw3vk3Pwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4brzsB3zkhzSjYy; Tue, 29 Jul 2025 23:33:50 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id 734B1180487; Tue, 29 Jul 2025 23:38:25 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:25 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:24 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 1/8] drivers/perf: hisi: Relax the event ID check in the framework Date: Tue, 29 Jul 2025 23:38:16 +0800 Message-ID: <20250729153823.2026154-2-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" From: Yicong Yang Event ID is only using the attr::config bit [7, 0] but we check the event range using the whole 64bit field. It blocks the usage of the resident field of attr::config. Relax the check by only using the bit [7, 0]. Signed-off-by: Yicong Yang Signed-off-by: Yushan Wang Reviewed-by: Jonathan Csmeron --- drivers/perf/hisilicon/hisi_uncore_pmu.c | 2 +- drivers/perf/hisilicon/hisi_uncore_pmu.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisili= con/hisi_uncore_pmu.c index ef058b1dd509..3050899ddf17 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -234,7 +234,7 @@ int hisi_uncore_pmu_event_init(struct perf_event *event) return -EINVAL; =20 hisi_pmu =3D to_hisi_pmu(event->pmu); - if (event->attr.config > hisi_pmu->check_event) + if ((event->attr.config & HISI_EVENTID_MASK) > hisi_pmu->check_event) return -EINVAL; =20 if (hisi_pmu->on_cpu =3D=3D -1) diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisili= con/hisi_uncore_pmu.h index f4fed2544877..50a97e79076a 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.h +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h @@ -43,7 +43,8 @@ return FIELD_GET(GENMASK_ULL(hi, lo), event->attr.config); \ } =20 -#define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff) +#define HISI_EVENTID_MASK 0xff +#define HISI_GET_EVENTID(ev) ((ev)->hw.config_base & HISI_EVENTID_MASK) =20 #define HISI_PMU_EVTYPE_BITS 8 #define HISI_PMU_EVTYPE_SHIFT(idx) ((idx) % 4 * HISI_PMU_EVTYPE_BITS) --=20 2.33.0 From nobody Sun Oct 5 22:01:49 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EE07285CBD for ; Tue, 29 Jul 2025 15:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803511; cv=none; b=a6FHJ3VNgyfMpVGkwPbvHcki0w0F704yLkqeWVqckU58njW59KqFygBvn4QSfUXUi+wVkfyEWU+d2bEiBLj5dI32XnNqyHv0bx6WNrU11cotj/QikNLVlYWwT9v+axWAyE51JNSDI637h9ynla0pgvvASpGFOcmv3iVKdt1+9VI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803511; c=relaxed/simple; bh=vttgwWfL3raPSueJCiRBOF7pniAdRlAuR26xPSS6TpI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BjuZPX5xLpLl/PLnTvGlcnoa63wRTRAh3dEQtwstm1r8NcM03e7nYQ4SVkQ2fst9XGXngjhqX5QYeDHUs1hZChWhEAEEtVW9mCJuv8ndqLlIqqZR9OfgJ7InsLqshSou1hj/yCKosfMPR7c2Paobq19w4nf3TE46fxlZQtUaYJ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4brzvm3Yqnz2RVvl; Tue, 29 Jul 2025 23:36:04 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id CE6411A0188; Tue, 29 Jul 2025 23:38:25 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:25 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:25 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 2/8] drivers/perf: hisi: Export hisi_uncore_pmu_isr() Date: Tue, 29 Jul 2025 23:38:17 +0800 Message-ID: <20250729153823.2026154-3-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" From: Yicong Yang Currently Uncore PMU framework assume one PMU device only have one interrupt and will help register the interrupt handler. It cannot support a PMU with multiple interrupt resources. An uncore PMU may have multiple interrupts that can share the same handler. Export hisi_uncore_pmu_isr() to allow drivers register the irq handler by their own routine. Signed-off-by: Yicong Yang Signed-off-by: Yushan Wang Reviewed-by: Jonathan Cameron --- drivers/perf/hisilicon/hisi_uncore_pmu.c | 3 ++- drivers/perf/hisilicon/hisi_uncore_pmu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisili= con/hisi_uncore_pmu.c index 3050899ddf17..ff20ad54f51b 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -149,7 +149,7 @@ static void hisi_uncore_pmu_clear_event_idx(struct hisi= _pmu *hisi_pmu, int idx) clear_bit(idx, hisi_pmu->pmu_events.used_mask); } =20 -static irqreturn_t hisi_uncore_pmu_isr(int irq, void *data) +irqreturn_t hisi_uncore_pmu_isr(int irq, void *data) { struct hisi_pmu *hisi_pmu =3D data; struct perf_event *event; @@ -178,6 +178,7 @@ static irqreturn_t hisi_uncore_pmu_isr(int irq, void *d= ata) =20 return IRQ_HANDLED; } +EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_isr, "HISI_PMU"); =20 int hisi_uncore_pmu_init_irq(struct hisi_pmu *hisi_pmu, struct platform_device *pdev) diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisili= con/hisi_uncore_pmu.h index 50a97e79076a..40aac70352e9 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.h +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h @@ -163,6 +163,7 @@ int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struc= t hlist_node *node); ssize_t hisi_uncore_pmu_identifier_attr_show(struct device *dev, struct device_attribute *attr, char *page); +irqreturn_t hisi_uncore_pmu_isr(int irq, void *data); int hisi_uncore_pmu_init_irq(struct hisi_pmu *hisi_pmu, struct platform_device *pdev); void hisi_uncore_pmu_init_topology(struct hisi_pmu *hisi_pmu, struct devic= e *dev); --=20 2.33.0 From nobody Sun Oct 5 22:01:49 2025 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D46E293C73 for ; Tue, 29 Jul 2025 15:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803511; cv=none; b=OIjGxMbeNkvZY2NROQwSIhJS4l8GnVJ+xDosfhrkipX3OqDXi3AbCfVo7V0X8t+SnMSYKR0ENaE8NHXU0rur0t9bWvO39Zf+gse/DuQlwugpXUANVhPHoqtxg5wglxn31ybbsGzWwv1fqRyhhhKnkUdCc63WHR2FezbYwe8Wr08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803511; c=relaxed/simple; bh=FKpOGwbI8tj2329sOvIyP8dSaq6hykXnLCSjpTE7Pt0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ej7OIlpVUfQH9zCABurkXoyz7YQgEVol8D+pXzPb8Q2nP2mogErHRoTCHM1nkT/YHVMRw3bV2Eo4eNwVxhyfD1Lh3RBi2z9noceUB7XTTLsyOP4M0Nscywee6JriMMs5zHcfFZ39vb//VNTtymOCDymkXUJTy3LgoOJ0dTAgqXU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4brzvL6vYtz1R8qr; Tue, 29 Jul 2025 23:35:42 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id 4A243140155; Tue, 29 Jul 2025 23:38:26 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:26 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:25 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 3/8] drivers/perf: hisi: Simplify the probe process of each L3C PMU version Date: Tue, 29 Jul 2025 23:38:18 +0800 Message-ID: <20250729153823.2026154-4-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" From: Yicong Yang Version 1 and 2 of L3C PMU also use different HID. Make use of struct acpi_device_id::driver_data for version specific information rather than judge the version register. This will help to simplify the probe process and also a bit easier for extension. Signed-off-by: Yicong Yang Signed-off-by: Yushan Wang Reviewed-by: Jonathan Cameron --- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 43 ++++++++++++-------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hi= silicon/hisi_uncore_l3c_pmu.c index 412fc3a97963..db683dd7375c 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -345,13 +345,6 @@ static void hisi_l3c_pmu_clear_int_status(struct hisi_= pmu *l3c_pmu, int idx) writel(1 << idx, l3c_pmu->base + L3C_INT_CLEAR); } =20 -static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] =3D { - { "HISI0213", }, - { "HISI0214", }, - {} -}; -MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match); - static int hisi_l3c_pmu_init_data(struct platform_device *pdev, struct hisi_pmu *l3c_pmu) { @@ -371,6 +364,10 @@ static int hisi_l3c_pmu_init_data(struct platform_devi= ce *pdev, return -EINVAL; } =20 + l3c_pmu->dev_info =3D device_get_match_data(&pdev->dev); + if (!l3c_pmu->dev_info) + return -ENODEV; + l3c_pmu->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(l3c_pmu->base)) { dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n"); @@ -457,6 +454,18 @@ static const struct attribute_group *hisi_l3c_pmu_v2_a= ttr_groups[] =3D { NULL }; =20 +static const struct hisi_pmu_dev_info hisi_l3c_pmu_v1 =3D { + .attr_groups =3D hisi_l3c_pmu_v1_attr_groups, + .counter_bits =3D 48, + .check_event =3D L3C_V1_NR_EVENTS, +}; + +static const struct hisi_pmu_dev_info hisi_l3c_pmu_v2 =3D { + .attr_groups =3D hisi_l3c_pmu_v2_attr_groups, + .counter_bits =3D 64, + .check_event =3D L3C_V2_NR_EVENTS, +}; + static const struct hisi_uncore_ops hisi_uncore_l3c_ops =3D { .write_evtype =3D hisi_l3c_pmu_write_evtype, .get_event_idx =3D hisi_uncore_pmu_get_event_idx, @@ -487,16 +496,9 @@ static int hisi_l3c_pmu_dev_probe(struct platform_devi= ce *pdev, if (ret) return ret; =20 - if (l3c_pmu->identifier >=3D HISI_PMU_V2) { - l3c_pmu->counter_bits =3D 64; - l3c_pmu->check_event =3D L3C_V2_NR_EVENTS; - l3c_pmu->pmu_events.attr_groups =3D hisi_l3c_pmu_v2_attr_groups; - } else { - l3c_pmu->counter_bits =3D 48; - l3c_pmu->check_event =3D L3C_V1_NR_EVENTS; - l3c_pmu->pmu_events.attr_groups =3D hisi_l3c_pmu_v1_attr_groups; - } - + l3c_pmu->pmu_events.attr_groups =3D l3c_pmu->dev_info->attr_groups; + l3c_pmu->counter_bits =3D l3c_pmu->dev_info->counter_bits; + l3c_pmu->check_event =3D l3c_pmu->dev_info->check_event; l3c_pmu->num_counters =3D L3C_NR_COUNTERS; l3c_pmu->ops =3D &hisi_uncore_l3c_ops; l3c_pmu->dev =3D &pdev->dev; @@ -554,6 +556,13 @@ static void hisi_l3c_pmu_remove(struct platform_device= *pdev) &l3c_pmu->node); } =20 +static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] =3D { + { "HISI0213", (kernel_ulong_t)&hisi_l3c_pmu_v1 }, + { "HISI0214", (kernel_ulong_t)&hisi_l3c_pmu_v2 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match); + static struct platform_driver hisi_l3c_pmu_driver =3D { .driver =3D { .name =3D "hisi_l3c_pmu", --=20 2.33.0 From nobody Sun Oct 5 22:01:49 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F4AB293C6C for ; Tue, 29 Jul 2025 15:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803510; cv=none; b=Ez0DqYFMV8hs/XdVv7wch2bT/FVAAudDEYrX/hp39MbDtXLcUz9lOHWSflWquQpzympT2L0ACvVW/56djot/iyaNI+A8IbSv4ateB8rXMFpcBgnUlZS++7XvuGxy9TjSU8Fyp38kaOcroE00/zsfftJuvYWG6pRaSx+noDawmsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803510; c=relaxed/simple; bh=/PL1vpm9TYOAWALaGnBy2T0QsBNqW7Bo0yWNFVB6jQw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nOVguQRdHus5Cse6sjY/QcH6Oh08Jfwe2664ROqMP/yIpB9522GQKjWSUfpZ/56X3/JbJFrCGsyygGSnXlksNjm5KLtfUWXarkHrpC5adB6lYhN+pbqEmZW2KH55LGKHAM1PboTOC/L4exptmEkBNQKyJpfjzzGWRvY5lR1iPGI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4brzvn2GhLz2RVvT; Tue, 29 Jul 2025 23:36:05 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id A21F118005F; Tue, 29 Jul 2025 23:38:26 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:26 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:25 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 4/8] drivers/perf: hisi: Extract the event filter check of L3C PMU Date: Tue, 29 Jul 2025 23:38:19 +0800 Message-ID: <20250729153823.2026154-5-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" From: Yicong Yang L3C PMU has 4 filter options which are sharing perf_event_attr::config1. Driver will check config1 to see whether a certain event has a filter setting. It'll be incorrect if we make use of other bits in config1 for non-filter options. So check whether each filter options are set directly in a separate function instead. Signed-off-by: Yicong Yang Signed-off-by: Yushan Wang Reviewed-by: Jonathan Cameron --- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hi= silicon/hisi_uncore_l3c_pmu.c index db683dd7375c..a372dd2c07b5 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -204,9 +204,15 @@ static void hisi_l3c_pmu_clear_core_tracetag(struct pe= rf_event *event) } } =20 +static bool hisi_l3c_pmu_have_filter(struct perf_event *event) +{ + return hisi_get_tt_req(event) || hisi_get_tt_core(event) || + hisi_get_datasrc_cfg(event) || hisi_get_datasrc_skt(event); +} + static void hisi_l3c_pmu_enable_filter(struct perf_event *event) { - if (event->attr.config1 !=3D 0x0) { + if (hisi_l3c_pmu_have_filter(event)) { hisi_l3c_pmu_config_req_tracetag(event); hisi_l3c_pmu_config_core_tracetag(event); hisi_l3c_pmu_config_ds(event); @@ -215,7 +221,7 @@ static void hisi_l3c_pmu_enable_filter(struct perf_even= t *event) =20 static void hisi_l3c_pmu_disable_filter(struct perf_event *event) { - if (event->attr.config1 !=3D 0x0) { + if (hisi_l3c_pmu_have_filter(event)) { hisi_l3c_pmu_clear_ds(event); hisi_l3c_pmu_clear_core_tracetag(event); hisi_l3c_pmu_clear_req_tracetag(event); --=20 2.33.0 From nobody Sun Oct 5 22:01:49 2025 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ED9A298987 for ; Tue, 29 Jul 2025 15:38:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803516; cv=none; b=s9MNpGDOwQ0UoNpw6PqVrTDLQRAjbFEKpMCv0N+TuIYgEZrn9zOntSys6yBnFJjlZo88n5HaTwJDTIY/7SFlMntEg/a03eHmr0jkvYGf1+ipEiO+rbpIOD9Q7cKE83oLZxkAaHjf/1Qs8KaHYNN6Mo62FQ1r4IubvvaUWBUHT1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803516; c=relaxed/simple; bh=QUCVYtIMVjY3ZVxvZ5i+HOYe1LGOqs+zz4lLRZ1tucA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U+3TGJvENE5+gH/ZjYZJruEyFZ+K5FA0nZ2PHta1+2eQE1QZfY8koy8yVxK5KoeoESwxWM6cb3/7Tbin9YLZ+jqoqGq5ywbmu2IBN0AEVcWj6qNDDvXylcOl8OujPE9zba6IHoAKgh2WP5zIT8KQ0v2PdYBEAMZ22PQwxxnoSis= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4brzsd70MgzdcB9; Tue, 29 Jul 2025 23:34:13 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id 33A78180B52; Tue, 29 Jul 2025 23:38:27 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:26 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:26 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 5/8] drivers/perf: hisi: Extend the field of tt_core Date: Tue, 29 Jul 2025 23:38:20 +0800 Message-ID: <20250729153823.2026154-6-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" From: Yicong Yang Currently the tt_core's using config1's bit [7, 0] and can not be extended. For some platforms there's more the 8 CPUs sharing the L3 cache. So make tt_core use config2's bit [15, 0] and the remaining bits in config2 is reserved for extension. Signed-off-by: Yicong Yang Signed-off-by: Yushan Wang Reviewed-by: Jonathan Cameron --- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hi= silicon/hisi_uncore_l3c_pmu.c index a372dd2c07b5..39444f11cbad 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -55,10 +55,10 @@ #define L3C_V1_NR_EVENTS 0x59 #define L3C_V2_NR_EVENTS 0xFF =20 -HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_core, config1, 7, 0); HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_req, config1, 10, 8); HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_cfg, config1, 15, 11); HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 16, 16); +HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_core, config2, 15, 0); =20 static void hisi_l3c_pmu_config_req_tracetag(struct perf_event *event) { @@ -397,7 +397,7 @@ static const struct attribute_group hisi_l3c_pmu_v1_for= mat_group =3D { =20 static struct attribute *hisi_l3c_pmu_v2_format_attr[] =3D { HISI_PMU_FORMAT_ATTR(event, "config:0-7"), - HISI_PMU_FORMAT_ATTR(tt_core, "config1:0-7"), + HISI_PMU_FORMAT_ATTR(tt_core, "config2:0-15"), HISI_PMU_FORMAT_ATTR(tt_req, "config1:8-10"), HISI_PMU_FORMAT_ATTR(datasrc_cfg, "config1:11-15"), HISI_PMU_FORMAT_ATTR(datasrc_skt, "config1:16"), --=20 2.33.0 From nobody Sun Oct 5 22:01:49 2025 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBADA298991 for ; Tue, 29 Jul 2025 15:38:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803517; cv=none; b=rIVA8ohmjbHxLn2jHQc3NCHaFupKJ2+e2f0RuEDXsxsht2i7sQFzmDIyAQG2QoewaridkStVT5Cwv59qyKwE/RTqhxEwdrmE9B87VfrBJ7JVhcXfNZsHobOfTRntBZ1eoKVGp7qYh1clCEkuOOyV7U7a55FBjbzT5mfVy0IZ6tA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803517; c=relaxed/simple; bh=pN99BjN2i/SYImCHhpOtr9qgBYd6xWMB1l6p8kiujMc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=St7V8pS+ZFprQc1Le0VoTEuhn2dbtHFD8SxPksYqFFsdOVW62UHli9JDuKgex7zzL/8QDd8Vmz/9Va6n40Kk6/xoMq+f8bwZkvh2nB4cRwOj3bpIUnmRCWzPdQh+DHI3rMbkVeB8NC2GsN4SsRg1nyyWIj/IkV6I2s+FcdDGCq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4brzxJ3x85ztScm; Tue, 29 Jul 2025 23:37:24 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id 6C181140278; Tue, 29 Jul 2025 23:38:27 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:27 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:26 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 6/8] drivers/perf: hisi: Refactor the event configuration of L3C PMU Date: Tue, 29 Jul 2025 23:38:21 +0800 Message-ID: <20250729153823.2026154-7-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" From: Yicong Yang The event register is configured using hisi_pmu::base directly since only one address space is supported for L3C PMU. We need to extend if events configuration locates in different address space. In order to make preparation for such hardware, extract the event register configuration to separate function using hw_perf_event::event_base as each event's base address. Implement a private hisi_uncore_ops::get_event_idx() callback for initialize the event_base besides get the hardware index. No functional changes intended. Signed-off-by: Yicong Yang Signed-off-by: Yushan Wang Reviewed-by: Jonathan Cameron --- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 128 ++++++++++++------- 1 file changed, 83 insertions(+), 45 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hi= silicon/hisi_uncore_l3c_pmu.c index 39444f11cbad..6ac0ea74cda3 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -60,51 +60,86 @@ HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_cfg, config1, 15,= 11); HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 16, 16); HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_core, config2, 15, 0); =20 -static void hisi_l3c_pmu_config_req_tracetag(struct perf_event *event) +static int hisi_l3c_pmu_get_event_idx(struct perf_event *event) { struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + unsigned long *used_mask =3D l3c_pmu->pmu_events.used_mask; + u32 num_counters =3D l3c_pmu->num_counters; + int idx; + + idx =3D find_first_zero_bit(used_mask, num_counters); + if (idx =3D=3D num_counters) + return -EAGAIN; + + set_bit(idx, used_mask); + event->hw.event_base =3D (unsigned long)l3c_pmu->base; + return idx; +} + +static u32 hisi_l3c_pmu_event_readl(struct hw_perf_event *hwc, u32 reg) +{ + return readl((void __iomem *)hwc->event_base + reg); +} + +static void hisi_l3c_pmu_event_writel(struct hw_perf_event *hwc, u32 reg, = u32 val) +{ + writel(val, (void __iomem *)hwc->event_base + reg); +} + +static u64 hisi_l3c_pmu_event_readq(struct hw_perf_event *hwc, u32 reg) +{ + return readq((void __iomem *)hwc->event_base + reg); +} + +static void hisi_l3c_pmu_event_writeq(struct hw_perf_event *hwc, u32 reg, = u64 val) +{ + writeq(val, (void __iomem *)hwc->event_base + reg); +} + +static void hisi_l3c_pmu_config_req_tracetag(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; u32 tt_req =3D hisi_get_tt_req(event); =20 if (tt_req) { u32 val; =20 /* Set request-type for tracetag */ - val =3D readl(l3c_pmu->base + L3C_TRACETAG_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_TRACETAG_CTRL); val |=3D tt_req << L3C_TRACETAG_REQ_SHIFT; val |=3D L3C_TRACETAG_REQ_EN; - writel(val, l3c_pmu->base + L3C_TRACETAG_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_TRACETAG_CTRL, val); =20 /* Enable request-tracetag statistics */ - val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_PERF_CTRL); val |=3D L3C_TRACETAG_EN; - writel(val, l3c_pmu->base + L3C_PERF_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_PERF_CTRL, val); } } =20 static void hisi_l3c_pmu_clear_req_tracetag(struct perf_event *event) { - struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; u32 tt_req =3D hisi_get_tt_req(event); =20 if (tt_req) { u32 val; =20 /* Clear request-type */ - val =3D readl(l3c_pmu->base + L3C_TRACETAG_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_TRACETAG_CTRL); val &=3D ~(tt_req << L3C_TRACETAG_REQ_SHIFT); val &=3D ~L3C_TRACETAG_REQ_EN; - writel(val, l3c_pmu->base + L3C_TRACETAG_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_TRACETAG_CTRL, val); =20 /* Disable request-tracetag statistics */ - val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_PERF_CTRL); val &=3D ~L3C_TRACETAG_EN; - writel(val, l3c_pmu->base + L3C_PERF_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_PERF_CTRL, val); } } =20 static void hisi_l3c_pmu_write_ds(struct perf_event *event, u32 ds_cfg) { - struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; u32 reg, reg_idx, shift, val; int idx =3D hwc->idx; @@ -120,15 +155,15 @@ static void hisi_l3c_pmu_write_ds(struct perf_event *= event, u32 ds_cfg) reg_idx =3D idx % 4; shift =3D 8 * reg_idx; =20 - val =3D readl(l3c_pmu->base + reg); + val =3D hisi_l3c_pmu_event_readl(hwc, reg); val &=3D ~(L3C_DATSRC_MASK << shift); val |=3D ds_cfg << shift; - writel(val, l3c_pmu->base + reg); + hisi_l3c_pmu_event_writel(hwc, reg, val); } =20 static void hisi_l3c_pmu_config_ds(struct perf_event *event) { - struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; u32 ds_cfg =3D hisi_get_datasrc_cfg(event); u32 ds_skt =3D hisi_get_datasrc_skt(event); =20 @@ -138,15 +173,15 @@ static void hisi_l3c_pmu_config_ds(struct perf_event = *event) if (ds_skt) { u32 val; =20 - val =3D readl(l3c_pmu->base + L3C_DATSRC_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_DATSRC_CTRL); val |=3D L3C_DATSRC_SKT_EN; - writel(val, l3c_pmu->base + L3C_DATSRC_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_DATSRC_CTRL, val); } } =20 static void hisi_l3c_pmu_clear_ds(struct perf_event *event) { - struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; u32 ds_cfg =3D hisi_get_datasrc_cfg(event); u32 ds_skt =3D hisi_get_datasrc_skt(event); =20 @@ -156,51 +191,51 @@ static void hisi_l3c_pmu_clear_ds(struct perf_event *= event) if (ds_skt) { u32 val; =20 - val =3D readl(l3c_pmu->base + L3C_DATSRC_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_DATSRC_CTRL); val &=3D ~L3C_DATSRC_SKT_EN; - writel(val, l3c_pmu->base + L3C_DATSRC_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_DATSRC_CTRL, val); } } =20 static void hisi_l3c_pmu_config_core_tracetag(struct perf_event *event) { - struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; u32 core =3D hisi_get_tt_core(event); =20 if (core) { u32 val; =20 /* Config and enable core information */ - writel(core, l3c_pmu->base + L3C_CORE_CTRL); - val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_CORE_CTRL, core); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_PERF_CTRL); val |=3D L3C_CORE_EN; - writel(val, l3c_pmu->base + L3C_PERF_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_PERF_CTRL, val); =20 /* Enable core-tracetag statistics */ - val =3D readl(l3c_pmu->base + L3C_TRACETAG_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_TRACETAG_CTRL); val |=3D L3C_TRACETAG_CORE_EN; - writel(val, l3c_pmu->base + L3C_TRACETAG_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_TRACETAG_CTRL, val); } } =20 static void hisi_l3c_pmu_clear_core_tracetag(struct perf_event *event) { - struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; u32 core =3D hisi_get_tt_core(event); =20 if (core) { u32 val; =20 /* Clear core information */ - writel(L3C_COER_NONE, l3c_pmu->base + L3C_CORE_CTRL); - val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_CORE_CTRL, L3C_COER_NONE); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_PERF_CTRL); val &=3D ~L3C_CORE_EN; - writel(val, l3c_pmu->base + L3C_PERF_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_PERF_CTRL, val); =20 /* Disable core-tracetag statistics */ - val =3D readl(l3c_pmu->base + L3C_TRACETAG_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_TRACETAG_CTRL); val &=3D ~L3C_TRACETAG_CORE_EN; - writel(val, l3c_pmu->base + L3C_TRACETAG_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_TRACETAG_CTRL, val); } } =20 @@ -239,18 +274,19 @@ static u32 hisi_l3c_pmu_get_counter_offset(int cntr_i= dx) static u64 hisi_l3c_pmu_read_counter(struct hisi_pmu *l3c_pmu, struct hw_perf_event *hwc) { - return readq(l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(hwc->idx)); + return hisi_l3c_pmu_event_readq(hwc, hisi_l3c_pmu_get_counter_offset(hwc-= >idx)); } =20 static void hisi_l3c_pmu_write_counter(struct hisi_pmu *l3c_pmu, struct hw_perf_event *hwc, u64 val) { - writeq(val, l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(hwc->idx)); + hisi_l3c_pmu_event_writeq(hwc, hisi_l3c_pmu_get_counter_offset(hwc->idx),= val); } =20 static void hisi_l3c_pmu_write_evtype(struct hisi_pmu *l3c_pmu, int idx, u32 type) { + struct hw_perf_event *hwc =3D &l3c_pmu->pmu_events.hw_events[idx]->hw; u32 reg, reg_idx, shift, val; =20 /* @@ -265,10 +301,10 @@ static void hisi_l3c_pmu_write_evtype(struct hisi_pmu= *l3c_pmu, int idx, shift =3D 8 * reg_idx; =20 /* Write event code to L3C_EVENT_TYPEx Register */ - val =3D readl(l3c_pmu->base + reg); + val =3D hisi_l3c_pmu_event_readl(hwc, reg); val &=3D ~(L3C_EVTYPE_NONE << shift); val |=3D (type << shift); - writel(val, l3c_pmu->base + reg); + hisi_l3c_pmu_event_writel(hwc, reg, val); } =20 static void hisi_l3c_pmu_start_counters(struct hisi_pmu *l3c_pmu) @@ -303,9 +339,9 @@ static void hisi_l3c_pmu_enable_counter(struct hisi_pmu= *l3c_pmu, u32 val; =20 /* Enable counter index in L3C_EVENT_CTRL register */ - val =3D readl(l3c_pmu->base + L3C_EVENT_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_EVENT_CTRL); val |=3D (1 << hwc->idx); - writel(val, l3c_pmu->base + L3C_EVENT_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_EVENT_CTRL, val); } =20 static void hisi_l3c_pmu_disable_counter(struct hisi_pmu *l3c_pmu, @@ -314,9 +350,9 @@ static void hisi_l3c_pmu_disable_counter(struct hisi_pm= u *l3c_pmu, u32 val; =20 /* Clear counter index in L3C_EVENT_CTRL register */ - val =3D readl(l3c_pmu->base + L3C_EVENT_CTRL); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_EVENT_CTRL); val &=3D ~(1 << hwc->idx); - writel(val, l3c_pmu->base + L3C_EVENT_CTRL); + hisi_l3c_pmu_event_writel(hwc, L3C_EVENT_CTRL, val); } =20 static void hisi_l3c_pmu_enable_counter_int(struct hisi_pmu *l3c_pmu, @@ -324,10 +360,10 @@ static void hisi_l3c_pmu_enable_counter_int(struct hi= si_pmu *l3c_pmu, { u32 val; =20 - val =3D readl(l3c_pmu->base + L3C_INT_MASK); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_INT_MASK); /* Write 0 to enable interrupt */ val &=3D ~(1 << hwc->idx); - writel(val, l3c_pmu->base + L3C_INT_MASK); + hisi_l3c_pmu_event_writel(hwc, L3C_INT_MASK, val); } =20 static void hisi_l3c_pmu_disable_counter_int(struct hisi_pmu *l3c_pmu, @@ -335,10 +371,10 @@ static void hisi_l3c_pmu_disable_counter_int(struct h= isi_pmu *l3c_pmu, { u32 val; =20 - val =3D readl(l3c_pmu->base + L3C_INT_MASK); + val =3D hisi_l3c_pmu_event_readl(hwc, L3C_INT_MASK); /* Write 1 to mask interrupt */ val |=3D (1 << hwc->idx); - writel(val, l3c_pmu->base + L3C_INT_MASK); + hisi_l3c_pmu_event_writel(hwc, L3C_INT_MASK, val); } =20 static u32 hisi_l3c_pmu_get_int_status(struct hisi_pmu *l3c_pmu) @@ -348,7 +384,9 @@ static u32 hisi_l3c_pmu_get_int_status(struct hisi_pmu = *l3c_pmu) =20 static void hisi_l3c_pmu_clear_int_status(struct hisi_pmu *l3c_pmu, int id= x) { - writel(1 << idx, l3c_pmu->base + L3C_INT_CLEAR); + struct hw_perf_event *hwc =3D &l3c_pmu->pmu_events.hw_events[idx]->hw; + + hisi_l3c_pmu_event_writel(hwc, L3C_INT_CLEAR, 1 << idx); } =20 static int hisi_l3c_pmu_init_data(struct platform_device *pdev, @@ -474,7 +512,7 @@ static const struct hisi_pmu_dev_info hisi_l3c_pmu_v2 = =3D { =20 static const struct hisi_uncore_ops hisi_uncore_l3c_ops =3D { .write_evtype =3D hisi_l3c_pmu_write_evtype, - .get_event_idx =3D hisi_uncore_pmu_get_event_idx, + .get_event_idx =3D hisi_l3c_pmu_get_event_idx, .start_counters =3D hisi_l3c_pmu_start_counters, .stop_counters =3D hisi_l3c_pmu_stop_counters, .enable_counter =3D hisi_l3c_pmu_enable_counter, --=20 2.33.0 From nobody Sun Oct 5 22:01:49 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C016D293C74 for ; Tue, 29 Jul 2025 15:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803513; cv=none; b=aZuOk3bUJD8x1JhzAyRnskU43U0+WNgo1eHBNYxAHY9GVsuxqwMx/rLGUhzODeNSQMIMgv1LOeZ4Td5RAwtechn+7H0iMXBppk6taLrG50Wpb9/c4x4OEuVcO2Zput7oUeyr8IZQU42ZJTsOlMWOMj5NHjd02Ucgm/tmdfVEDTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803513; c=relaxed/simple; bh=oOQjPJMc+puu6JJ+pTquZYygPv8zu0xHC2r/deJIB4I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ky/T1WDZs4nqDMyTZi98RonlaVEkgE9fkiVbr2+h+fYunt91AfHx2ZG60zHjfdFedMqv6AMfELCCs1raxC1bWFnlbHJ9kqmvuYB5qypESkT+Fb4d/tF/ooi6axaB53blISnkhBfVM3cgvH6KPnJClO1zORUMkS7rt8zewO6awHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4brzvp4lj1z2RW1x; Tue, 29 Jul 2025 23:36:06 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id 03AC11A016C; Tue, 29 Jul 2025 23:38:28 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:27 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:27 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 7/8] drivers/perf: hisi: Add support for L3C PMU v3 Date: Tue, 29 Jul 2025 23:38:22 +0800 Message-ID: <20250729153823.2026154-8-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" From: Yicong Yang This patch adds support for L3C PMU v3. The v3 L3C PMU supports an extended events space which can be controlled in up to 2 extra address spaces with separate overflow interrupts. The layout of the control/event registers are kept the same. The extended events with original ones together cover the monitoring job of all transactions on L3C. The extended events is specified with `ext=3D[1|2]` option for the driver to distinguish, like below: perf stat -e hisi_sccl0_l3c0_0/event=3D,ext=3D1/ Currently only event option using config bit [7, 0]. There's still plenty unused space. Make ext using config [16, 17] and reserve bit [15, 8] for event option for future extension. With the capability of extra counters, number of counters for HiSilicon uncore PMU could reach up to 24, the usedmap is extended accordingly. The hw_perf_event::event_base is initialized to the base MMIO address of the event and will be used for later control, overflow handling and counts readout. We still make use of the Uncore PMU framework for handling the events and interrupt migration on CPU hotplug. The framework's cpuhp callback will handle the event migration and interrupt migration of orginial event, if PMU supports extended events then the interrupt of extended events is migrated to the same CPU choosed by the framework. A new HID of HISI0215 is used for this version of L3C PMU. Signed-off-by: Yicong Yang Co-developed-by: Yushan Wang Signed-off-by: Yushan Wang --- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 360 +++++++++++++++++-- drivers/perf/hisilicon/hisi_uncore_pmu.h | 2 +- 2 files changed, 329 insertions(+), 33 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hi= silicon/hisi_uncore_l3c_pmu.c index 6ac0ea74cda3..414c923f4ddf 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -55,24 +55,84 @@ #define L3C_V1_NR_EVENTS 0x59 #define L3C_V2_NR_EVENTS 0xFF =20 +#define L3C_MAX_EXT 2 + +HISI_PMU_EVENT_ATTR_EXTRACTOR(ext, config, 17, 16); HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_req, config1, 10, 8); HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_cfg, config1, 15, 11); HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 16, 16); HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_core, config2, 15, 0); =20 +struct hisi_l3c_pmu { + struct hisi_pmu l3c_pmu; + + /* MMIO and IRQ resources for extension events */ + void __iomem *ext_base[L3C_MAX_EXT]; + int ext_irq[L3C_MAX_EXT]; + int ext_num; +}; + +#define to_hisi_l3c_pmu(_l3c_pmu) \ + container_of(_l3c_pmu, struct hisi_l3c_pmu, l3c_pmu) + +/* + * The hardware counter idx used in counter enable/disable, + * interrupt enable/disable and status check, etc. + */ +#define L3C_HW_IDX(_idx) ((_idx) % L3C_NR_COUNTERS) + +/* The ext resource number to which a hardware counter belongs. */ +#define L3C_CNTR_EXT(_idx) ((_idx) / L3C_NR_COUNTERS) + +struct hisi_l3c_pmu_ext { + bool support_ext; +}; + +static inline bool support_ext(struct hisi_l3c_pmu *pmu) +{ + return ((struct hisi_l3c_pmu_ext *)pmu->l3c_pmu.dev_info->private)->suppo= rt_ext; +} + static int hisi_l3c_pmu_get_event_idx(struct perf_event *event) { struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); unsigned long *used_mask =3D l3c_pmu->pmu_events.used_mask; - u32 num_counters =3D l3c_pmu->num_counters; + int ext =3D hisi_get_ext(event); int idx; =20 - idx =3D find_first_zero_bit(used_mask, num_counters); - if (idx =3D=3D num_counters) + /* + * For an L3C PMU that supports extension events, we can monitor + * maximum 2 * num_counters to 3 * num_counters events, depending on + * the number of ext regions supported by hardware. Thus use bit + * [0, num_counters - 1] for normal events and bit + * [ext * num_counters, (ext + 1) * num_counters - 1] for extension + * events. The idx allocation will keep unchanged for normal events and + * we can also use the idx to distinguish whether it's an extension + * event or not. + * + * Since normal events and extension events locates on the different + * address space, save the base address to the event->hw.event_base. + */ + if (ext) { + if (!support_ext(hisi_l3c_pmu)) + return -EOPNOTSUPP; + + event->hw.event_base =3D (unsigned long)hisi_l3c_pmu->ext_base[ext - 1]; + idx =3D find_next_zero_bit(used_mask, L3C_NR_COUNTERS * (ext + 1), + L3C_NR_COUNTERS * ext); + } else { + event->hw.event_base =3D (unsigned long)l3c_pmu->base; + idx =3D find_next_zero_bit(used_mask, L3C_NR_COUNTERS, 0); + } + + if (idx >=3D L3C_NR_COUNTERS * (ext + 1)) return -EAGAIN; =20 set_bit(idx, used_mask); - event->hw.event_base =3D (unsigned long)l3c_pmu->base; + + WARN_ON(idx < L3C_NR_COUNTERS * ext || idx >=3D L3C_NR_COUNTERS * (ext + = 1)); + return idx; } =20 @@ -142,7 +202,7 @@ static void hisi_l3c_pmu_write_ds(struct perf_event *ev= ent, u32 ds_cfg) { struct hw_perf_event *hwc =3D &event->hw; u32 reg, reg_idx, shift, val; - int idx =3D hwc->idx; + int idx =3D L3C_HW_IDX(hwc->idx); =20 /* * Select the appropriate datasource register(L3C_DATSRC_TYPE0/1). @@ -263,12 +323,21 @@ static void hisi_l3c_pmu_disable_filter(struct perf_e= vent *event) } } =20 +static int hisi_l3c_pmu_check_filter(struct perf_event *event) +{ + struct hisi_pmu *l3c_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + int ext =3D hisi_get_ext(event); + + return ext < 0 || ext > hisi_l3c_pmu->ext_num; +} + /* * Select the counter register offset using the counter index */ static u32 hisi_l3c_pmu_get_counter_offset(int cntr_idx) { - return (L3C_CNTR0_LOWER + (cntr_idx * 8)); + return (L3C_CNTR0_LOWER + (L3C_HW_IDX(cntr_idx) * 8)); } =20 static u64 hisi_l3c_pmu_read_counter(struct hisi_pmu *l3c_pmu, @@ -289,6 +358,8 @@ static void hisi_l3c_pmu_write_evtype(struct hisi_pmu *= l3c_pmu, int idx, struct hw_perf_event *hwc =3D &l3c_pmu->pmu_events.hw_events[idx]->hw; u32 reg, reg_idx, shift, val; =20 + idx =3D L3C_HW_IDX(idx); + /* * Select the appropriate event select register(L3C_EVENT_TYPE0/1). * There are 2 event select registers for the 8 hardware counters. @@ -309,28 +380,62 @@ static void hisi_l3c_pmu_write_evtype(struct hisi_pmu= *l3c_pmu, int idx, =20 static void hisi_l3c_pmu_start_counters(struct hisi_pmu *l3c_pmu) { + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + unsigned long *used_mask =3D l3c_pmu->pmu_events.used_mask; + unsigned long bit =3D find_first_bit(used_mask, l3c_pmu->num_counters); u32 val; + int i; =20 /* - * Set perf_enable bit in L3C_PERF_CTRL register to start counting - * for all enabled counters. + * Check if any counter belongs to the normal range (instead of ext + * range). If so, enable it. */ - val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); - val |=3D L3C_PERF_CTRL_EN; - writel(val, l3c_pmu->base + L3C_PERF_CTRL); + if (bit < L3C_NR_COUNTERS) { + val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); + val |=3D L3C_PERF_CTRL_EN; + writel(val, l3c_pmu->base + L3C_PERF_CTRL); + } + + /* If not, do enable it on ext ranges. */ + for (i =3D 0; i < hisi_l3c_pmu->ext_num; i++) { + bit =3D find_next_bit(used_mask, L3C_NR_COUNTERS * (i + 2), + L3C_NR_COUNTERS * (i + 1)); + if (L3C_CNTR_EXT(bit) =3D=3D i + 1) { + val =3D readl(hisi_l3c_pmu->ext_base[i] + L3C_PERF_CTRL); + val |=3D L3C_PERF_CTRL_EN; + writel(val, hisi_l3c_pmu->ext_base[i] + L3C_PERF_CTRL); + } + } } =20 static void hisi_l3c_pmu_stop_counters(struct hisi_pmu *l3c_pmu) { + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + unsigned long *used_mask =3D l3c_pmu->pmu_events.used_mask; + unsigned long bit =3D find_first_bit(used_mask, l3c_pmu->num_counters); u32 val; + int i; =20 /* - * Clear perf_enable bit in L3C_PERF_CTRL register to stop counting - * for all enabled counters. + * Check if any counter belongs to the normal range (instead of ext + * range). If so, stop it. */ - val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); - val &=3D ~(L3C_PERF_CTRL_EN); - writel(val, l3c_pmu->base + L3C_PERF_CTRL); + if (bit < L3C_NR_COUNTERS) { + val =3D readl(l3c_pmu->base + L3C_PERF_CTRL); + val &=3D ~(L3C_PERF_CTRL_EN); + writel(val, l3c_pmu->base + L3C_PERF_CTRL); + } + + /* If not, do stop it on ext ranges. */ + for (i =3D 0; i < hisi_l3c_pmu->ext_num; i++) { + bit =3D find_next_bit(used_mask, L3C_NR_COUNTERS * (i + 2), + L3C_NR_COUNTERS * (i + 1)); + if (L3C_CNTR_EXT(bit) =3D=3D i + 1) { + val =3D readl(hisi_l3c_pmu->ext_base[i] + L3C_PERF_CTRL); + val &=3D ~L3C_PERF_CTRL_EN; + writel(val, hisi_l3c_pmu->ext_base[i] + L3C_PERF_CTRL); + } + } } =20 static void hisi_l3c_pmu_enable_counter(struct hisi_pmu *l3c_pmu, @@ -340,7 +445,7 @@ static void hisi_l3c_pmu_enable_counter(struct hisi_pmu= *l3c_pmu, =20 /* Enable counter index in L3C_EVENT_CTRL register */ val =3D hisi_l3c_pmu_event_readl(hwc, L3C_EVENT_CTRL); - val |=3D (1 << hwc->idx); + val |=3D (1 << L3C_HW_IDX(hwc->idx)); hisi_l3c_pmu_event_writel(hwc, L3C_EVENT_CTRL, val); } =20 @@ -351,7 +456,7 @@ static void hisi_l3c_pmu_disable_counter(struct hisi_pm= u *l3c_pmu, =20 /* Clear counter index in L3C_EVENT_CTRL register */ val =3D hisi_l3c_pmu_event_readl(hwc, L3C_EVENT_CTRL); - val &=3D ~(1 << hwc->idx); + val &=3D ~(1 << L3C_HW_IDX(hwc->idx)); hisi_l3c_pmu_event_writel(hwc, L3C_EVENT_CTRL, val); } =20 @@ -362,7 +467,7 @@ static void hisi_l3c_pmu_enable_counter_int(struct hisi= _pmu *l3c_pmu, =20 val =3D hisi_l3c_pmu_event_readl(hwc, L3C_INT_MASK); /* Write 0 to enable interrupt */ - val &=3D ~(1 << hwc->idx); + val &=3D ~(1 << L3C_HW_IDX(hwc->idx)); hisi_l3c_pmu_event_writel(hwc, L3C_INT_MASK, val); } =20 @@ -373,20 +478,34 @@ static void hisi_l3c_pmu_disable_counter_int(struct h= isi_pmu *l3c_pmu, =20 val =3D hisi_l3c_pmu_event_readl(hwc, L3C_INT_MASK); /* Write 1 to mask interrupt */ - val |=3D (1 << hwc->idx); + val |=3D (1 << L3C_HW_IDX(hwc->idx)); hisi_l3c_pmu_event_writel(hwc, L3C_INT_MASK, val); } =20 static u32 hisi_l3c_pmu_get_int_status(struct hisi_pmu *l3c_pmu) { - return readl(l3c_pmu->base + L3C_INT_STATUS); + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + u32 status, status_ext =3D 0; + u32 ext_int; + + status =3D readl(l3c_pmu->base + L3C_INT_STATUS); + + if (!support_ext(hisi_l3c_pmu)) + return status; + + for (int i =3D 0; i < hisi_l3c_pmu->ext_num; i++) { + ext_int =3D readl(hisi_l3c_pmu->ext_base[i] + L3C_INT_STATUS); + status_ext |=3D ext_int << (L3C_NR_COUNTERS * i); + } + + return status | (status_ext << L3C_NR_COUNTERS); } =20 static void hisi_l3c_pmu_clear_int_status(struct hisi_pmu *l3c_pmu, int id= x) { struct hw_perf_event *hwc =3D &l3c_pmu->pmu_events.hw_events[idx]->hw; =20 - hisi_l3c_pmu_event_writel(hwc, L3C_INT_CLEAR, 1 << idx); + hisi_l3c_pmu_event_writel(hwc, L3C_INT_CLEAR, 1 << L3C_HW_IDX(idx)); } =20 static int hisi_l3c_pmu_init_data(struct platform_device *pdev, @@ -408,10 +527,6 @@ static int hisi_l3c_pmu_init_data(struct platform_devi= ce *pdev, return -EINVAL; } =20 - l3c_pmu->dev_info =3D device_get_match_data(&pdev->dev); - if (!l3c_pmu->dev_info) - return -ENODEV; - l3c_pmu->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(l3c_pmu->base)) { dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n"); @@ -423,6 +538,48 @@ static int hisi_l3c_pmu_init_data(struct platform_devi= ce *pdev, return 0; } =20 +static int hisi_l3c_pmu_init_ext(struct hisi_pmu *l3c_pmu, struct platform= _device *pdev) +{ + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + char *irqname; + int ret, irq; + int ext_num; + int i; + + /* HiSilicon L3C PMU ext should have more than 1 irq resources. */ + ext_num =3D platform_irq_count(pdev); + if (ext_num < 2) + return -ENODEV; + + hisi_l3c_pmu->ext_num =3D ext_num - 1; + + for (i =3D 0; i < hisi_l3c_pmu->ext_num; i++) { + hisi_l3c_pmu->ext_base[i] =3D devm_platform_ioremap_resource(pdev, i + 1= ); + if (IS_ERR(hisi_l3c_pmu->ext_base[i])) + return PTR_ERR(hisi_l3c_pmu->ext_base[i]); + + irq =3D platform_get_irq(pdev, i + 1); + if (irq < 0) + return irq; + + irqname =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s ext%d", + dev_name(&pdev->dev), i + 1); + if (!irqname) + return -ENOMEM; + + ret =3D devm_request_irq(&pdev->dev, irq, hisi_uncore_pmu_isr, + IRQF_NOBALANCING | IRQF_NO_THREAD, + irqname, l3c_pmu); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Fail to request EXT IRQ: %d.\n", irq); + + hisi_l3c_pmu->ext_irq[i] =3D irq; + } + + return 0; +} + static struct attribute *hisi_l3c_pmu_v1_format_attr[] =3D { HISI_PMU_FORMAT_ATTR(event, "config:0-7"), NULL, @@ -447,6 +604,19 @@ static const struct attribute_group hisi_l3c_pmu_v2_fo= rmat_group =3D { .attrs =3D hisi_l3c_pmu_v2_format_attr, }; =20 +static struct attribute *hisi_l3c_pmu_v3_format_attr[] =3D { + HISI_PMU_FORMAT_ATTR(event, "config:0-7"), + HISI_PMU_FORMAT_ATTR(ext, "config:16-17"), + HISI_PMU_FORMAT_ATTR(tt_req, "config1:8-10"), + HISI_PMU_FORMAT_ATTR(tt_core, "config2:0-15"), + NULL +}; + +static const struct attribute_group hisi_l3c_pmu_v3_format_group =3D { + .name =3D "format", + .attrs =3D hisi_l3c_pmu_v3_format_attr, +}; + static struct attribute *hisi_l3c_pmu_v1_events_attr[] =3D { HISI_PMU_EVENT_ATTR(rd_cpipe, 0x00), HISI_PMU_EVENT_ATTR(wr_cpipe, 0x01), @@ -482,6 +652,26 @@ static const struct attribute_group hisi_l3c_pmu_v2_ev= ents_group =3D { .attrs =3D hisi_l3c_pmu_v2_events_attr, }; =20 +static struct attribute *hisi_l3c_pmu_v3_events_attr[] =3D { + HISI_PMU_EVENT_ATTR(rd_spipe, 0x18), + HISI_PMU_EVENT_ATTR(rd_hit_spipe, 0x19), + HISI_PMU_EVENT_ATTR(wr_spipe, 0x1a), + HISI_PMU_EVENT_ATTR(wr_hit_spipe, 0x1b), + HISI_PMU_EVENT_ATTR(io_rd_spipe, 0x1c), + HISI_PMU_EVENT_ATTR(io_rd_hit_spipe, 0x1d), + HISI_PMU_EVENT_ATTR(io_wr_spipe, 0x1e), + HISI_PMU_EVENT_ATTR(io_wr_hit_spipe, 0x1f), + HISI_PMU_EVENT_ATTR(cycles, 0x7f), + HISI_PMU_EVENT_ATTR(l3c_ref, 0xbc), + HISI_PMU_EVENT_ATTR(l3c2ring, 0xbd), + NULL +}; + +static const struct attribute_group hisi_l3c_pmu_v3_events_group =3D { + .name =3D "events", + .attrs =3D hisi_l3c_pmu_v3_events_attr, +}; + static const struct attribute_group *hisi_l3c_pmu_v1_attr_groups[] =3D { &hisi_l3c_pmu_v1_format_group, &hisi_l3c_pmu_v1_events_group, @@ -498,16 +688,41 @@ static const struct attribute_group *hisi_l3c_pmu_v2_= attr_groups[] =3D { NULL }; =20 +static const struct attribute_group *hisi_l3c_pmu_v3_attr_groups[] =3D { + &hisi_l3c_pmu_v3_format_group, + &hisi_l3c_pmu_v3_events_group, + &hisi_pmu_cpumask_attr_group, + &hisi_pmu_identifier_group, + NULL +}; + +static struct hisi_l3c_pmu_ext hisi_l3c_pmu_support_ext =3D { + .support_ext =3D true, +}; + +static struct hisi_l3c_pmu_ext hisi_l3c_pmu_not_support_ext =3D { + .support_ext =3D false, +}; + static const struct hisi_pmu_dev_info hisi_l3c_pmu_v1 =3D { .attr_groups =3D hisi_l3c_pmu_v1_attr_groups, .counter_bits =3D 48, .check_event =3D L3C_V1_NR_EVENTS, + .private =3D &hisi_l3c_pmu_not_support_ext, }; =20 static const struct hisi_pmu_dev_info hisi_l3c_pmu_v2 =3D { .attr_groups =3D hisi_l3c_pmu_v2_attr_groups, .counter_bits =3D 64, .check_event =3D L3C_V2_NR_EVENTS, + .private =3D &hisi_l3c_pmu_not_support_ext, +}; + +static const struct hisi_pmu_dev_info hisi_l3c_pmu_v3 =3D { + .attr_groups =3D hisi_l3c_pmu_v3_attr_groups, + .counter_bits =3D 64, + .check_event =3D L3C_V2_NR_EVENTS, + .private =3D &hisi_l3c_pmu_support_ext, }; =20 static const struct hisi_uncore_ops hisi_uncore_l3c_ops =3D { @@ -525,11 +740,15 @@ static const struct hisi_uncore_ops hisi_uncore_l3c_o= ps =3D { .clear_int_status =3D hisi_l3c_pmu_clear_int_status, .enable_filter =3D hisi_l3c_pmu_enable_filter, .disable_filter =3D hisi_l3c_pmu_disable_filter, + .check_filter =3D hisi_l3c_pmu_check_filter, }; =20 static int hisi_l3c_pmu_dev_probe(struct platform_device *pdev, struct hisi_pmu *l3c_pmu) { + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + struct hisi_l3c_pmu_ext *l3c_pmu_dev_ext =3D + (struct hisi_l3c_pmu_ext *)l3c_pmu->dev_info->private; int ret; =20 ret =3D hisi_l3c_pmu_init_data(pdev, l3c_pmu); @@ -548,27 +767,50 @@ static int hisi_l3c_pmu_dev_probe(struct platform_dev= ice *pdev, l3c_pmu->dev =3D &pdev->dev; l3c_pmu->on_cpu =3D -1; =20 + if (l3c_pmu_dev_ext->support_ext) { + ret =3D hisi_l3c_pmu_init_ext(l3c_pmu, pdev); + if (ret) + return ret; + /* + * The extension events have their own counters with the + * same number of the normal events counters. So we can + * have at maximum num_counters * ext events monitored. + */ + l3c_pmu->num_counters +=3D hisi_l3c_pmu->ext_num * L3C_NR_COUNTERS; + } + return 0; } =20 static int hisi_l3c_pmu_probe(struct platform_device *pdev) { + struct hisi_l3c_pmu *hisi_l3c_pmu; struct hisi_pmu *l3c_pmu; char *name; int ret; =20 - l3c_pmu =3D devm_kzalloc(&pdev->dev, sizeof(*l3c_pmu), GFP_KERNEL); - if (!l3c_pmu) + hisi_l3c_pmu =3D devm_kzalloc(&pdev->dev, sizeof(*hisi_l3c_pmu), GFP_KERN= EL); + if (!hisi_l3c_pmu) return -ENOMEM; =20 + l3c_pmu =3D &hisi_l3c_pmu->l3c_pmu; platform_set_drvdata(pdev, l3c_pmu); =20 + l3c_pmu->dev_info =3D device_get_match_data(&pdev->dev); + if (!l3c_pmu->dev_info) + return -ENODEV; + ret =3D hisi_l3c_pmu_dev_probe(pdev, l3c_pmu); if (ret) return ret; =20 - name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%d_l3c%d", - l3c_pmu->topo.sccl_id, l3c_pmu->topo.ccl_id); + if (l3c_pmu->topo.sub_id >=3D 0) + name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%d_l3c%d_%d", + l3c_pmu->topo.sccl_id, l3c_pmu->topo.ccl_id, + l3c_pmu->topo.sub_id); + else + name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%d_l3c%d", + l3c_pmu->topo.sccl_id, l3c_pmu->topo.ccl_id); if (!name) return -ENOMEM; =20 @@ -603,6 +845,7 @@ static void hisi_l3c_pmu_remove(struct platform_device = *pdev) static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] =3D { { "HISI0213", (kernel_ulong_t)&hisi_l3c_pmu_v1 }, { "HISI0214", (kernel_ulong_t)&hisi_l3c_pmu_v2 }, + { "HISI0215", (kernel_ulong_t)&hisi_l3c_pmu_v3 }, {} }; MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match); @@ -617,14 +860,67 @@ static struct platform_driver hisi_l3c_pmu_driver =3D= { .remove =3D hisi_l3c_pmu_remove, }; =20 +static int hisi_l3c_pmu_online_cpu(unsigned int cpu, struct hlist_node *no= de) +{ + struct hisi_pmu *l3c_pmu =3D hlist_entry_safe(node, struct hisi_pmu, node= ); + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + int ret; + + /* + * Invoking the framework's online function for doing the core logic + * of CPU, interrupt and perf context migrating. Then return directly + * if we don't support L3C_PMU_FEAT_EXT. Otherwise migrate the ext_irq + * using the migrated CPU. + * + * Same logic for CPU offline. + */ + ret =3D hisi_uncore_pmu_online_cpu(cpu, node); + if (ret) + return ret; + + /* Avoid L3C pmu not supporting ext from ext irq migrating. */ + if (!support_ext(hisi_l3c_pmu)) + return 0; + + for (int i =3D 0; i < hisi_l3c_pmu->ext_num; i++) + WARN_ON(irq_set_affinity(hisi_l3c_pmu->ext_irq[i], + cpumask_of(l3c_pmu->on_cpu))); + return 0; +} + +static int hisi_l3c_pmu_offline_cpu(unsigned int cpu, struct hlist_node *n= ode) +{ + struct hisi_pmu *l3c_pmu =3D hlist_entry_safe(node, struct hisi_pmu, node= ); + struct hisi_l3c_pmu *hisi_l3c_pmu =3D to_hisi_l3c_pmu(l3c_pmu); + int ret; + + ret =3D hisi_uncore_pmu_offline_cpu(cpu, node); + if (ret) + return ret; + + if (l3c_pmu->on_cpu >=3D nr_cpu_ids) { + disable_irq(l3c_pmu->irq); + return 0; + } + + /* Avoid L3C pmu not supporting ext from ext irq migrating. */ + if (!support_ext(hisi_l3c_pmu)) + return 0; + + for (int i =3D 0; i < hisi_l3c_pmu->ext_num; i++) + WARN_ON(irq_set_affinity(hisi_l3c_pmu->ext_irq[i], + cpumask_of(l3c_pmu->on_cpu))); + return 0; +} + static int __init hisi_l3c_pmu_module_init(void) { int ret; =20 ret =3D cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, "AP_PERF_ARM_HISI_L3_ONLINE", - hisi_uncore_pmu_online_cpu, - hisi_uncore_pmu_offline_cpu); + hisi_l3c_pmu_online_cpu, + hisi_l3c_pmu_offline_cpu); if (ret) { pr_err("L3C PMU: Error setup hotplug, ret =3D %d\n", ret); return ret; diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisili= con/hisi_uncore_pmu.h index 40aac70352e9..a65de3b30397 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.h +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h @@ -24,7 +24,7 @@ #define pr_fmt(fmt) "hisi_pmu: " fmt =20 #define HISI_PMU_V2 0x30 -#define HISI_MAX_COUNTERS 0x10 +#define HISI_MAX_COUNTERS 0x18 #define to_hisi_pmu(p) (container_of(p, struct hisi_pmu, pmu)) =20 #define HISI_PMU_ATTR(_name, _func, _config) \ --=20 2.33.0 From nobody Sun Oct 5 22:01:49 2025 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3CB3293C77 for ; Tue, 29 Jul 2025 15:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803513; cv=none; b=k38BlyNIdjiOdWkZUQkEV4M0Q4LX5Nle0nnm6sOcwIJ8EidzSYbmzXWVwfY9YUA3hizzPAaSx9Ipzl42fjf7MNcKIUPmr2IKMXXAqaqpVZ+jdjvSh3fVcRKzxM59p0B7BqvklV8gbOrgZ0MHia8Cga0nDpZ7xFKkC2Zr0V0j/54= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753803513; c=relaxed/simple; bh=KJzheRQfyRAydciUNWS2xsbioY0FAmSaFYrR9j6Q/EI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=X70lGF8euzM9nSks8UKXcXrW42xRhkcN05eg9qlp/6sXX4SXOctSCbC2kuRBs/3m8grCdyMMN4MBIpt9Z9ZN57Xi5Z/1n2+nFdXWjMrTfo8mj9mQz7wqRL+LisKu6/NkSyhQmV2ZtJoKCukG+FD8xU/umxK2PfozJWFOf/K2W1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4brzvq2FLVz23jcW; Tue, 29 Jul 2025 23:36:07 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id 31C2B1A016C; Tue, 29 Jul 2025 23:38:28 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:27 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 29 Jul 2025 23:38:27 +0800 From: Yushan Wang To: , , , CC: , , , , , Subject: [PATCH 8/8] Documentation: hisi-pmu: Add introduction to HiSilicon V3 PMU Date: Tue, 29 Jul 2025 23:38:23 +0800 Message-ID: <20250729153823.2026154-9-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250729153823.2026154-1-wangyushan12@huawei.com> References: <20250729153823.2026154-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" Some of HiSilicon V3 PMU hardware is divided into parts to fulfill the job of monitoring specific parts of a device. Add description on that as well as the newly added ext operand for L3C PMU. Signed-off-by: Yushan Wang Reviewed-by: Jonathan Cameron --- Documentation/admin-guide/perf/hisi-pmu.rst | 43 +++++++++++++++++++-- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/ad= min-guide/perf/hisi-pmu.rst index 48992a0b8e94..4c7584fe3c1a 100644 --- a/Documentation/admin-guide/perf/hisi-pmu.rst +++ b/Documentation/admin-guide/perf/hisi-pmu.rst @@ -12,15 +12,16 @@ The HiSilicon SoC encapsulates multiple CPU and IO dies= . Each CPU cluster called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has two HHAs (0 - 1) and four DDRCs (0 - 3), respectively. =20 -HiSilicon SoC uncore PMU driver -------------------------------- +HiSilicon SoC uncore PMU v1 +--------------------------- =20 Each device PMU has separate registers for event counting, control and interrupt, and the PMU driver shall register perf PMU drivers like L3C, HHA and DDRC etc. The available events and configuration options shall -be described in the sysfs, see: +be described in the sysfs, see:: + +/sys/bus/event_source/devices/hisi_sccl{X}_ =20 -/sys/bus/event_source/devices/hisi_sccl{X}_. The "perf list" command shall list the available events from sysfs. =20 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU @@ -55,6 +56,9 @@ Example usage of perf:: $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 $# perf stat -a -e hisi_sccl3_l3c0/config=3D0x02/ sleep 5 =20 +HiSilicon SoC uncore PMU v2 +---------------------------------- + For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the = same as PMU v1, but some new functions are added to the hardware. =20 @@ -112,6 +116,37 @@ uring channel. It is 2 bits. Some important codes are = as follows: - 2'b00: default value, count the events which sent to the both uring and uring_ext channel; =20 +HiSilicon SoC uncore PMU v3 +---------------------------------- + +For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are +further divided into parts for finer granularity of tracing, each part has= its +own dedicated PMU, and all such PMUs together cover the monitoring job of = events +on particular uncore device. Such PMUs are described in sysfs with name fo= rmat +slightly changed:: + +/sys/bus/event_source/devices/hisi_sccl{X}_ + +Z is the sub-id, indicating different PMUs for part of hardware device. + +Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU +provides ``ext`` operand to allow exploration of even finer granual statis= tics +of L3C PMU, L3C PMU driver use that as hint of termination when delivering= perf +command to hardware: + +- ext=3D0: Default, could be used with event names. +- ext=3D1 and ext=3D2: Must be used with event codes, event names are not = supported. + +An example of perf command could be:: + + $# perf stat -a -e hisi_sccl0_l3c1_0/event=3D0x1,ext=3D1/ sleep 5 + +or:: + + $# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5 + +As above, ``hisi_sccl0_l3c1_0`` locates PMU on CPU cluster 0, L3 cache 1 p= ipe0. + Users could configure IDs to count data come from specific CCL/ICL, by set= ting srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will= not --=20 2.33.0